minor fixes

Change-Id: I4be15d264e402be000811dffc1b28a2bc93ab297
Reviewed-on: https://forge.frm2.tum.de/review/18941
Tested-by: JenkinsCodeReview <bjoern_pedersen@frm2.tum.de>
Reviewed-by: Enrico Faulhaber <enrico.faulhaber@frm2.tum.de>
This commit is contained in:
Enrico Faulhaber
2018-09-03 12:03:15 +02:00
parent 5f640ce299
commit 7e54cd93b7
10 changed files with 165 additions and 26 deletions

View File

@ -98,6 +98,8 @@ class SimWritable(SimBase, Writable):
def write_target(self, value):
self.value = value
def _hw_wait(self):
pass
class SimDrivable(SimBase, Drivable):
def __init__(self, logger, cfgdict, devname, dispatcher):
@ -126,4 +128,8 @@ class SimDrivable(SimBase, Drivable):
else:
self._value = self.target
sleep(0.3)
self.status = self.Status.OK, ''
self.status = self.Status.IDLE, ''
def _hw_wait(self):
while self.status[0] == self.Status.BUSY:
sleep(0.3)