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fix issue with new syntax in simulation

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for creating extra parameters a subclass of SimBase is created,
in order to treat parameters and read_/write_ methods properly.

Change-Id: I9061b9afb0f8922b36b8f9448c45bb3aadb8f515
Reviewed-on: https://forge.frm2.tum.de/review/c/sine2020/secop/playground/+/25961
Tested-by: Jenkins Automated Tests <pedersen+jenkins@frm2.tum.de>
Reviewed-by: Enrico Faulhaber <enrico.faulhaber@frm2.tum.de>
Reviewed-by: Markus Zolliker <markus.zolliker@psi.ch>
This commit is contained in:
zolliker 2021-05-17 16:36:29 +02:00
parent b0f0a48e51
commit 09411f36f3
1 changed files with 43 additions and 43 deletions
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76
secop/simulation.py
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@ -36,82 +36,82 @@ from secop.modules import BasicPoller, Drivable, \
class SimBase: class SimBase:
pollerClass = BasicPoller pollerClass = BasicPoller
def __init__(self, cfgdict): def __new__(cls, devname, logger, cfgdict, dispatcher):
# spice up parameters if requested by extra property extra_params = cfgdict.pop('extra_params', '') or cfgdict.pop('.extra_params', '')
# hint: us a comma-separated list if mor than one extra_param attrs = {}
# BIG FAT WARNING: changing extra params will NOT generate events! if extra_params:
# XXX: implement default read_* and write_* methods to handle
# read and change messages correctly
if '.extra_params' in cfgdict:
extra_params = cfgdict.pop('.extra_params')
# make a copy of self.parameter # make a copy of self.parameter
self.accessibles = dict((k, v.copy()) for k, v in self.accessibles.items()) # self.accessibles = dict((k, v.copy()) for k, v in self.accessibles.items())
for k in extra_params.split(','): for k in extra_params.split(','):
k = k.strip() k = k.strip()
self.accessibles[k] = Parameter('extra_param: %s' % k.strip(), attrs[k] = Parameter('extra_param: %s' % k.strip(),
datatype=FloatRange(), datatype=FloatRange(),
default=0.0) default=0.0)
def reader(pname=k):
def reader(self, pname=k):
self.log.debug('simulated reading %s' % pname) self.log.debug('simulated reading %s' % pname)
return self.accessibles[pname].value return self.parameters[pname].value
setattr(self, 'read_' + k, reader)
def writer(newval, pname=k): attrs['read_' + k] = reader
def writer(self, newval, pname=k):
self.log.debug('simulated writing %r to %s' % (newval, pname)) self.log.debug('simulated writing %r to %s' % (newval, pname))
self.accessibles[pname].value = newval self.parameters[pname].value = newval
return newval return newval
setattr(self, 'write_' + k, writer)
attrs['write_' + k] = writer
return object.__new__(type('SimBase_%s' % devname, (cls,), attrs))
def initModule(self): def initModule(self):
self._sim_thread = mkthread(self._sim) self._sim_thread = mkthread(self._sim)
def _sim(self): def _sim(self):
try: try:
if not self.sim():
self.log.info('sim thread running')
while not self.sim(): while not self.sim():
pass pass
self.log.info('sim thread ended')
except Exception as e: except Exception as e:
self.log.exception(e) self.log.exception(e)
self.log.info('sim thread ended')
def sim(self): def sim(self):
return True # nothing to do, stop thread return True # nothing to do, stop thread
def read_value(self):
if 'jitter' in self.accessibles:
return self._value + self.jitter*(0.5-random.random())
return self._value
class SimModule(SimBase, Module): class SimModule(SimBase, Module):
def __init__(self, devname, logger, cfgdict, dispatcher): pass
SimBase.__init__(self, cfgdict) # def __init__(self, devname, logger, cfgdict, dispatcher):
Module.__init__(self, devname, logger, cfgdict, dispatcher) # SimBase.__init__(self, cfgdict)
# Module.__init__(self, devname, logger, cfgdict, dispatcher)
class SimReadable(SimBase, Readable): class SimReadable(SimBase, Readable):
def __init__(self, devname, logger, cfgdict, dispatcher): def __init__(self, devname, logger, cfgdict, dispatcher):
SimBase.__init__(self, cfgdict) # SimBase.__init__(self, cfgdict)
Readable.__init__(self, devname, logger, cfgdict, dispatcher) super().__init__(devname, logger, cfgdict, dispatcher)
self._value = self.accessibles['value'].default self._value = self.parameters['value'].default
def read_value(self):
if 'jitter' in self.parameters:
return self._value + self.jitter * (0.5 - random.random())
return self._value
class SimWritable(SimBase, Writable): class SimWritable(SimReadable, Writable):
def __init__(self, devname, logger, cfgdict, dispatcher):
SimBase.__init__(self, cfgdict)
Writable.__init__(self, devname, logger, cfgdict, dispatcher)
self._value = self.accessibles['value'].default
def read_value(self): def read_value(self):
return self.target return self.target
def write_target(self, value): def write_target(self, value):
self.value = value self.value = value
def _hw_wait(self): def _hw_wait(self):
pass pass
class SimDrivable(SimBase, Drivable):
def __init__(self, devname, logger, cfgdict, dispatcher): class SimDrivable(SimReadable, Drivable):
SimBase.__init__(self, cfgdict)
Drivable.__init__(self, devname, logger, cfgdict, dispatcher)
self._value = self.accessibles['value'].default
def sim(self): def sim(self):
while self._value == self.target: while self._value == self.target: