From bf9921ab05d0a5599402f25414530fc619e3c234 Mon Sep 17 00:00:00 2001
From: soederqvist_a <alexander.soederqvist@psi.ch>
Date: Wed, 10 Sep 2025 12:47:56 +0200
Subject: [PATCH] Simulate more correct counter resetting

---
 Makefile       | 2 +-
 sim/daq_sim.py | 8 ++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 56ca12a..320f633 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,7 @@ include /ioc/tools/driver.makefile
 MODULE=sinqDAQ
 BUILDCLASSES=Linux
 EPICS_VERSIONS=7.0.7
-ARCH_FILTER=RHEL%
+ARCH_FILTER=RHEL8%
 
 # additional module dependencies
 REQUIRED+=asyn
diff --git a/sim/daq_sim.py b/sim/daq_sim.py
index 2df6337..9eb1724 100644
--- a/sim/daq_sim.py
+++ b/sim/daq_sim.py
@@ -50,7 +50,7 @@ class DAQ:
         ]
 
     def clearCount(self, counter):
-        self.counts[counter-1] = 0
+        self.counts[counter] = 0
 
     def clearCounts(self):
         self.counts = [0] * self.total_channels
@@ -260,7 +260,11 @@ with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s:
 
                 elif re.fullmatch(r'CC (\d+)', data):
                     counter = int(re.fullmatch(r'CC (\d+)', data).group(1))
-                    daq.clearCount(counter)
+                    num_bits = daq.total_channels
+                    bits = [(counter >> bit) & 1 for bit in range(num_bits - 1, -1, -1)]
+                    for ch, bit in enumerate(bits):
+                        if bit:
+                            daq.clearCount(ch)
                     send('')
 
                 elif re.fullmatch(r'TP (\d+(\.\d+)?)', data):