From 5f86266fc0b5dc1d19376c3935995ae9f46c87f6 Mon Sep 17 00:00:00 2001
From: soederqvist_a <alexander.soederqvist@psi.ch>
Date: Wed, 10 Sep 2025 12:47:56 +0200
Subject: [PATCH] Simulate more correct counter resetting

---
 sim/daq_sim.py | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/sim/daq_sim.py b/sim/daq_sim.py
index 2df6337..9eb1724 100644
--- a/sim/daq_sim.py
+++ b/sim/daq_sim.py
@@ -50,7 +50,7 @@ class DAQ:
         ]
 
     def clearCount(self, counter):
-        self.counts[counter-1] = 0
+        self.counts[counter] = 0
 
     def clearCounts(self):
         self.counts = [0] * self.total_channels
@@ -260,7 +260,11 @@ with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s:
 
                 elif re.fullmatch(r'CC (\d+)', data):
                     counter = int(re.fullmatch(r'CC (\d+)', data).group(1))
-                    daq.clearCount(counter)
+                    num_bits = daq.total_channels
+                    bits = [(counter >> bit) & 1 for bit in range(num_bits - 1, -1, -1)]
+                    for ch, bit in enumerate(bits):
+                        if bit:
+                            daq.clearCount(ch)
                     send('')
 
                 elif re.fullmatch(r'TP (\d+(\.\d+)?)', data):