308 lines
7.0 KiB
C
308 lines
7.0 KiB
C
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/* drvStc.c */
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/* share/src/drv $Id$ */
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/*
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* The following are specific driver routines for the AMD STC
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*
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* NOTE: if multiple threads use these routines at once you must provide locking
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* so command/data sequences are gauranteed. See mz8310_driver.c for examples.
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*
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*
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* Author: Jeff Hill
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* Date: Feb 89
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*
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* Experimental Physics and Industrial Control System (EPICS)
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*
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* Copyright 1991, the Regents of the University of California,
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* and the University of Chicago Board of Governors.
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*
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* This software was produced under U.S. Government contracts:
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* (W-7405-ENG-36) at the Los Alamos National Laboratory,
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* and (W-31-109-ENG-38) at Argonne National Laboratory.
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*
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* Initial development by:
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* The Controls and Automation Group (AT-8)
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* Ground Test Accelerator
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* Accelerator Technology Division
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* Los Alamos National Laboratory
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*
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* Co-developed with
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* The Controls and Computing Group
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* Accelerator Systems Division
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* Advanced Photon Source
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* Argonne National Laboratory
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*
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* Modification Log:
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* -----------------
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*
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* joh 022089 Init Release
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* joh 042889 Added read back
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* joh 111789 Fixed reset goes to byte mode bug
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* joh 121090 Fixed confusion about the polarity of internal/external
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* clock between DB and the drivers.
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* joh 110791 Prevent the stc from generating tc prior to the trigger
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* in delayed pulse mode by forcing edge 0 delays of zero to be
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* a delay of one instead.
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* joh 010491 force all edge 0 delays less than two to two
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* bg 062692 force all edge 0 delays less than two to two
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*/
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/* drvStc.c - Driver Support Routines for Stc */
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#include <vxWorks.h>
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#include <stdioLib.h>
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#include <dbDefs.h>
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#include <drvSup.h>
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#include <module_types.h>
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/* If any of the following does not exist replace it with #define <> NULL */
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static long report();
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static long init();
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struct {
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long number;
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DRVSUPFUN report;
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DRVSUPFUN init;
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} drvStc={
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2,
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report,
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init};
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static long report(fp)
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FILE *fp;
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{
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return(0);
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}
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static long init()
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{
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int status;
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return(0);
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}
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#define CHANONCHIP 5
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#define CHIPCHAN (channel%CHANONCHIP)
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#define CHIPNUM (channel/CHANONCHIP)
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#define STC_RESET *pcmd = 0xff
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#define STC_BUS16 *pcmd = 0xef
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#define STC_SET_MASTER_MODE(D) {*pcmd = 0x17; *pdata=(D);}
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#define STC_MASTER_MODE (*pcmd = 0x17, *pdata)
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#define STC_CTR_INIT(MODE,LOAD,HOLD)\
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{*pcmd = CHIPCHAN+1; *pdata = (MODE); *pdata = (LOAD); *pdata= (HOLD);}
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#define STC_CTR_READ(MODE,LOAD,HOLD)\
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{*pcmd = CHIPCHAN+1; (MODE) = *pdata; (LOAD) = *pdata; (HOLD) = *pdata;}
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#define STC_SET_TC(D) *pcmd = 0xe0 | ((D)?8:0)|(CHIPCHAN+1)
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#define STC_LOAD *pcmd = 0x40 | 1<<(CHIPCHAN)
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#define STC_STEP *pcmd = 0xf0 | (CHIPCHAN+1)
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#define STC_ARM *pcmd = 0x20 | 1<<CHIPCHAN
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#define STC_DISARM *pcmd = 0xc0 | 1<<CHIPCHAN
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stc_io_report(pcmd,pdata)
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register unsigned char *pcmd;
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register unsigned short *pdata;
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{
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int cmd, data;
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if(vxMemProbe(pcmd, READ, sizeof(*pcmd), &cmd) != OK)
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return ERROR;
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if(vxMemProbe(pdata, READ, sizeof(*pdata), &data) != OK)
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return ERROR;
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return OK;
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}
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stc_init(pcmd, pdata, master_mode)
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register unsigned char *pcmd;
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register unsigned short *pdata;
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unsigned short master_mode;
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{
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int dummy;
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int channel;
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if(vxMemProbe(pcmd, READ, sizeof(*pcmd), &dummy) != OK)
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return ERROR;
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if(vxMemProbe(pdata, READ, sizeof(*pdata), &dummy) != OK)
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return ERROR;
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/*
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go to 16 bit mode in order to test the master mode register
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*/
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STC_BUS16;
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if(master_mode != STC_MASTER_MODE){
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/*
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start in a known state
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*/
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STC_RESET;
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/*
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required since the reset puts it in byte mode
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*/
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STC_BUS16;
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STC_SET_MASTER_MODE(master_mode);
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for(channel=0; channel<CHANONCHIP; channel++)
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STC_LOAD;
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}
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return OK;
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}
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stc_one_shot_read(preset, edge0_count, edge1_count, pcmd, pdata, channel,int_source)
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unsigned int *preset;
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unsigned short *edge0_count;
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unsigned short *edge1_count;
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unsigned char *pcmd;
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unsigned short *pdata;
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unsigned int channel;
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unsigned int *int_source;
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{
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int dummy;
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unsigned short mode;
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unsigned short edge0;
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unsigned short edge1;
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if(vxMemProbe(pcmd, READ, sizeof(*pcmd), &dummy) != OK)
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return ERROR;
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if(vxMemProbe(pdata, READ, sizeof(*pdata), &dummy) != OK)
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return ERROR;
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if(channel>=CHANONCHIP)
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return ERROR;
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STC_CTR_READ(mode, edge0, edge1);
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/*
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Only return values if the counter is in the proper mode
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see stc_one_shot() for info on conversions and functions selected
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by these bit fields
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*/
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if(mode == 0xc16a){
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*int_source = FALSE;
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*preset = TRUE;
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*edge0_count = ~edge0;
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*edge1_count = ~edge1+1;
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}
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else if(mode == 0xc162){
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*int_source = FALSE;
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*preset = FALSE;
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*edge0_count = edge0-1;
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*edge1_count = edge1;
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}
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else if(mode == 0xcb6a){
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*int_source = TRUE;
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*preset = TRUE;
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*edge0_count = ~edge0;
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*edge1_count = ~edge1+1;
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}
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else if(mode == 0xcb62){
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*int_source = TRUE;
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*preset = FALSE;
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*edge0_count = edge0-1;
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*edge1_count = edge1;
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}
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else
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return ERROR;
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return OK;
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}
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stc_one_shot(preset, edge0_count, edge1_count, pcmd, pdata, channel,int_source)
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unsigned int preset;
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unsigned short edge0_count;
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unsigned short edge1_count;
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unsigned char *pcmd;
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unsigned short *pdata;
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unsigned int channel;
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int int_source;
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{
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int dummy;
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if(vxMemProbe(pcmd, READ, sizeof(*pcmd), &dummy) != OK)
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return ERROR;
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if(vxMemProbe(pdata, READ, sizeof(*pdata), &dummy) != OK)
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return ERROR;
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if(channel>=CHANONCHIP)
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return ERROR;
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/*
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* joh 110791
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* Prevent the stc from generating tc prior to the trigger
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* in delayed pulse mode by forcing edge 0 delays of zero to be
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* a delay of one instead.
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*
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* 010492
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* Strange extra edges occur when the delay is 0 or 1
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* and the counter is reinitialized to a width of
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* zero so I have disabled a delay of one also
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*
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* These extra edges occur when TC is set
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*/
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if(edge0_count < 2)
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edge0_count = 2;
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STC_DISARM;
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/*
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active positive going edge (gate input)
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count on the rising edge of source
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ctr source: (F1- internal) (SRC1- external)
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mode L - Hardware triggered delayed pulse one-shot
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binary count
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count down (count up if preset is TRUE)
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TC toggled output
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see chapter 7 of the Am9513 STC tech man concerning count + 1
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*/
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/*
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NOTE: I must be able to read back the state of the preset later
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so I encode this information in the count down/up bit.
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count up on TRUE preset
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count down on FALSE preset
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see stc_one_shot_read() above
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*/
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if(int_source){
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if(preset)
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STC_CTR_INIT(0xcb6a, ~edge0_count, ~edge1_count+1)
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else
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STC_CTR_INIT(0xcb62, edge0_count+1, edge1_count);
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}else{
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if(preset)
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STC_CTR_INIT(0xc16a, ~edge0_count, ~edge1_count+1)
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else
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STC_CTR_INIT(0xc162, edge0_count+1, edge1_count);
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}
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STC_LOAD;
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/*
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see chapter 7 of the Am9513 STC tech man concerning this step
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*/
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STC_STEP;
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STC_SET_TC(preset);
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/*
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Only arm counter if the pulse has a finite duration
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*/
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if(edge1_count != 0){
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STC_ARM;
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}
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return OK;
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}
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