diff --git a/src/vxWorks/src/Makefile b/src/vxWorks/src/Makefile index 86b529d6b..a415292e5 100644 --- a/src/vxWorks/src/Makefile +++ b/src/vxWorks/src/Makefile @@ -6,6 +6,8 @@ INC += fast_lock.h INC += drvTS.h INC += devLib.h INC += epicsDynLink.h +INC += module_types.h +INC += task_params.h SRCS += drvTS.c SRCS += devLib.c diff --git a/src/vxWorks/src/module_types.h b/src/vxWorks/src/module_types.h new file mode 100644 index 000000000..a1cbe1d12 --- /dev/null +++ b/src/vxWorks/src/module_types.h @@ -0,0 +1,586 @@ +/* module_types.h */ +/* base/include $Id$ */ +/* + * Author: Bob Dalesio + * Date: 12-07-88 + * + * Experimental Physics and Industrial Control System (EPICS) + * + * Copyright 1991, the Regents of the University of California, + * and the University of Chicago Board of Governors. + * + * This software was produced under U.S. Government contracts: + * (W-7405-ENG-36) at the Los Alamos National Laboratory, + * and (W-31-109-ENG-38) at Argonne National Laboratory. + * + * Initial development by: + * The Controls and Automation Group (AT-8) + * Ground Test Accelerator + * Accelerator Technology Division + * Los Alamos National Laboratory + * + * Co-developed with + * The Controls and Computing Group + * Accelerator Systems Division + * Advanced Photon Source + * Argonne National Laboratory + * + * Modification Log: + * ----------------- + * .01 12-07-88 lrd moved IO_TYPES.H into here + * added interruptable indicator for each io card + * added arrays of pointers for info on the io cards + * .02 02-01-89 lrd add Allen-Bradley Modules + * rearrange I/O card order + * .03 02-04-89 lrd add bus specification + * + * .04 02-06-89 joh add timing int vec # + * .05 02-09-89 lrd move vectors and I/O card base addresses here + * .06 02-11-89 lrd changed AB num cards to 12 and OFE num chan to 4 + * .04 02-13-89 joh fixed length of timing address array + * .05 04-22-89 lrd changed AB num channels to 8 for ABBI cards + * .06 04-24-89 lrd moved AB 6008SV info here + * .07 05-26-89 joh added Joerger VTR1 transient recorder + * .08 09-13-89 lrd add VXI module specification to each type + * remove unused modules + * .09 09-25-89 lrd AB adapters to 8 cards to 16 and IFE channels to + * 8 + * .10 10-17-89 lrd AB changed number of cards from 12 to 16 for + * binary inputs and outputs + * .11 11-21-89 joh fixed card and chnl count for at5 vxi timing + * .12 11-30-89 lrd add the OMS 6 axis motor driver + * .13 12-12-89 joh moved XY220 base to match changes made by the + * hardware section. + * .14 05-16-90 cr add Single Ended IFE module + * .15 05-24-90 mk add 4-20Ma IFE + * .16 05-23-90 lrd/ms add DVX-2502 + * .17 07-19-90 ms changed the mizar interrupt vector to e8 + * wouldn't work with the CMC ethernet card + * used the same interrupt vector + * .18 12-19-90 lrd add 0-5V IFE + * .19 03-26-91 lrd modified the AT5-VXIBO from 16 to 32 + * .20 07-23-91 ges Add AT830X card base addresses and vectors. + * .21 08-14-91 ges Add AT830X_1 card base addresses and ivectors. + * (These are the new gen 8308B and 8309C cards) + * .22 06-24-92 joh added the hp E1368a VXI video switching module + * .23 06-25-92 bg stripped intitial 1 off the standard addresses + * in AB_BASE_ADDR,ai_memaddrs,wf_memaddrs,AT830X_ + * ADDRS, and AT830X_1_ADDRS so they can be mapped + in sysBusToLocalAdrs + * .24 06-25-92 bg stripped initial ff off all short addresses so + they can be mapped in sysBusToLocalAdrs + * .25 06-25-92 bg Moved SM_BASE_ADDR frin oms_driver.h to sm_addrs + in this file. + * .26 06-25-92 bg Moved dvx addresses,interrupt vectors,channel numbers + and card number definitions from dvx_driver.h to here. + + * .26 06-25-92 bg Moved dvx addresses,interrupt vectors,channel numbers + * .27 06-25-92 bg Added definitions for xy240_driver + * .28 06-25-92 bg Removed all reference to the Zio085 + * .29 06-26-92 bg Temporarily returned all reference to the Zio085 + * .30 06-26-92 joh added binary input capability to the hp E1368a + * VXI video switching module + * .31 06-30-92 joh added constant for the number of VXI LA + * .32 07-06-92 joh added base and size VXIA24 & A32 devices + * .33 07-07-92 joh added KSC V215 VXI AI + * .34 07-09-92 joh added AT8 FP10S master/slave fast + * protect module + * .35 07-10-92 joh added FP int vec base + * .36 07-17-92 bg moved addresses for Comet card from drvComet.c to + * here. + * .37 07-23-92 joh number of AI channels for AT5 VXI should be 8 not 6 + * number of BI channels for AT5 VXI should be 32 not 16 + * number of TI channels for AT5 VXI should be 10 not 5 + * (these changes reflect the AT5 hardware upgrade) + * + * .38 08-04-92 joh fixed COMET A16 base addr + * .39 08-10-92 joh number of xy220 cards now matches the AT8 + * address standard + * .40 08-11-92 joh moved xy010 base to here + * .41 08-11-92 joh took out xycom specific defines + * .42 09-15-92 joh DVX num cards was set allowing the DVX to + * overlap the VXI DC address and continue + * outside of VME A16. DVX num cards is now one + * .43 06-18-93 lrd reduced xy220 number of cards to 1 - mv167 mismatch on short address space + * .44 05-05-94 kornke Changed number of supported OMS cards. + */ + +#ifndef INCLmodule_typesh +#define INCLmodule_typesh + +/* Device module types */ +/* + * all devices have corresponding entries in ~operator/db/src/menus.c + * changes must be made in both areas to keep the database and drivers in sync + */ +/* & in comment indicates tested with card 0 */ +/* % in comment indicates tested with card other than card 0 */ +/* # in comment indicates that the Nth card has been tested */ +/* !! never been tested */ + +/* + * @# If any changes are made to this file, check the procedures + * ab_card, and vme_card in signallist.c, and get_address in sigmenu.c. + */ + +#ifdef MODULE_TYPES_INIT +#define MODULE_TYPES_DEF(MT_DEF_PARM) MT_DEF_PARM +#else +#define MODULE_TYPES_DEF(MT_DEF_PARM) extern MT_DEF_PARM; +#endif + +/* Number of columns used in io_report. */ +#define IOR_MAX_COLS 4 + +/* I/O types */ +#define IO_AI 0 +#define IO_AO 1 +#define IO_BI 2 +#define IO_BO 3 +#define IO_SM 4 +#define IO_WF 5 +#define IO_TIMER 6 +#define MAX_IO_TYPE IO_TIMER + +/* bus types */ +/* must correspond to the values in link types */ +/* these defines are in ~gta/dbcon/h/link.h */ + + +/* equates for the Allen-Bradley cards. */ +#define AB_BASE_ADDR 0xc00000 /* base addr of first AB6008SV */ +#define AB_MAX_LINKS 2 /* number of serial links from VME */ +#define AB_MAX_ADAPTERS 8 /* number of physical adapters on a link */ +#define AB_MAX_CARDS 16 /* max number of IO cards per adapter */ +#define AB_CARD_ADAPTER 16 /* cards per logical adapter */ +#define AB_CHAN_CARD 16 /* max channels per card */ + +/* analog inputs */ +#define AB1771IL 0 /* &% Allen-Bradley low level analog input */ +#define AB1771IFE 1 /* &% Allen-Bradley low level analog input */ +#define AB1771IXE 2 /* &% Allen-Bradley millivolt input */ +#define XY566SE 3 /* & Xycom 12-bit Single Ended Scanned*/ +#define XY566DI 4 /* &% Xycom 12-bit Differential Scanned */ +#define XY566DIL 5 /* &% Xycom 12-bit Differential Latched */ +#define VXI_AT5_AI 6 /* % AT-5 VXI module's Analog Inputs */ +#define AB1771IFE_SE 7 /* % A-B IFE in 16 single-ended input mode */ +#define AB1771IFE_4to20MA 8 /* % A-B IFE in 8 double-ended 4to20Ma */ +#define DVX2502 9 /* &% DVX_2502 128 chan 16 bit differential */ +#define AB1771IFE_0to5V 10 /* % A-B IFE in 8 double-ended 4to20Ma */ +#define KSCV215 11 /* % KSC V215 VXI 16 bit differential */ +#define AB1771IrPlatinum 12 /* % A-B RTD Platinum */ +#define AB1771IrCopper 13 /* % A-B RTD Copper */ +#define MAX_AI_TYPES AB1771IrCopper +MODULE_TYPES_DEF(short ai_num_cards[MAX_AI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={12,12,12, 4, 4, 6,32,12,12, 1, 12, 32, 12,12}; +#endif +MODULE_TYPES_DEF(short ai_num_channels[MAX_AI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 8, 8, 8,32,16,16, 8,16, 8, 127, 8, 32,6,6}; +#endif +MODULE_TYPES_DEF(short ai_interruptable[MAX_AI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0,0,0}; +#endif +MODULE_TYPES_DEF(short ai_bus[MAX_AI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 4, 4, 4, 2, 2, 2, 2, 4, 4, 2, 4, 2,4,4}; +#endif +MODULE_TYPES_DEF(unsigned short ai_addrs[MAX_AI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 0,0,0,0x6000,0x7000,0xe000, 0xc014,0,0, 0xff00, 0, 0,0,0}; +#endif +MODULE_TYPES_DEF(long ai_memaddrs[MAX_AI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={0,0,0,0x000000,0x040000,0x0c0000, 0,0,0, 0x100000, 0, 0,0,0}; +#endif + +/* analog outputs */ +#define AB1771OFE 0 /* &% Allen-Bradley 12 bit Analog Output */ +#define VMI4100 1 /* & VMIC VMIVME 4100 */ +#define ZIO085 2 /* & Ziomek 085 */ +#define VXI_AT5_AO 3 /* !! AT-5 VXI modules analog outputs */ +#define MAX_AO_TYPES VXI_AT5_AO +MODULE_TYPES_DEF(short ao_num_cards[MAX_AO_TYPES+1]) +#ifdef MODULE_TYPES_INIT + = {12, 4, 1, 32}; +#endif +MODULE_TYPES_DEF(short ao_num_channels[MAX_AO_TYPES+1]) +#ifdef MODULE_TYPES_INIT + = { 4, 16, 32, 16}; +#endif +MODULE_TYPES_DEF(short ao_interruptable[MAX_AO_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + = { 0, 0, 0, 1}; +#endif +MODULE_TYPES_DEF(short ao_bus[MAX_AO_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 4, 2, 2, 2}; +#endif +MODULE_TYPES_DEF(unsigned short ao_addrs[MAX_AO_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 0,0x4100,0x0800, 0xc000}; +#endif + +/* binary inputs */ +#define ABBI_08_BIT 0 /* &% Allen-Bradley generic Binary In 8 bit */ +#define ABBI_16_BIT 1 /* &% Allen-Bradley generic Binary In 16 bit */ +#define BB910 2 /* & BURR BROWN MPV 910 (relay) */ +#define XY210 3 /* &% XYcom 32 bit binary in */ +#define VXI_AT5_BI 4 /* !! AT-5 VXI modules binary inputs */ +#define HPE1368A_BI 5 /* !! HP E1368A video switch */ +#define AT8_FP10S_BI 6 /* !! AT8 FP10 slave fast protect */ +#define XY240_BI 7 /* !! Xycom 32 bit binary in / 32 bit binary out */ +#define MAX_BI_TYPES XY240_BI +MODULE_TYPES_DEF(short bi_num_cards[MAX_BI_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={ 12, 12, 4, 4, 32, 32, 8, 2}; +#endif +MODULE_TYPES_DEF(short bi_num_channels[MAX_BI_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={ 8, 16, 32, 32, 32, 16, 32, 32}; +#endif +MODULE_TYPES_DEF(short bi_interruptable[MAX_BI_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={ 1, 1, 0, 0, 1, 1, 1, 1}; +#endif +MODULE_TYPES_DEF(short bi_bus[MAX_BI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 4, 4, 2, 2, 2, 2, 2, 2}; +#endif +MODULE_TYPES_DEF(unsigned short bi_addrs[MAX_BI_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 0,0,0xb800,0xa000, 0xc000, 0xc000, 0x0e00, 0xd000}; +#endif + +/* binary outputs */ +#define ABBO_08_BIT 0 /* &% Allen-Bradley 8 bit binary out */ +#define ABBO_16_BIT 1 /* &% Allen-Bradley 16 bit binary out */ +#define BB902 2 /* &% BURR BROWN MPV 902 (relay) */ +#define XY220 3 /* &% XYcom 32 bit binary out */ +#define VXI_AT5_BO 4 /* !! AT-5 VXI modules binary outputs */ +#define HPE1368A_BO 5 /* !! HP E1368A video switch */ +#define AT8_FP10M_BO 6 /* !! AT8 FP10 master fast protect */ +#define XY240_BO 7 /* !! Xycom 32 bit binary in / 32 bit binary out */ +#define MAX_BO_TYPES XY240_BO +MODULE_TYPES_DEF(short bo_num_cards[MAX_BO_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={12, 12, 4, 1, 32, 32, 2, 2}; +#endif +MODULE_TYPES_DEF(short bo_num_channels[MAX_BO_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={ 8, 16, 32, 32, 32, 16, 32, 32}; +#endif +MODULE_TYPES_DEF(short bo_interruptable[MAX_BO_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={ 0, 0, 0, 0, 1, 0, 0, 1 }; +#endif +MODULE_TYPES_DEF(short bo_bus[MAX_BO_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 4, 4, 2, 2, 2, 2, 2, 2 }; +#endif +MODULE_TYPES_DEF(unsigned short bo_addrs[MAX_BO_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 0,0,0xd800,0xc800, 0xc000, 0xc000, 0x0c00, 0xd000}; +#endif + +/* stepper motor drivers */ +#define CM57_83E 0 /* & Compumotor 57-83E motor controller */ +#define OMS_6AXIS 1 /* & OMS six axis motor controller */ +#define MAX_SM_TYPES OMS_6AXIS +MODULE_TYPES_DEF(short sm_num_cards[MAX_SM_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={ 8, 8 }; +#endif +MODULE_TYPES_DEF(short sm_num_channels[MAX_SM_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + = { 1, 8}; +#endif +MODULE_TYPES_DEF(short sm_interruptable[MAX_SM_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + = { 0, 0 }; +#endif +MODULE_TYPES_DEF(short sm_bus[MAX_SM_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 2, 2 }; +#endif +MODULE_TYPES_DEF(unsigned short sm_addrs[MAX_SM_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 0x8000, 0xfc00 }; +#endif + +/* waveforms */ +#define XY566WF 0 /* & Xycom 566 as a waveform */ +#define CAMAC_THING 1 /* !! CAMAC waveform digitizer */ +#define JGVTR1 2 /* & Joerger transient recorder */ +#define COMET 3 /* !! COMET transient recorder */ +#define MAX_WF_TYPES COMET +MODULE_TYPES_DEF(short wf_num_cards[MAX_WF_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={4, 4, 8, 4}; +#endif +MODULE_TYPES_DEF(short wf_num_channels[MAX_WF_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={1, 1, 1, 4}; +#endif +MODULE_TYPES_DEF(short wf_interruptable[MAX_WF_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + = {0, 0, 0, 0}; +#endif +MODULE_TYPES_DEF(short wf_bus[MAX_WF_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={2, 3, 2, 2}; +#endif +MODULE_TYPES_DEF(unsigned short wf_addrs[MAX_WF_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={0x9000, 0, 0xB000, 0xbc00}; +#endif +MODULE_TYPES_DEF(unsigned short wf_armaddrs[MAX_WF_TYPES+1]) +#ifdef MODULE_TYPES_INIT + = {0x5400, 0, 0, 0}; +#endif +MODULE_TYPES_DEF(long wf_memaddrs[MAX_WF_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={0x080000, 0, 0xb80000, 0xe0000000}; +#endif + + +/* timing cards */ +#define MZ8310 0 /* &% Mizar Timing Module */ +#define DG535 1 /* !! GPIB timing instrument */ +#define VXI_AT5_TIME 2 /* !! AT-5 VXI modules timing channels */ +#define MAX_TM_TYPES VXI_AT5_TIME +MODULE_TYPES_DEF(short tm_num_cards[MAX_TM_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={ 4, 1, 32 }; +#endif +MODULE_TYPES_DEF(short tm_num_channels[MAX_TM_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + ={10, 1, 10}; +#endif +MODULE_TYPES_DEF(short tm_interruptable[MAX_TM_TYPES+1] ) +#ifdef MODULE_TYPES_INIT + = { 1, 0, 1 }; +#endif +MODULE_TYPES_DEF(short tm_bus[MAX_TM_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={ 2, 5, 2 }; +#endif +MODULE_TYPES_DEF(unsigned short tm_addrs[MAX_TM_TYPES+1]) +#ifdef MODULE_TYPES_INIT + ={0xf800, 0, 0xc000 }; +#endif + +/* AT830X clock cards */ +MODULE_TYPES_DEF(long AT830X_1_addrs ) +#ifdef MODULE_TYPES_INIT + = 0x0400; +#endif +MODULE_TYPES_DEF(short AT830X_1_num_cards ) +#ifdef MODULE_TYPES_INIT + = 2; +#endif +MODULE_TYPES_DEF(long AT830X_addrs ) +#ifdef MODULE_TYPES_INIT + = 0xaa0000; +#endif +MODULE_TYPES_DEF(short AT830X_num_cards ) +#ifdef MODULE_TYPES_INIT + = 2; +#endif + +/* + * system controller cards. + * (driver looks for only one card) + */ +MODULE_TYPES_DEF(long xy010ScA16Base) +#ifdef MODULE_TYPES_INIT + = 0x0000; +#endif +/* + * limit the size of the VXI logical address space + * + * = + 0xc000 + * + * LA VME address + * 0 + * EPICS_VXI_LA_COUNT + (EPICS_VXI_LA_COUNT-1)*64 + */ +MODULE_TYPES_DEF(unsigned char EPICS_VXI_LA_COUNT) +#ifdef MODULE_TYPES_INIT + = 32; +#endif + +/* + * + * address ranges for VXI A24 and A32 devices + * + */ +MODULE_TYPES_DEF(char *EPICS_VXI_A24_BASE) +#ifdef MODULE_TYPES_INIT + = (char *) 0x900000; +#endif +MODULE_TYPES_DEF(unsigned long EPICS_VXI_A24_SIZE) +#ifdef MODULE_TYPES_INIT + = 0x100000; +#endif +MODULE_TYPES_DEF(char *EPICS_VXI_A32_BASE) +#ifdef MODULE_TYPES_INIT + = (char *) 0x90000000; +#endif +MODULE_TYPES_DEF(unsigned long EPICS_VXI_A32_SIZE) +#ifdef MODULE_TYPES_INIT + = 0x10000000; +#endif + + +/****************************************************************************** + * + * Interrupt vector locations used by the MV167 CPU board. + * These are defined in mv167.h + * + * PCC2_INT_VEC_BASE 0x40 PCC interrupt vector base number + * any multiple of 0x10 + * UTIL_INT_VEC_BASE0 0x50 VMEchip2 utility interrupt + * vector base number + * any multiple of 0x10 + * UTIL_INT_VEC_BASE1 0x60 VMEchip2 utility interrupt + * vector base number + * any multiple of 0x10 + * + * INT_VEC_CD2400_A 0x90 int vec for channel A + * INT_VEC_CD2400_B 0x94 int vec for channel B + * INT_VEC_CD2400_C 0x98 int vec for channel C + * INT_VEC_CD2400_D 0x9c int vec for channel D + * + * LANC_IRQ_LEVEL 3 LNANC IRQ level + * MPCC_IRQ_LEVEL 4 serial comm IRQ level + * SYS_CLK_LEVEL 6 interrupt level for sysClk + * AUX_CLK_LEVEL 5 interrupt level for auxClk + * SCSI_IRQ_LEVEL 2 scsi interrupt level + * + ******************************************************************************/ + +/* interrupt vector allocation - one for each XY566 DIL card */ +MODULE_TYPES_DEF(int AI566_VNUM) +#ifdef MODULE_TYPES_INIT + =0xf8; /* Xycom 566 Differential Latched */ +#endif + +/* interrupt vector allocation - one for each DVX card */ +MODULE_TYPES_DEF(int DVX_IVEC0) +#ifdef MODULE_TYPES_INIT + =0xd0; +#endif + +/* stepper motor interrupt vector - one for each motor */ +MODULE_TYPES_DEF(int MD_INT_BASE) +#ifdef MODULE_TYPES_INIT + =0xf0; /* base of the motor int vector */ +#endif + +/* I reserve from here up to num_cards * 4 interrupting chans/card - joh */ +MODULE_TYPES_DEF(int MZ8310_INT_VEC_BASE) +#ifdef MODULE_TYPES_INIT + =0xe8; +#endif + +/* Allen-Bradley Serial Driver - MAX_AB_LINKS number of vectors */ +MODULE_TYPES_DEF(int AB_VEC_BASE) +#ifdef MODULE_TYPES_INIT + =0x60; +#endif + +/* only one interrupt vector allocated for all Joerger VTR1 boards joh */ +MODULE_TYPES_DEF(int JGVTR1_INT_VEC) +#ifdef MODULE_TYPES_INIT + =0xe0; +#endif + +/* AT830X_1 cards have 1 intr vector for each AT830X_1_num_cards (presently 2) */ +MODULE_TYPES_DEF(int AT830X_1_IVEC0) +#ifdef MODULE_TYPES_INIT + =0xd4; +#endif + +/* AT830X cards have 1 intr vector for each AT830X_num_cards (presently 2) */ +MODULE_TYPES_DEF(int AT830X_IVEC0) +#ifdef MODULE_TYPES_INIT + =0xd6; +#endif + +/* AT8 fast protect interrupt vector base */ +MODULE_TYPES_DEF(int AT8FP_IVEC_BASE) +#ifdef MODULE_TYPES_INIT + =0xa2; +#endif + + +MODULE_TYPES_DEF(int AT8FPM_IVEC_BASE ) +#ifdef MODULE_TYPES_INIT + =0xaa; +#endif + + +/****************************************************************************** + * + * Addresses and IRQ information used by the XVME402 bitbus cards. + * + ******************************************************************************/ +MODULE_TYPES_DEF(unsigned short BB_SHORT_OFF ) +#ifdef MODULE_TYPES_INIT + = 0x1800; /* the first address of link 0's region */ +#endif +#define BB_NUM_LINKS 4 /* max number of BB ports allowed */ +MODULE_TYPES_DEF(int BB_IVEC_BASE ) +#ifdef MODULE_TYPES_INIT + = 0xa0; /* vectored interrupts (2 used for each link) */ +#endif +MODULE_TYPES_DEF(int BB_IRQ_LEVEL ) +#ifdef MODULE_TYPES_INIT + = 5; /* IRQ level */ +#endif + +/****************************************************************************** + * + * Information for the PEP modular Bitbus boards. + * + ******************************************************************************/ +MODULE_TYPES_DEF(unsigned short PEP_BB_SHORT_OFF ) +#ifdef MODULE_TYPES_INIT + = 0x1c00; +#endif +MODULE_TYPES_DEF(int PEP_BB_IVEC_BASE ) +#ifdef MODULE_TYPES_INIT + = 0xe8; +#endif + +/****************************************************************************** + * + * Addresses and IRQ information used by the NI1014 and NI1014D bitbus cards. + * + ******************************************************************************/ +MODULE_TYPES_DEF(unsigned short NIGPIB_SHORT_OFF) +#ifdef MODULE_TYPES_INIT + = 0x5000;/* First address of link 0's region */ +#endif + /* Each link uses 0x0200 bytes */ +#define NIGPIB_NUM_LINKS 4 /* Max number of NI GPIB ports allowed */ +MODULE_TYPES_DEF(int NIGPIB_IVEC_BASE ) +#ifdef MODULE_TYPES_INIT + = 100; /* Vectored interrupts (2 used for each link) */ +#endif +MODULE_TYPES_DEF(int NIGPIB_IRQ_LEVEL ) +#ifdef MODULE_TYPES_INIT + =5; /* IRQ level */ +#endif + +#if 0 /* JRW */ +#define NI1014_LINK_NUM_BASE 0 +#endif + +/* + * nothing after this endif + */ +#endif /*INCLmodule_typesh*/ diff --git a/src/vxWorks/src/task_params.h b/src/vxWorks/src/task_params.h new file mode 100644 index 000000000..963ee7f04 --- /dev/null +++ b/src/vxWorks/src/task_params.h @@ -0,0 +1,281 @@ +/* $Id$ */ + +/* Parameters for tasks on IOC */ +/* + * Authors: Andy Kozubal, Jeff Hill, and Bob Dalesio + * Date: 2-24-89 + * + * Experimental Physics and Industrial Control System (EPICS) + * + * Copyright 1991, the Regents of the University of California, + * and the University of Chicago Board of Governors. + * + * This software was produced under U.S. Government contracts: + * (W-7405-ENG-36) at the Los Alamos National Laboratory, + * and (W-31-109-ENG-38) at Argonne National Laboratory. + * + * Initial development by: + * The Controls and Automation Group (AT-8) + * Ground Test Accelerator + * Accelerator Technology Division + * Los Alamos National Laboratory + * + * Co-developed with + * The Controls and Computing Group + * Accelerator Systems Division + * Advanced Photon Source + * Argonne National Laboratory + * + * Modification Log: + * ----------------- + * .01 07-23-91 ges Add time-stamp task. + * .02 09-12-91 joh stack sizes increased for v5 vxWorks. + * .03 10-24-91 lrd Increased stack sizes for scan tasks + * .04 12-12-91 joh Increased stack size for the + * wfDoneTask + * .05 12-18-91 mrk Added callback task priorities + * Changed def of PERIODSCAN_PRI and SEQUENCER_PRI + * Shortened length of task names + * .06 12-18-91 jba Global change of WDSCAN to TASKWD + * .07 01-21-92 rcz Increased all stack sizes by 1000 for V5 + * .08 01-21-92 jrw added the GPIB & BB driver task info + * .09 01-04-92 jba Added callback task priorities + * .10 03-16-92 jrw added BB rx and tx specific task info + * .11 05-22-92 lrd added the allen-bradley binary input Change of State scanner + * .12 08-26-92 joh added xy 240 stuff + * .13 08-26-92 joh added FP to CA repeater and on line to be safe + * .14 02-16-92 joh removed historical items + * .15 11-19-93 joh moved CA client priority up by one notch + * .16 09-13-93 joh incresed CA on line beacon maximum delay + * to 60 sec + * .17 03-18-94 mcn added entries for breakpoint tasks + * $Log$ + * Revision 1.6 1999/11/18 13:54:15 mrk + * moved to vxWorks specific code + * + * Revision 1.4 1998/09/29 14:45:50 mrk + * Task priorities were changed so that no epics task has higher priority than netTask. + * Definitions for IOEVENTSCAN and TIMESTAMP were removed. + * + * Revision 1.3 1998/05/20 21:00:43 mrk + * raised DB_CA_PRI to just higher than sequencer + * + * Revision 1.2 1998/01/20 21:49:54 mrk + * added the arch_stack_factor for 64 bit architectures; changes for errlog + * + * Revision 1.1 1996/11/22 20:49:43 jhill + * installed + * + * Revision 1.1 1996/06/24 13:32:35 mrk + * added task_params.h + * + * Revision 1.3 1996/06/19 20:48:44 jhill + * dounled ca stack for each ca cleint in the server + * + * Revision 1.2 1996/04/22 14:31:08 mrk + * Changes for dynamic link modification + * + * Revision 1.1 1996/01/25 21:13:29 mrk + * moved includes; .ascii=> .db; path changes + * + * Revision 1.27 1995/11/29 19:27:59 jhill + * added $Log$ + * added Revision 1.6 1999/11/18 13:54:15 mrk + * added moved to vxWorks specific code + * added + * added Revision 1.4 1998/09/29 14:45:50 mrk + * added Task priorities were changed so that no epics task has higher priority than netTask. + * added Definitions for IOEVENTSCAN and TIMESTAMP were removed. + * added + * added Revision 1.3 1998/05/20 21:00:43 mrk + * added raised DB_CA_PRI to just higher than sequencer + * added + * added Revision 1.2 1998/01/20 21:49:54 mrk + * added added the arch_stack_factor for 64 bit architectures; changes for errlog + * added + * added Revision 1.1 1996/11/22 20:49:43 jhill + * added installed + * added + * added Revision 1.1 1996/06/24 13:32:35 mrk + * added added task_params.h + * added + * added Revision 1.3 1996/06/19 20:48:44 jhill + * added dounled ca stack for each ca cleint in the server + * added + * added Revision 1.2 1996/04/22 14:31:08 mrk + * added Changes for dynamic link modification + * added + * added Revision 1.1 1996/01/25 21:13:29 mrk + * added moved includes; .ascii=> .db; path changes + * added + * + */ + +#ifndef INCtaskLibh +#include +#endif + +#define VXTASKIDSELF 0 + +/* Task Names */ +#define EVENTSCAN_NAME "scanEvent" +#define SCANONCE_NAME "scanOnce" +#define SMCMD_NAME "smCommand" +#define SMRESP_NAME "smResponse" +#define ABDONE_NAME "abDone" +#define ABSCAN_NAME "abScan" +#define ABCOS_NAME "abBiCosScanner" +#define MOMENTARY_NAME "momentary" +#define WFDONE_NAME "wfDone" +#define SEQUENCER_NAME "sequencer" +#define BKPT_CONT_NAME "bkptCont" +#define SCANNER_NAME "scanner" +#define REQ_SRVR_NAME "CA TCP" +#define CA_CLIENT_NAME "CA client" +#define CA_EVENT_NAME "CA event" +#define CAST_SRVR_NAME "CA UDP" +#define CA_REPEATER_NAME "CA repeater" +#define CA_ONLINE_NAME "CA online" +#define TASKWD_NAME "taskwd" +#define SMIOTEST_NAME "smInout" +#define SMROTTEST_NAME "smRotate" +#define EVENT_PEND_NAME "event task" +#define XY240_NAME "xy 240 scan" +#define GPIBLINK_NAME "gpibLink" +#define BBLINK_NAME "bbLinkTask" +#define BBTXLINK_NAME "bbTx" +#define BBRXLINK_NAME "bbRx" +#define BBWDTASK_NAME "bbwd" +#define ERRLOG_NAME "errlog" +#define LOG_RESTART_NAME "logRestart" + +/* Task priorities */ +#define SCANONCE_PRI 129 /* scan one time */ +/*DO NOT RUN ANY RECORD PROCESSING TASKS AT HIGHER PRIORITY THAN _netTask=50*/ +#define CALLBACK_PRI_LOW 140 /* callback task - generall callback task */ +#define CALLBACK_PRI_MEDIUM 135 /* callback task - generall callback task */ +#define CALLBACK_PRI_HIGH 128 /* callback task - generall callback task */ +#define EVENTSCAN_PRI 129 /* Event Scanner - Runs on a global event */ +#define SMCMD_PRI 120 /* Stepper Motor Command Task - Waits for cmds */ +#define SMRESP_PRI 121 /* Stepper Motor Resp Task - Waits for resps */ +#define ABCOS_PRI 121 /* Allen-Bradley Binary Input COS io_event wakeup */ +#define ABDONE_PRI 122 /* Allen-Bradley Resp Task - Interrupt Driven */ +#define ABSCAN_PRI 123 /* Allen-Bradley Scan Task - Base Rate .1 secs */ +#define BBLINK_PRI 124 +#define BBWDTASK_PRI 123 /* BitBus watchdog task */ +#define BBRXLINK_PRI 124 /* BitBus link task */ +#define BBTXLINK_PRI 125 /* BitBus link task */ +#define GPIBLINK_PRI 125 /* GPIB link task */ +#define MOMENTARY_PRI 126 /* Momentary output - posted from watchdog */ +#define WFDONE_PRI 127 /* Waveform Task - Base Rate of .1 second */ +#define PERIODSCAN_PRI 139 /* Periodic Scanners - Slowest rate */ +#define DB_CA_PRI 149 /*database to channel access*/ +#define SEQUENCER_PRI 151 +#define XY240_PRI 160 /* xy 240 dio scanner */ +#define SCANNER_PRI 170 +#define REQ_SRVR_PRI 181 /* Channel Access TCP request server*/ +#define CA_CLIENT_PRI 180 /* Channel Access clients */ +#define CA_REPEATER_PRI 181 /* Channel Access repeater */ +#define ERRLOG_PRI CA_REPEATER_PRI /*error logger task*/ +#define CAST_SRVR_PRI 182 /* Channel Access broadcast server */ +#define CA_ONLINE_PRI 183 /* Channel Access server online notify */ +#define TASKWD_PRI 200 /* Watchdog Scan Task - runs every 6 seconds */ +#define SMIOTEST_PRI 205 /* Stepper Mtr in/out test - runs every .1 sec */ +#define SMROTTEST_PRI 205 /* Stepper Mtr rotate test - runs every .1 sec */ +#define LOG_RESTART_PRI 200 /* Log server connection watch dog */ + +/* Task delay times (seconds) */ +#define TASKWD_DELAY 6 + +/* Task delay times (tics) */ +#define ABSCAN_RATE (sysClkRateGet()/6) +#define SEQUENCER_DELAY (sysClkRateGet()/5) +#define SCANNER_DELAY (sysClkRateGet()/5) +#define CA_ONLINE_DELAY (sysClkRateGet()*15) +#define LOG_RESTART_DELAY (sysClkRateGet()*30) + +/* Task creation options */ +#define ERRLOG_OPT VX_FP_TASK +#define EVENTSCAN_OPT VX_FP_TASK +#define SCANONCE_OPT VX_FP_TASK +#define CALLBACK_OPT VX_FP_TASK +#define SMCMD_OPT VX_FP_TASK +#define SMRESP_OPT VX_FP_TASK +#define ABDONE_OPT VX_FP_TASK +#define ABCOS_OPT VX_FP_TASK +#define ABSCAN_OPT VX_FP_TASK +#define MOMENTARY_OPT VX_FP_TASK +#define PERIODSCAN_OPT VX_FP_TASK +#define WFDONE_OPT VX_FP_TASK +#define SEQUENCER_OPT VX_FP_TASK | VX_STDIO +#define BKPT_CONT_OPT VX_FP_TASK +#define SCANNER_OPT VX_FP_TASK +#define REQ_SRVR_OPT VX_FP_TASK +#define CAST_SRVR_OPT VX_FP_TASK +#define CA_CLIENT_OPT VX_FP_TASK +#define CA_REPEATER_OPT VX_FP_TASK +#define CA_ONLINE_OPT VX_FP_TASK +#define TASKWD_OPT VX_FP_TASK +#define SMIOTEST_OPT VX_FP_TASK +#define SMROTTEST_OPT VX_FP_TASK +#define EVENT_PEND_OPT VX_FP_TASK +#define GPIBLINK_OPT VX_FP_TASK|VX_STDIO +#define BBLINK_OPT VX_FP_TASK|VX_STDIO +#define BBTXLINK_OPT VX_FP_TASK|VX_STDIO +#define BBRXLINK_OPT VX_FP_TASK|VX_STDIO +#define BBWDTASK_OPT VX_FP_TASK|VX_STDIO +#define DB_CA_OPT (VX_FP_TASK | VX_STDIO) +#define XY_240_OPT (0) /* none */ +#define LOG_RESTART_OPT (VX_FP_TASK) + + +/* + * Task stack sizes + * + * (original stack sizes are appropriate for the 68k) + * ARCH_STACK_FACTOR allows scaling the stacks on particular + * processor architectures + */ +#if CPU_FAMILY == MC680X0 +#define ARCH_STACK_FACTOR 1 +#elif CPU_FAMILY == SPARC +#define ARCH_STACK_FACTOR 2 +#else +#define ARCH_STACK_FACTOR 2 +#endif + +#define ERRLOG_STACK (4000*ARCH_STACK_FACTOR) +#define EVENTSCAN_STACK (11000*ARCH_STACK_FACTOR) +#define SCANONCE_STACK (11000*ARCH_STACK_FACTOR) +#define CALLBACK_STACK (11000*ARCH_STACK_FACTOR) +#define SMCMD_STACK (3000*ARCH_STACK_FACTOR) +#define SMRESP_STACK (3000*ARCH_STACK_FACTOR) +#define ABCOS_STACK (3000*ARCH_STACK_FACTOR) +#define ABDONE_STACK (3000*ARCH_STACK_FACTOR) +#define ABSCAN_STACK (3000*ARCH_STACK_FACTOR) +#define MOMENTARY_STACK (2000*ARCH_STACK_FACTOR) +#define PERIODSCAN_STACK (11000*ARCH_STACK_FACTOR) +#define WFDONE_STACK (9000*ARCH_STACK_FACTOR) +#define SEQUENCER_STACK (5500*ARCH_STACK_FACTOR) +#define BKPT_CONT_STACK (11000*ARCH_STACK_FACTOR) +#define SCANNER_STACK (3048*ARCH_STACK_FACTOR) +#define RSP_SRVR_STACK (5096*ARCH_STACK_FACTOR) +#define REQ_SRVR_STACK (5096*ARCH_STACK_FACTOR) +#define CAST_SRVR_STACK (5096*ARCH_STACK_FACTOR) +#define CA_CLIENT_STACK (11000*ARCH_STACK_FACTOR) +#define CA_REPEATER_STACK (5096*ARCH_STACK_FACTOR) +#define CA_ONLINE_STACK (3048*ARCH_STACK_FACTOR) +#define TASKWD_STACK (2000*ARCH_STACK_FACTOR) +#define SMIOTEST_STACK (2000*ARCH_STACK_FACTOR) +#define SMROTTEST_STACK (2000*ARCH_STACK_FACTOR) +#define EVENT_PEND_STACK (5096*ARCH_STACK_FACTOR) +#define TIMESTAMP_STACK (4000*ARCH_STACK_FACTOR) +#define GPIBLINK_STACK (5000*ARCH_STACK_FACTOR) +#define BBLINK_STACK (5000*ARCH_STACK_FACTOR) +#define BBRXLINK_STACK (5000*ARCH_STACK_FACTOR) +#define BBTXLINK_STACK (5000*ARCH_STACK_FACTOR) +#define BBWDTASK_STACK (5000*ARCH_STACK_FACTOR) +#define DB_CA_STACK (11000*ARCH_STACK_FACTOR) +#define XY_240_STACK (4096*ARCH_STACK_FACTOR) +#define LOG_RESTART_STACK (0x1000*ARCH_STACK_FACTOR) +