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AliceMazzoleni99
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* added simulator tests in github workflows * indentation error * typo * debug * Logging for debugging * added more debug lines * more debugging * debug * debug * debug * dont throw if process does not exist * debug * added absolute path to sls_detector commands * some refactoring in test scripts * added absolute path to all slsdet command * typo * ../tests/scripts/test_frame_synchronizer.py * raise exception upon failure for github workflows * removed hidden tags * some refactoring in test scripts * some refactoring * fixed CMakeLists * fixed unsuccesful merge * updated python tests using simulators * debug import error * debug module import * python -m runs module pytest as script - everything in path available * removed integartion tests * enable file write not to log files * run tests without log files * increased sleep time for udp packets * added logg level variable to cmake * added testing policies to documenattion * disabled check for num_frames for jungfrau & xilinx * set log level as cmake cached variable * disable tests for jungfrau and xilinx_ctb * check frames for HDF5 * updated Documentation of Testing * changed withdetectorsimulators to detectorintegration * replaced [.cmdcall] with [.detectorintegration] * check_file_size only disabled for jungfrau - disable for all roi tests * changed time to wait after receive to 5 ms * take into account half modules of eiger * num udp interfaces needs to be consistent across modules * suppressed warning enclosing if * config added 2 udp ports per default for moench and jungfrau * write detector output to console * allow jungfrau to tests num frames, remove unused variable (numinterfaces), add comment for future to handle traceback to know which calling function threw the files unmatched, added documentation for tests (examples for .detectoritnegration and how to disable marked tests, removed addditional argumetns to disable for test_simulator as one can just use ~, removed the check that checks for jungfrau checking number of frames at master attributes and at rx test, removed unused advanced_test_settings in test_simulator script, the num_mods check for multiple modules is removed and default num modules set to 1 for test_simulator (to be increased later), back to raising exception for killprocess * removed integration tests from cmakelists.txt and cmk.sh, modified the tests workflow command to reflect the disable argument and removed xilinx_ctb from test (fix fromdeveloper merge to be done) * filtering by actual name for disable certain tests on github workflow * minor refactor * wip * wip * changes to run on local rh9 runner instead of github workfloa * modified yml to remove some leftover from github workflow * test * fix build_dir in scripts (github workflow) and pytest dir in gitea workflow * making the local machine use python3.13 binary * pythonpath added * changes for build_Dir back * allowing ctb api tests * allowed ctb api tests and set up slsdetname envt variable for shared memory being reserved just for these tests * added rh8 workflow for local runner on gitea * remnants from rh9 local runner * remnants from rh9 local runner * conda env for all shell for local runner * allowing hdf5 to build on local runner * run all tests for both the runners * refactored fixtures a bit and merged some tests that use one session for entire server * test fail * test fix * adding github workflow to test without data file checks and without logs * documentation changes * unnecessary import in conftest * allowing the session_simulator to test for multiple modules and interfaces etc * allow test_simulator script to run for 2 modules for all modules except ctb and xilinx ctb * run upon push * removing the disable file check on github workflow * minor adjustment * testing without synch * reverting to previous * with log file * without the space * summary from file and more error extracts from file to terminal * minor * trying nlf for more details * updated with no log file to print everything to screen also for det and rxr * trying a no throw * stoi was more about indent in yaml * tries * wip * debug * number of frames inconsistent fix=>just take first one, only test xilinx * jungfrau tests without frames caught check * extend the disable file check to everywhere that creates files * specify path for test_simulator * withoutprinting == * wip * back with printing===, but not parsing file for errors anymore * lang? * wip * safe log? * wip2 * wip * dont split error as its streaming live, just raise * with log files * lang? * last resort * wip * test no det with general tests * show tests live * also include hidden integration tests * without extra summary? * revert * last resort again * tsquash on int64_t? * tsquash on int64_t? mroe print * writing to /tmp? * all tests * might be the fix? * write to file * fixed a few quiet mode no log file tests * work on any branch for github tests, work on also release candidates for gitea tests * added frame synchronizer tests to github workflow * moved tests to run_tests.yaml from cmake.yaml * documentation * disabled general tests --------- Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
397 lines
14 KiB
Python
397 lines
14 KiB
Python
import pytest, sys, traceback
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from pathlib import Path
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current_dir = Path(__file__).resolve().parents[2]
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scripts_dir = current_dir / "tests" / "scripts"
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sys.path.append(str(scripts_dir))
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print(sys.path)
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from utils_for_test import (
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Log,
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LogLevel,
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)
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from slsdet import Detector
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@pytest.mark.detectorintegration
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def test_define_reg(session_simulator, request):
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""" Test setting define_reg for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.define_reg(name="test_reg", addr=RegisterAddress(0x200)) # valid
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d.define_reg(name="test_reg", addr=addr1) # takes a register address
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d.define_reg(name="test_reg2", addr=0x202) # takes an int
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# not using keyword arguments
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with pytest.raises(TypeError) as exc_info:
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d.define_reg("randomreg", 0x203)
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# invalid value type
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg3", addr='0x203')
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assert "addr must int or RegisterAddress" in str(exc_info.value)
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# defining with duplicate value
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg3", addr=addr1)
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assert "Value already assigned" in str(exc_info.value)
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assert(d.getRegisterAddress("test_reg") == addr1)
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assert(d.getRegisterName(addr1) == "test_reg")
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# accessing non existent reg name
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with pytest.raises(Exception) as exc_info:
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d.reg['random_reg']
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assert "No entry found for key" in str(exc_info.value)
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# get non existing reg address
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with pytest.raises(Exception) as exc_info:
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d.getRegisterName(RegisterAddress(0x300))
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assert "No entry found for value" in str(exc_info.value)
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d.clearRegisterDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg", addr=0x201)
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assert "Register Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_define_bit(session_simulator, request):
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""" Test setting define_bit for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.define_reg(name="test_reg1", addr=addr1)
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d.define_reg(name="test_reg2", addr=addr2)
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# not using keyword arguments
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with pytest.raises(TypeError) as exc_info:
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d.define_bit("randombit", 0x203, 1)
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# invalid value type (bit=string)
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with pytest.raises(ValueError) as exc_info:
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position='1')
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# invalid bit_position
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position=32)
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assert "Bit position must be between 0 and 31" in str(exc_info.value)
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# defining with random reg value
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name='test_bit1', addr='random_reg', bit_position=1)
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assert "No entry found for key" in str(exc_info.value)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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# defining bit address with bit_position as well
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with pytest.raises(ValueError) as exc_info:
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d.define_bit(name='test_bit1', addr=bit1, bit_position=1)
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assert "bit_position must be None" in str(exc_info.value)
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d.define_bit(name="test_bit1", addr='test_reg2', bit_position=1)
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position=1) # modify reg
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d.define_bit(name='test_bit1', addr=bit1) # modify pos
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d.define_bit(name="test_bit2", addr=0x201, bit_position=4) # int addr
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d.define_bit(name="test_bit3", addr=addr2, bit_position=3) # RegisterAddress addr
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assert(d.getBitAddress('test_bit1') == bit1)
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assert(d.getBitAddress('test_bit2') == bit2)
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assert(d.getBitAddress('test_bit3') == bit3)
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assert(d.getBitAddress('test_bit1').address() == addr1)
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assert(d.getBitAddress('test_bit1').bitPosition() == 2)
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assert(d.getBitAddress('test_bit2') == BitAddress(addr1, 4))
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assert(d.getBitName(bit1) == 'test_bit1')
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assert(d.getBitName(bit2) == 'test_bit2')
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assert(d.getBitName(bit3) == 'test_bit3')
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assert(d.getBitName(BitAddress(addr2,3)) == 'test_bit3')
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# bit doesnt exist for that reg
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with pytest.raises(Exception) as exc_info:
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d.getBitName(BitAddress(addr1, 5))
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assert "No entry found for value" in str(exc_info.value)
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# addr doesnt exist for that reg
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with pytest.raises(Exception) as exc_info:
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d.getBitName(BitAddress(RegisterAddress(0x300), 5))
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assert "No entry found for value" in str(exc_info.value)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_using_defined_reg_and_bit(session_simulator, request):
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""" Test using defined reg and bit define_bit for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.setRegisterDefinition('test_reg1', addr1)
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d.setRegisterDefinition('test_reg2', addr2)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setBitDefinition('test_bit1', bit1)
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d.setBitDefinition('test_bit2', bit2)
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d.setBitDefinition('test_bit3', bit3)
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prev_val_addr1 = d.reg[addr1]
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prev_val_addr2 = d.reg[addr2]
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# reg name doesnt exist
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with pytest.raises(Exception) as exc_info:
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d.reg['random_reg']
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.setBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.clearBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.getBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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# bit name doesnt exist
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with pytest.raises(Exception) as exc_info:
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d.setBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.clearBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.getBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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d.reg['test_reg1'] = RegisterValue(0x0)
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assert(d.reg['test_reg1'].value() == 0x0)
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d.reg['test_reg1'] = RegisterValue(0x10)
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assert(d.reg['test_reg1'].value() == 0x10)
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d.setBit('test_bit1')
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assert(d.reg['test_reg1'].value() == 0x14) # 0x10 | (1 << 2)
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d.clearBit('test_bit1')
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assert(d.reg['test_reg1'].value() == 0x10)
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assert(d.getBit('test_bit1') == 0)
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# restore previous values
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d.reg[addr1] = prev_val_addr1
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d.reg[addr2] = prev_val_addr2
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_definelist_reg(session_simulator, request):
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""" Test using definelist_reg for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setRegisterDefinitions({
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'test_reg1': RegisterAddress(0x201),
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'test_reg2': RegisterAddress(0x202)
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})
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res = d.getRegisterDefinitions()
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assert(res['test_reg1'] == addr1)
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assert(res['test_reg2'] == addr2)
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assert(len(res) == 2)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_definelist_bit(session_simulator, request):
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""" Test using definelist_bit for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setRegisterDefinitions({
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'test_reg1': RegisterAddress(0x201),
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'test_reg2': RegisterAddress(0x202)
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})
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d.setBitDefinitions({
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'test_bit1': BitAddress(addr1, 2),
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'test_bit2': BitAddress(addr1, 4),
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'test_bit3': BitAddress(addr2, 3)
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})
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res = d.getBitDefinitions()
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assert(len(res) == 3)
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assert(res['test_bit1'] == bit1)
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assert(res['test_bit2'] == bit2)
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assert(res['test_bit3'] == bit3)
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assert(res['test_bit2'].address() == addr1)
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assert(res['test_bit2'].bitPosition() == 4)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_parameters_file(session_simulator, request):
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""" Test using test_parameters_file."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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with open("/tmp/params.det", "w") as f:
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f.write("frames 2\n")
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f.write("fwrite 1\n")
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# this should not throw
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d.parameters = "/tmp/params.det"
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assert d.frames == 2
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assert d.fwrite == 1
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Log(LogLevel.INFOGREEN, f"✅ Test passed. Command: parameters")
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@pytest.mark.detectorintegration
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def test_include_file(session_simulator, request):
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""" Test using test_include_file."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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with open("/tmp/params.det", "w") as f:
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f.write("frames 3\n")
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f.write("fwrite 0\n")
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# this should not throw
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d.include = "/tmp/params.det"
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assert d.frames == 3
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assert d.fwrite == 0
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Log(LogLevel.INFOGREEN, f"✅ Test passed. Command: include")
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@pytest.mark.detectorintegration
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def test_patternstart(session_simulator, request):
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""" Test using patternstart for ctb, xilinx_ctb and mythen3."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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|
if det_type in ['ctb', 'xilinx_ctb', 'mythen3']:
|
|
d.patternstart()
|
|
else:
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.patternstart()
|
|
assert "not implemented" in str(exc_info.value)
|
|
|
|
Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
|