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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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175 lines
7.6 KiB
C
Executable File
175 lines
7.6 KiB
C
Executable File
#pragma once
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#include "blackfin.h"
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/**
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* To be defined
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*
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* (in blackfin.h)
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* I2C_CLOCK_MHZ
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*
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* (RegisterDefs.h)
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* I2C_SCL_LOW_COUNT_REG
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* I2C_SCL_HIGH_COUNT_REG
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* I2C_SDA_HOLD_REG
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* I2C_CONTROL_REG
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* I2C_TRANSFER_COMMAND_FIFO_REG
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* I2C_RX_DATA_FIFO_LEVEL_REG
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*/
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#define I2C_DATA_RATE_KBPS (200)
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/** Control Register */
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#define I2C_CTRL_ENBLE_CORE_OFST (0)
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#define I2C_CTRL_ENBLE_CORE_MSK (0x00000001 << I2C_CTRL_ENBLE_CORE_OFST)
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#define I2C_CTRL_BUS_SPEED_OFST (1)
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#define I2C_CTRL_BUS_SPEED_MSK (0x00000001 << I2C_CTRL_BUS_SPEED_OFST)
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#define I2C_CTRL_BUS_SPEED_STNDRD_100_VAL ((0x0 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // standard mode (up to 100 kbps)
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#define I2C_CTRL_BUS_SPEED_FAST_400_VAL ((0x1 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // fast mode (up to 400 kbps)
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/** if actual level of transfer command fifo <= thd level, TX_READY interrupt asserted */
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#define I2C_CTRL_TFR_CMD_FIFO_THD_OFST (2)
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#define I2C_CTRL_TFR_CMD_FIFO_THD_MSK (0x00000003 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
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#define I2C_CTRL_TFR_CMD_EMPTY_VAL ((0x0 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
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#define I2C_CTRL_TFR_CMD_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
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#define I2C_CTRL_TFR_CMD_ONE_HALF_VAL ((0x2 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
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#define I2C_CTRL_TFR_CMD_NOT_FULL_VAL ((0x3 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
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/** if actual level of receive data fifo <= thd level, RX_READY interrupt asserted */
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#define I2C_CTRL_RX_DATA_FIFO_THD_OFST (4)
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#define I2C_CTRL_RX_DATA_FIFO_THD_MSK (0x00000003 << I2C_CTRL_RX_DATA_FIFO_THD_OFST)
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#define I2C_CTRL_RX_DATA_1_VALID_ENTRY_VAL ((0x0 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
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#define I2C_CTRL_RX_DATA_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
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#define I2C_CTRL_RX_DATA_ONE_HALF_VAL ((0x2 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
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#define I2C_CTRL_RX_DATA_FULL_VAL ((0x3 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
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/** Transfer Command Fifo register */
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#define I2C_TFR_CMD_RW_OFST (0)
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#define I2C_TFR_CMD_RW_MSK (0x00000001 << I2C_TFR_CMD_RW_OFST)
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#define I2C_TFR_CMD_RW_WRITE_VAL ((0x0 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
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#define I2C_TFR_CMD_RW_READ_VAL ((0x1 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
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#define I2C_TFR_CMD_ADDR_OFST (1)
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#define I2C_TFR_CMD_ADDR_MSK (0x0000007F << I2C_TFR_CMD_ADDR_OFST)
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/** when writing, rw and addr converts to data to be written mask */
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#define I2C_TFR_CMD_DATA_FR_WR_OFST (0)
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#define I2C_TFR_CMD_DATA_FR_WR_MSK (0x000000FF << I2C_TFR_CMD_DATA_FR_WR_OFST)
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#define I2C_TFR_CMD_STOP_OFST (8)
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#define I2C_TFR_CMD_STOP_MSK (0x00000001 << I2C_TFR_CMD_ADDR_OFST)
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#define I2C_TFR_CMD_RPTD_STRT_OFST (9)
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#define I2C_TFR_CMD_RPTD_STRT_MSK (0x00000001 << I2C_TFR_CMD_RPTD_STRT_OFST)
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uint32_t I2C_Control_Reg = 0x0;
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uint32_t I2C_Rx_Data_Fifo_Level_Reg = 0x0;
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uint32_t I2C_Scl_Low_Count_Reg = 0x0;
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uint32_t I2C_Scl_High_Count_Reg = 0x0;
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uint32_t I2C_Sda_Hold_Reg = 0x0;
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uint32_t I2C_Transfer_Command_Fifo_Reg = 0x0;
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/**
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* Configure the I2C core,
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* Enable core and
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* Calibrate the calibration register for current readout
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* @param creg control register (defined in RegisterDefs.h)
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* @param rreg rx data fifo level register (defined in RegisterDefs.h)
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* @param slreg scl low count register (defined in RegisterDefs.h)
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* @param shreg scl high count register (defined in RegisterDefs.h)
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* @param sdreg sda hold register (defined in RegisterDefs.h)
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* @param treg transfer command fifo register (defined in RegisterDefs.h)
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*/
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void I2C_ConfigureI2CCore(uint32_t creg, uint32_t rreg, uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg) {
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FILE_LOG(logINFO, ("\tConfiguring I2C Core for %d kbps:\n", I2C_DATA_RATE_KBPS));
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I2C_Control_Reg = creg;
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I2C_Rx_Data_Fifo_Level_Reg = rreg;
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I2C_Scl_Low_Count_Reg = slreg;
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I2C_Scl_High_Count_Reg = shreg;
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I2C_Sda_Hold_Reg = sdreg;
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I2C_Transfer_Command_Fifo_Reg = treg;
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// calculate scl low and high period count
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uint32_t sclPeriodNs = ((1000.00 * 1000.00) / (double)I2C_DATA_RATE_KBPS);
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// scl low period same as high period
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uint32_t sclLowPeriodNs = sclPeriodNs / 2;
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// convert to us, then to clock (defined in blackfin.h)
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uint32_t sclLowPeriodCount = (sclLowPeriodNs / 1000.00) * I2C_CLOCK_MHZ;
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// calculate sda hold data count
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uint32_t sdaDataHoldTimeNs = (sclLowPeriodNs / 2); // scl low period same as high period
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// convert to us, then to clock (defined in blackfin.h)
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uint32_t sdaDataHoldCount = ((sdaDataHoldTimeNs / 1000.00) * I2C_CLOCK_MHZ);
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FILE_LOG(logINFO, ("\tSetting SCL Low Period: %d ns (%d clocks)\n", sclLowPeriodNs, sclLowPeriodCount));
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bus_w(I2C_Scl_Low_Count_Reg, sclLowPeriodCount);
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FILE_LOG(logINFO, ("\tSetting SCL High Period: %d ns (%d clocks)\n", sclLowPeriodNs, sclLowPeriodCount));
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bus_w(I2C_Scl_High_Count_Reg, sclLowPeriodCount);
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FILE_LOG(logINFO, ("\tSetting SDA Hold Time: %d ns (%d clocks)\n", sdaDataHoldTimeNs, sdaDataHoldCount));
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bus_w(I2C_Sda_Hold_Reg, (uint32_t)sdaDataHoldCount);
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FILE_LOG(logINFO, ("\tEnabling core\n"));
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bus_w(I2C_Control_Reg, I2C_CTRL_ENBLE_CORE_MSK | I2C_CTRL_BUS_SPEED_FAST_400_VAL);// fixme: (works?)
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}
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/**
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* Read register
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* @param deviceId device Id
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* @param addr register address
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* @returns value read from register
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*/
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uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
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FILE_LOG(logDEBUG1, ("\tReading from I2C device 0x%x and reg 0x%x\n", devId, addr));
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// device Id mask
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uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
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// write I2C ID
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bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
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// write register addr
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bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
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// repeated start with read
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bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
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// continue reading
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bus_w(I2C_Transfer_Command_Fifo_Reg, 0x0);
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// stop reading
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bus_w(I2C_Transfer_Command_Fifo_Reg, I2C_TFR_CMD_STOP_MSK);
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// read value
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return bus_r(I2C_Rx_Data_Fifo_Level_Reg);
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}
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/**
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* Write register (16 bit value)
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* @param deviceId device Id
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* @param addr register address
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* @param data data to be written (16 bit)
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*/
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void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data) {
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FILE_LOG(logDEBUG1, ("Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId, addr, data));
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// device Id mask
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uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
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// write I2C ID
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bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
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// write register addr
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bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
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// repeated start with write
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bus_w(I2C_Transfer_Command_Fifo_Reg, ((devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK) & ~(I2C_TFR_CMD_RW_MSK)));
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uint8_t msb = (uint8_t)((data & 0xFF00) >> 8);
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uint8_t lsb = (uint8_t)(data & 0x00FF);
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// writing data MSB
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bus_w(I2C_Transfer_Command_Fifo_Reg, ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
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// writing data LSB and stop writing bit
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bus_w(I2C_Transfer_Command_Fifo_Reg, ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK);
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}
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