mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-04-22 03:14:38 +02:00
576 lines
19 KiB
Python
576 lines
19 KiB
Python
import pytest, sys, traceback
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from pathlib import Path
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current_dir = Path(__file__).resolve().parents[2]
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scripts_dir = current_dir / "tests" / "scripts"
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sys.path.append(str(scripts_dir))
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print(sys.path)
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from utils_for_test import (
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Log,
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LogLevel,
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)
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from slsdet import Detector
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@pytest.mark.detectorintegration
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def test_define_reg(session_simulator, request):
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""" Test setting define_reg for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.define_reg(name="test_reg", addr=RegisterAddress(0x200)) # valid
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d.define_reg(name="test_reg", addr=addr1) # takes a register address
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d.define_reg(name="test_reg2", addr=0x202) # takes an int
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# not using keyword arguments
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with pytest.raises(TypeError) as exc_info:
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d.define_reg("randomreg", 0x203)
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# invalid value type
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg3", addr='0x203')
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assert "addr must int or RegisterAddress" in str(exc_info.value)
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# defining with duplicate value
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg3", addr=addr1)
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assert "Value already assigned" in str(exc_info.value)
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assert(d.getRegisterAddress("test_reg") == addr1)
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assert(d.getRegisterName(addr1) == "test_reg")
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# accessing non existent reg name
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with pytest.raises(Exception) as exc_info:
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d.reg['random_reg']
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assert "No entry found for key" in str(exc_info.value)
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# get non existing reg address
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with pytest.raises(Exception) as exc_info:
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d.getRegisterName(RegisterAddress(0x300))
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assert "No entry found for value" in str(exc_info.value)
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d.clearRegisterDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg", addr=0x201)
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assert "Register Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_define_bit(session_simulator, request):
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""" Test setting define_bit for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.define_reg(name="test_reg1", addr=addr1)
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d.define_reg(name="test_reg2", addr=addr2)
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# not using keyword arguments
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with pytest.raises(TypeError) as exc_info:
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d.define_bit("randombit", 0x203, 1)
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# invalid value type (bit=string)
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with pytest.raises(ValueError) as exc_info:
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position='1')
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# invalid bit_position
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position=32)
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assert "Bit position must be between 0 and 31" in str(exc_info.value)
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# defining with random reg value
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name='test_bit1', addr='random_reg', bit_position=1)
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assert "No entry found for key" in str(exc_info.value)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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# defining bit address with bit_position as well
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with pytest.raises(ValueError) as exc_info:
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d.define_bit(name='test_bit1', addr=bit1, bit_position=1)
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assert "bit_position must be None" in str(exc_info.value)
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d.define_bit(name="test_bit1", addr='test_reg2', bit_position=1)
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position=1) # modify reg
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d.define_bit(name='test_bit1', addr=bit1) # modify pos
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d.define_bit(name="test_bit2", addr=0x201, bit_position=4) # int addr
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d.define_bit(name="test_bit3", addr=addr2, bit_position=3) # RegisterAddress addr
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assert(d.getBitAddress('test_bit1') == bit1)
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assert(d.getBitAddress('test_bit2') == bit2)
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assert(d.getBitAddress('test_bit3') == bit3)
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assert(d.getBitAddress('test_bit1').address() == addr1)
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assert(d.getBitAddress('test_bit1').bitPosition() == 2)
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assert(d.getBitAddress('test_bit2') == BitAddress(addr1, 4))
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assert(d.getBitName(bit1) == 'test_bit1')
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assert(d.getBitName(bit2) == 'test_bit2')
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assert(d.getBitName(bit3) == 'test_bit3')
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assert(d.getBitName(BitAddress(addr2,3)) == 'test_bit3')
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# bit doesnt exist for that reg
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with pytest.raises(Exception) as exc_info:
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d.getBitName(BitAddress(addr1, 5))
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assert "No entry found for value" in str(exc_info.value)
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# addr doesnt exist for that reg
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with pytest.raises(Exception) as exc_info:
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d.getBitName(BitAddress(RegisterAddress(0x300), 5))
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assert "No entry found for value" in str(exc_info.value)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_using_defined_reg_and_bit(session_simulator, request):
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""" Test using defined reg and bit define_bit for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.setRegisterDefinition('test_reg1', addr1)
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d.setRegisterDefinition('test_reg2', addr2)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setBitDefinition('test_bit1', bit1)
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d.setBitDefinition('test_bit2', bit2)
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d.setBitDefinition('test_bit3', bit3)
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prev_val_addr1 = d.reg[addr1]
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prev_val_addr2 = d.reg[addr2]
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# reg name doesnt exist
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with pytest.raises(Exception) as exc_info:
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d.reg['random_reg']
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.setBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.clearBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.getBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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# bit name doesnt exist
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with pytest.raises(Exception) as exc_info:
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d.setBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.clearBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.getBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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d.reg['test_reg1'] = RegisterValue(0x0)
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assert(d.reg['test_reg1'].value() == 0x0)
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d.reg['test_reg1'] = RegisterValue(0x10)
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assert(d.reg['test_reg1'].value() == 0x10)
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d.setBit('test_bit1')
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assert(d.reg['test_reg1'].value() == 0x14) # 0x10 | (1 << 2)
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d.clearBit('test_bit1')
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assert(d.reg['test_reg1'].value() == 0x10)
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assert(d.getBit('test_bit1') == 0)
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# restore previous values
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d.reg[addr1] = prev_val_addr1
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d.reg[addr2] = prev_val_addr2
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_definelist_reg(session_simulator, request):
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""" Test using definelist_reg for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setRegisterDefinitions({
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'test_reg1': RegisterAddress(0x201),
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'test_reg2': RegisterAddress(0x202)
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})
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res = d.getRegisterDefinitions()
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assert(res['test_reg1'] == addr1)
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assert(res['test_reg2'] == addr2)
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assert(len(res) == 2)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_definelist_bit(session_simulator, request):
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""" Test using definelist_bit for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setRegisterDefinitions({
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'test_reg1': RegisterAddress(0x201),
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'test_reg2': RegisterAddress(0x202)
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})
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d.setBitDefinitions({
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'test_bit1': BitAddress(addr1, 2),
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'test_bit2': BitAddress(addr1, 4),
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'test_bit3': BitAddress(addr2, 3)
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})
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res = d.getBitDefinitions()
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assert(len(res) == 3)
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assert(res['test_bit1'] == bit1)
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assert(res['test_bit2'] == bit2)
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assert(res['test_bit3'] == bit3)
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assert(res['test_bit2'].address() == addr1)
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assert(res['test_bit2'].bitPosition() == 4)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_parameters_file(session_simulator, request):
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""" Test using test_parameters_file."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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with open("/tmp/params.det", "w") as f:
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f.write("frames 2\n")
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f.write("fwrite 1\n")
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# this should not throw
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d.parameters = "/tmp/params.det"
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assert d.frames == 2
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assert d.fwrite == 1
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Log(LogLevel.INFOGREEN, f"✅ Test passed. Command: parameters")
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@pytest.mark.detectorintegration
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def test_include_file(session_simulator, request):
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""" Test using test_include_file."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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with open("/tmp/params.det", "w") as f:
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f.write("frames 3\n")
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f.write("fwrite 0\n")
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# this should not throw
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d.include = "/tmp/params.det"
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assert d.frames == 3
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assert d.fwrite == 0
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Log(LogLevel.INFOGREEN, f"✅ Test passed. Command: include")
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@pytest.mark.detectorintegration
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def test_patternstart(session_simulator, request):
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""" Test using patternstart for ctb, xilinx_ctb and mythen3."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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if det_type in ['ctb', 'xilinx_ctb', 'mythen3']:
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d.patternstart()
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else:
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with pytest.raises(Exception) as exc_info:
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d.patternstart()
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assert "not implemented" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_runclk(session_simulator, request):
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""" Test using runclk for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import Hz, MHz, kHz
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_runclk = d.getRUNClock()
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d.runclk
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# invalid value type
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with pytest.raises(Exception) as exc_info:
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d.runclk = 5e6
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with pytest.raises(Exception) as exc_info:
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d.runclk = 5 * 1000 * 1000
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with pytest.raises(Exception) as exc_info:
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d.runclk = Hz(5e6)
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d.runclk = MHz(5)
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assert d.runclk.value == 5_000_000
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d.runclk = MHz(4.5)
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assert d.runclk.value == 4_500_000
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d.runclk = kHz(5000.5)
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assert d.runclk.value == 5_000_500
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# invalid values from server
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# max is 300MHz
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with pytest.raises(Exception) as exc_info:
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d.runclk = MHz(301)
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# min is 2MHz for ctb and 10MHz for xilinx_ctb
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if det_type == 'ctb':
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with pytest.raises(Exception) as exc_info:
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d.runclk = MHz(1)
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else:
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with pytest.raises(Exception) as exc_info:
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d.runclk = MHz(9)
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c = MHz(2)
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for rc in [5, 10, 15, 20]:
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d.runclk = rc * c
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assert d.runclk.value == 40_000_000
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for i in range(len(d)):
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d.setRUNClock(prev_runclk[i], [i])
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.detectorintegration
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def test_adcclk(session_simulator, request):
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""" Test using adcclk for ctb and xilinx_ctb."""
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det_type, num_interfaces, num_mods, d = session_simulator
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assert d is not None
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from slsdet import Hz, MHz, kHz
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if det_type in ['ctb', 'xilinx_ctb']:
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prev_adcclk = d.getADCClock()
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d.adcclk
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# invalid value type
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with pytest.raises(Exception) as exc_info:
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d.adcclk = 5e6
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with pytest.raises(Exception) as exc_info:
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d.adcclk = 5 * 1000 * 1000
|
|
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.adcclk = Hz(5e6)
|
|
|
|
d.adcclk = MHz(5)
|
|
assert d.adcclk.value == 5_000_000
|
|
|
|
d.adcclk = MHz(4.5)
|
|
assert d.adcclk.value == 4_500_000
|
|
|
|
d.adcclk = kHz(5000.5)
|
|
assert d.adcclk.value == 5_000_500
|
|
|
|
# invalid values from server
|
|
# max is 300MHz
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.adcclk = MHz(301)
|
|
|
|
# min is 2MHz for ctb and 10MHz for xilinx_ctb
|
|
if det_type == 'ctb':
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.adcclk = MHz(1)
|
|
else:
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.adcclk = MHz(9)
|
|
|
|
c = MHz(2)
|
|
for rc in [5, 10, 15, 20]:
|
|
d.adcclk = rc * c
|
|
assert d.adcclk.value == 40_000_000
|
|
|
|
for i in range(len(d)):
|
|
d.setADCClock(prev_adcclk[i], [i])
|
|
|
|
Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
|
|
|
|
|
|
@pytest.mark.detectorintegration
|
|
def test_dbitclk(session_simulator, request):
|
|
""" Test using dbitclk for ctb and xilinx_ctb."""
|
|
det_type, num_interfaces, num_mods, d = session_simulator
|
|
assert d is not None
|
|
|
|
from slsdet import Hz, MHz, kHz
|
|
|
|
if det_type in ['ctb', 'xilinx_ctb']:
|
|
prev_dbitclk = d.getDBITClock()
|
|
|
|
d.dbitclk
|
|
|
|
# invalid value type
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.dbitclk = 5e6
|
|
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.dbitclk = 5 * 1000 * 1000
|
|
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.dbitclk = Hz(5e6)
|
|
|
|
d.dbitclk = MHz(5)
|
|
assert d.dbitclk.value == 5_000_000
|
|
|
|
d.dbitclk = MHz(4.5)
|
|
assert d.dbitclk.value == 4_500_000
|
|
|
|
d.dbitclk = kHz(5000.5)
|
|
assert d.dbitclk.value == 5_000_500
|
|
|
|
# invalid values from server
|
|
# max is 300MHz
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.dbitclk = MHz(301)
|
|
|
|
# min is 2MHz for ctb and 10MHz for xilinx_ctb
|
|
if det_type == 'ctb':
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.dbitclk = MHz(1)
|
|
else:
|
|
with pytest.raises(Exception) as exc_info:
|
|
d.dbitclk = MHz(9)
|
|
|
|
c = MHz(2)
|
|
for rc in [5, 10, 15, 20]:
|
|
d.dbitclk = rc * c
|
|
assert d.dbitclk.value == 40_000_000
|
|
|
|
for i in range(len(d)):
|
|
d.setDBITClock(prev_dbitclk[i], [i])
|
|
|
|
Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
|
|
|
|
|
|
@pytest.mark.detectorintegration
|
|
def test_syncclk(session_simulator, request):
|
|
""" Test using syncclk for ctb."""
|
|
det_type, num_interfaces, num_mods, d = session_simulator
|
|
assert d is not None
|
|
|
|
if det_type in ['ctb']:
|
|
d.syncclk
|
|
|
|
Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed") |