mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-22 22:40:02 +02:00
177 lines
7.1 KiB
C
177 lines
7.1 KiB
C
#ifndef SLSDETECTORSERVER_DEFS_H
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#define SLSDETECTORSERVER_DEFS_H
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#include "sls_detector_defs.h" //default dynamicgain in settings
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#include "RegisterDefs.h"
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#include <stdint.h>
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#define GOODBYE (-200)
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#define PROGRAMMING_MODE (-200)
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#define MIN_REQRD_VRSN_T_RD_API 0x171220
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#define REQRD_FRMWR_VRSN 0x181206 // temp bug fix from last version, timing mode is backwards compatible
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/* Struct Definitions */
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typedef struct ip_header_struct {
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uint16_t ip_len;
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uint8_t ip_tos;
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uint8_t ip_ihl:4 ,ip_ver:4;
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uint16_t ip_offset:13,ip_flag:3;
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uint16_t ip_ident;
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uint16_t ip_chksum;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint32_t ip_sourceip;
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uint32_t ip_destip;
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} ip_header;
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/* Enums */
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enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
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enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
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enum DACINDEX {VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP };
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#define DEFAULT_DAC_VALS { 1220, /* VB_COMP */ \
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3000, /* VDD_PROT */ \
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1053, /* VIN_COM */ \
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1450, /* VREF_PRECH */ \
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750, /* VB_PIXBUF */ \
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1000, /* VB_DS */ \
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480, /* VREF_DS */ \
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420 /* VREF_COMP */ \
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};
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enum NETWORKINDEX { TXN_FRAME };
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/* Hardware Definitions */
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#define NMAXMOD (1)
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#define NMOD (1)
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#define NCHAN (256 * 256)
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#define NCHIP (8)
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#define NADC (0)
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#define NDAC (8)
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#define NDAC_OLDBOARD (16)
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#define DYNAMIC_RANGE (16)
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#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define IP_PACKETSIZE (0x2052)
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#define CLK_RUN (40) /* MHz */
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#define CLK_SYNC (20) /* MHz */
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (100*1000*1000)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (10*1000) //ns
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#define DEFAULT_PERIOD (2*1000*1000) //ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_TMP_THRSHLD (65*1000) //milli degree Celsius
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#define DEFAULT_NUM_STRG_CLLS (0)
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#define DEFAULT_STRG_CLL_STRT (0xf)
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/* Defines in the Firmware */
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#define MAX_TIMESLOT_VAL (0x1F)
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#define MAX_THRESHOLD_TEMP_VAL (127999) //millidegrees
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#define MAX_STORAGE_CELL_VAL (15) //0xF
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#define ACQ_TIME_MIN_CLOCK (2)
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#define SAMPLE_ADC_HALF_SPEED (SAMPLE_DECMT_FACTOR_2_VAL + SAMPLE_DGTL_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x1000 */
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#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_DECMT_FACTOR_4_VAL + SAMPLE_DGTL_SAMPLE_8_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_ADC_SAMPLE_0_VAL) /* 0x2810 */
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#define CONFIG_HALF_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_HALF_SPEED_20MHZ_VAL + CONFIG_OPRTN_MDE_1_X_10GBE_VAL)
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#define CONFIG_QUARTER_SPEED (CONFIG_TDMA_DISABLE_VAL + CONFIG_QUARTER_SPEED_10MHZ_VAL + CONFIG_OPRTN_MDE_1_X_10GBE_VAL)
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#define ADC_OFST_HALF_SPEED_VAL (0x1f) //(0x20)
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#define ADC_OFST_QUARTER_SPEED_VAL (0x0f) //(0x0f)
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#define ADC_PHASE_HALF_SPEED (0x2D) //45
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#define ADC_PHASE_QUARTER_SPEED (0x2D) //45
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#define ADC_PORT_INVERT_VAL (0x453b2a9c)
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/* Maybe not required for jungfrau */
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#define NTRIMBITS (6)
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#define NCOUNTBITS (24)
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#define NCHIPS_PER_ADC (2)
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#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
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#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
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#define ALLMOD (0xffff)
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#define ALLFIFO (0xffff)
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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#define LSB_OF_64_BIT_REG_OFST (0)
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#define BIT_32_MSK (0xFFFFFFFF)
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/* LTC2620 DAC DEFINES */
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#define LTC2620_DAC_CMD_OFST (20)
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#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_ADDR_OFST (16)
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#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
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#define LTC2620_DAC_DATA_OFST (4)
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#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
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#define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_NUMBITS (24)
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/* MAX1932 HV DEFINES */
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#define MAX1932_HV_NUMBITS (8)
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#define MAX1932_HV_DATA_OFST (0)
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#define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST)
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/** PLL Reconfiguration Registers */
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//https://www.altera.com/documentation/mcn1424769382940.html
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#define PLL_MODE_REG (0x00)
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#define PLL_STATUS_REG (0x01)
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#define PLL_START_REG (0x02)
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#define PLL_N_COUNTER_REG (0x03)
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#define PLL_M_COUNTER_REG (0x04)
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#define PLL_C_COUNTER_REG (0x05)
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#define PLL_PHASE_SHIFT_REG (0x06)
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#define PLL_SHIFT_NUM_SHIFTS_OFST (0)
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#define PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
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#define PLL_SHIFT_CNT_SELECT_OFST (16)
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#define PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
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#define PLL_SHIFT_CNT_SLCT_C0_VAL ((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C1_VAL ((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C2_VAL ((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C3_VAL ((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C4_VAL ((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C5_VAL ((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C6_VAL ((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C7_VAL ((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C8_VAL ((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C9_VAL ((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C10_VAL ((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C11_VAL ((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C12_VAL ((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C13_VAL ((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C14_VAL ((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C15_VAL ((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C16_VAL ((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C17_VAL ((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_UP_DOWN_OFST (21)
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#define PLL_SHIFT_UP_DOWN_MSK (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
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#define PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
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#define PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
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#define PLL_K_COUNTER_REG (0x07)
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#define PLL_BANDWIDTH_REG (0x08)
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#define PLL_CHARGEPUMP_REG (0x09)
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#define PLL_VCO_DIV_REG (0x1c)
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#define PLL_MIF_REG (0x1f)
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#endif /* SLSDETECTORSERVER_DEFS_H */
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