mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-05-16 02:15:37 +02:00
Martin Mueller
0837de2a5a
* round CTB clocks to next closest possible value, added freq measurement * added time for firmware to measrue actual value after frequency change * add check for backwards compatibility * change CTB and XCTB clock values to MHz, TODO: units and validation errors * changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ? * do the same for dbit and adcclk * added tolerance to exptime, fixed test * update default values in server defs * added virtual check in Altera_PLL, update testcases * change python and pyctbgui to accept and return floating point MHz * update help and comments * Dev/ctb clocks fix (#1434) * introduced new type Hz, typetraits, String conversions, command generation (not yet generated) * incorrect unit typo * cmd generation and compiles * default to MHz, removed space between units for consistency with timers, min and max checks for clks * in python, but need to change the default to Hz again for clean code and intuition * allow ints, doubles, implicit conversions * dont allow raw ints, doubles and implicit conversions * fixed tests * added operators for Hz in python * fix test for min clk for xilinx ctb * fix test * fix python tests * fixed xilinx period and default clks * test fix * removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb * removing 3 clock cycle code from xilinx as well * formatting * loadpattern before 3 clk cycles code * actualtime and measurement time to be implemented in 100ns already in fw * fix tests * pyzmq dependency forthe tests * fixed pyctbgui for freq * insert tolerance check again * also added tolerance check for patwaittime * formatting * minor: rounding test * removed Rep redundant in ToString for freq * intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary * minor, and binaries * minor, default clk vals are 0 but set up at detector setup * get frequency only for that unit * tolerance process * missed in previous commit * some more changes to exptime and validations * ctb is probably done * periodleft and delayleft * fixed xilinx freq conv as well * fixed m3 bug, binaries * xilinx: setup also done in stop server so that the clk is not 0 * missed a test marker * binaries in * review fixes, simpler validation of timers in ctb and xilinx ctb * typo fix * format * fix tests --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include <inttypes.h>
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#if defined(JUNGFRAUD)
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/**
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* Set Defines
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* @param creg control register
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* @param preg parameter register
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* @param rprmsk reconfig parameter reset mask
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* @param wpmsk write parameter mask
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* @param prmsk pll reset mask
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* @param amsk address mask
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* @param aofst address offset
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* @param wd2msk write parameter mask for pll for dbit clock (Jungfrau only)
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* @param clk2Index clkIndex of second pll (Jungfrau only)
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*/
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void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
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uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
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int aofst, uint32_t wd2msk, int clk2Index);
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#elif defined(CHIPTESTBOARDD)
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void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
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uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
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int aofst, uint32_t freqreg);
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#else
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/**
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* Set Defines
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* @param creg control register
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* @param preg parameter register
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* @param rprmsk reconfig parameter reset mask
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* @param wpmsk write parameter mask
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* @param prmsk pll reset mask
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* @param amsk address mask
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* @param aofst address offset
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*/
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void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
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uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
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int aofst);
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#endif
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/**
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* Reset only PLL
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*/
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void ALTERA_PLL_ResetPLL();
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/**
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* Reset PLL Reconfiguration and PLL
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*/
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void ALTERA_PLL_ResetPLLAndReconfiguration();
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/**
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* Set PLL Reconfig register
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* @param reg register
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* @param val value
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* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use
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* second WR mask)
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*/
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void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
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int useSecondWRMask);
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/**
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* Write Phase Shift
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* @param phase phase shift
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* @param clkIndex clock index
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* @param pos 1 if up down direction of shift is positive, else 0
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*/
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void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos);
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/**
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* Set PLL mode register to polling mode
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*/
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void ALTERA_PLL_SetModePolling();
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/**
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* Calculate and write output frequency
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* @param clkIndex clock index
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* @param pllVCOFreqHz PLL VCO Frequency in Hz
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* @param value frequency to set to
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* @param frequency set
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*/
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int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqHz, int value);
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/**
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* get measured clock frequency
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*/
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#if defined(CHIPTESTBOARDD)
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uint32_t ALTERA_PLL_getFrequency(uint32_t clkIDX);
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#endif
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