mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-05-20 08:46:48 +02:00
Martin Mueller
0837de2a5a
* round CTB clocks to next closest possible value, added freq measurement * added time for firmware to measrue actual value after frequency change * add check for backwards compatibility * change CTB and XCTB clock values to MHz, TODO: units and validation errors * changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ? * do the same for dbit and adcclk * added tolerance to exptime, fixed test * update default values in server defs * added virtual check in Altera_PLL, update testcases * change python and pyctbgui to accept and return floating point MHz * update help and comments * Dev/ctb clocks fix (#1434) * introduced new type Hz, typetraits, String conversions, command generation (not yet generated) * incorrect unit typo * cmd generation and compiles * default to MHz, removed space between units for consistency with timers, min and max checks for clks * in python, but need to change the default to Hz again for clean code and intuition * allow ints, doubles, implicit conversions * dont allow raw ints, doubles and implicit conversions * fixed tests * added operators for Hz in python * fix test for min clk for xilinx ctb * fix test * fix python tests * fixed xilinx period and default clks * test fix * removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb * removing 3 clock cycle code from xilinx as well * formatting * loadpattern before 3 clk cycles code * actualtime and measurement time to be implemented in 100ns already in fw * fix tests * pyzmq dependency forthe tests * fixed pyctbgui for freq * insert tolerance check again * also added tolerance check for patwaittime * formatting * minor: rounding test * removed Rep redundant in ToString for freq * intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary * minor, and binaries * minor, default clk vals are 0 but set up at detector setup * get frequency only for that unit * tolerance process * missed in previous commit * some more changes to exptime and validations * ctb is probably done * periodleft and delayleft * fixed xilinx freq conv as well * fixed m3 bug, binaries * xilinx: setup also done in stop server so that the clk is not 0 * missed a test marker * binaries in * review fixes, simpler validation of timers in ctb and xilinx ctb * typo fix * format * fix tests --------- Co-authored-by: Martin Mueller <martin.mueller@psi.ch> Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
178 lines
5.0 KiB
C
178 lines
5.0 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include "RegisterDefs.h"
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#include "sls/sls_detector_defs.h"
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#define MIN_REQRD_VRSN_T_RD_API 0x181130
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#define REQRD_FRMWR_VRSN 0x260504
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#define NUM_HARDWARE_VERSIONS (1)
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#define HARDWARE_VERSION_NUMBERS \
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{ 0x3f }
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#define HARDWARE_VERSION_NAMES \
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{ "5.1" }
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#define LINKED_SERVER_NAME "ctbDetectorServer"
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#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
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/* Hardware Definitions */
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#define NCHAN (40)
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#define NCHAN_ANALOG (32)
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#define NCHAN_DIGITAL (64)
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#define NCHAN_TRANSCEIVER (4)
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#define NBITS_PER_TRANSCEIVER (64)
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#define NCHIP (1)
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#define NDAC (24)
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#define NPWR (6)
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#define NDAC_ONLY (NDAC - NPWR)
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define CLK_FREQ (156.25) // MHz
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/** Default Parameters */
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#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define DEFAULT_STARTING_FRAME_NUMBER (1)
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#define DEFAULT_NUM_SAMPLES (1)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_EXPTIME (0)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_VLIMIT (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_RUN_CLK (80000000) // 80 MHz
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#define DEFAULT_ADC_CLK (40000000) // 40 MHz
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#define DEFAULT_SYNC_CLK (40000000) // 40 MHz
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#define DEFAULT_DBIT_CLK (200000000) // 200 MHz
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#define NS_TO_CLK_CYCLE (1E-9) // ns to MHz
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#define DEFAULT_TRANSCEIVER_MASK (0x3)
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#define MIN_CLK_FREQ (2000000) // 2 MHz
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#define MAX_CLK_FREQ (300000000) // 300 MHz
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#define MAX_TRANSCEIVER_MASK (0xF)
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#define MAX_TRANSCEIVER_SAMPLES (0xFFFF)
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#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
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#define HIGHVOLTAGE_MIN (60)
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#define HIGHVOLTAGE_MAX (200) // min dac val
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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#define VCHIP_MIN_MV (1673)
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#define VCHIP_MAX_MV (2668) // min dac val
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#define POWER_RGLTR_MIN (636)
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#define POWER_RGLTR_MAX \
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(2638) // min dac val (not vchip-max) because of dac conversions
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#define VCHIP_POWER_INCRMNT (200)
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#define VIO_MIN_MV (1200) // for fpga to function
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/* Defines in the Firmware */
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#define DIGITAL_IO_DELAY_MAXIMUM_PS \
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((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
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OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
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#define MAX_PHASE_SHIFTS_STEPS (8)
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#define WAIT_TME_US_FR_ACQDONE_REG \
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(100) // wait time in us after acquisition done to ensure there is no data
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// in fifo
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#define WAIT_TIME_US_PLL (10 * 1000)
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#define WAIT_TIME_US_STP_ACQ (100)
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#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
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#define WAIT_TIME_PATTERN_READ (10)
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#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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#define LSB_OF_64_BIT_REG_OFST (0)
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#define BIT32_MSK (0xFFFFFFFF)
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#define BIT16_MASK (0xFFFF)
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#define MAXIMUM_ADC_CLK (65000000) // 65 MHz
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#define PLL_VCO_FREQ_HZ (800000000) // 800MHz
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl : 4, ip_ver : 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset : 13, ip_flags : 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define IP_HEADER_SIZE (20)
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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/* Enums */
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enum ADCINDEX {
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V_PWR_IO,
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V_PWR_A,
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V_PWR_B,
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V_PWR_C,
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V_PWR_D,
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I_PWR_IO,
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I_PWR_A,
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I_PWR_B,
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I_PWR_C,
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I_PWR_D,
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S_ADC0,
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S_ADC1,
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S_ADC2,
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S_ADC3,
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S_ADC4,
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S_ADC5,
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S_ADC6,
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S_ADC7,
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S_TMP
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};
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enum DACINDEX {
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D0,
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D1,
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D2,
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D3,
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D4,
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D5,
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D6,
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D7,
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D8,
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D9,
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D10,
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D11,
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D12,
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D13,
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D14,
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D15,
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D16,
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D17,
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D_PWR_D,
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D_PWR_CHIP,
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D_PWR_C,
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D_PWR_B,
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D_PWR_A,
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D_PWR_IO
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};
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#define PWR_NAMES "VA", "VB", "VC", "VD", "VIO"
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enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
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#define CLK_NAMES "run", "adc", "sync", "dbit"
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