mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-19 18:40:01 +02:00
d23722a4b7
* eiger: hardwareversion, fix firmware version unable to read version scenarios, check to see if febl, febr and beb have same fw version * feb versions can be picked up only after feb initialization
160 lines
5.9 KiB
C
160 lines
5.9 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include "sls/sls_detector_defs.h"
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#define LINKED_SERVER_NAME "eigerDetectorServer"
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#define NUM_HARDWARE_VERSIONS (2)
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#define HARDWARE_VERSION_NUMBERS {0x0, 0x1};
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#define HARDWARE_VERSION_NAMES \
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{ "FX70T", "FX30T" }
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#define REQUIRED_FIRMWARE_VERSION (31)
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// virtual ones renamed for consistency
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// real ones keep previous name for compatibility (already in production)
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#ifdef VIRTUAL
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#define ID_FILE "detid_eiger.txt"
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#else
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#define ID_FILE "detid.txt"
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#endif
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#define CONFIG_FILE ("config_eiger.txt")
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#define WAIT_STOP_SERVER_START (1 * 1000 * 1000)
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#define STATUS_IDLE 0
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#define STATUS_RUNNING 1
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#define STATUS_ERROR 2
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/* Enums */
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enum DACINDEX {
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E_VSVP,
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E_VTRIM,
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E_VRPREAMP,
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E_VRSHAPER,
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E_VSVN,
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E_VTGSTV,
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E_VCMP_LL,
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E_VCMP_LR,
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E_VCAL,
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E_VCMP_RL,
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E_RXB_RB,
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E_RXB_LB,
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E_VCMP_RR,
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E_VCP,
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E_VCN,
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E_VISHAPER,
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E_VTHRESHOLD
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};
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#define DAC_NAMES \
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"VSvP", "Vtrim", "Vrpreamp", "Vrshaper", "VSvN", "Vtgstv", "Vcmp_ll", \
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"Vcmp_lr", "Vcal", "Vcmp_rl", "rxb_rb", "rxb_lb", "Vcmp_rr", "Vcp", \
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"Vcn", "Vishaper", "Vthreshold"
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#define DEFAULT_DAC_VALS \
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{ \
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0, /* VSvP */ \
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2480, /* Vtrim */ \
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3300, /* Vrpreamp */ \
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1400, /* Vrshaper */ \
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4000, /* VSvN */ \
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2556, /* Vtgstv */ \
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1000, /* Vcmp_ll */ \
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1000, /* Vcmp_lr */ \
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0, /* Vcal */ \
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1000, /* Vcmp_rl */ \
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1100, /* rxb_rb */ \
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1100, /* rxb_lb */ \
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1000, /* Vcmp_rr */ \
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1000, /* Vcp */ \
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2000, /* Vcn */ \
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1550 /* Vishaper */ \
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};
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enum ADCINDEX {
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TEMP_FPGAEXT,
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TEMP_10GE,
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TEMP_DCDC,
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TEMP_SODL,
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TEMP_SODR,
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TEMP_FPGA,
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TEMP_FPGAFEBL,
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TEMP_FPGAFEBR
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};
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#define ADC_NAMES \
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"FPGA EXT", "10GE", "DCDC", "SODL", "SODR", "FPGA", "FPGA_FL", "FPGA_FR"
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enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
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enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
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enum CLKINDEX { RUN_CLK, NUM_CLOCKS };
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enum TOPINDEX { TOP_HARDWARE, OW_TOP, OW_BOTTOM };
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#define TOP_NAMES "hardware", "top", "bottom"
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enum MASTERINDEX { MASTER_HARDWARE, OW_MASTER, OW_SLAVE };
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#define MASTER_NAMES "hardware", "master", "slave"
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#define CLK_NAMES "run"
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/* Hardware Definitions */
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#define NCHAN (256 * 256)
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#define NCHIP (4)
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#define NDAC (16)
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#define TEN_GIGA_BUFFER_SIZE (4112)
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#define ONE_GIGA_BUFFER_SIZE (1040)
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#define TEN_GIGA_CONSTANT (4)
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#define ONE_GIGA_CONSTANT (16)
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#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
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#define NORMAL_HIGHVOLTAGE_OUTPUTPORT \
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"/sys/class/hwmon/hwmon5/device/out0_output"
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#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
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#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
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#define DEFAULT_UDP_SOURCE_PORT (0xE185)
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_STARTING_FRAME_NUMBER (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (1E9) // ns
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#define DEFAULT_PERIOD (1E9) // ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_SUBFRAME_EXPOSURE (2621440) // 2.6ms
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#define DEFAULT_SUBFRAME_DEADTIME (0)
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#define DEFAULT_DYNAMIC_RANGE (16)
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#define DEFAULT_PARALLEL_MODE (1)
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#define DEFAULT_READOUT_OVERFLOW32_MODE (0)
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#define DEFAULT_CLK_SPEED (FULL_SPEED)
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#define DEFAULT_IO_DELAY (650)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_PHOTON_ENERGY (-1)
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#define DEFAULT_RATE_CORRECTION (0)
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#define DEFAULT_EXT_GATING_ENABLE (0)
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#define DEFAULT_EXT_GATING_POLARITY (1) // positive
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#define DEFAULT_TEST_MODE (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define MAX_TRIMBITS_VALUE (63)
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#define MIN_ROWS_PER_READOUT (1)
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#define MAX_ROWS_PER_READOUT (256)
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#define MAX_PACKETS_PER_REQUEST (256)
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#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
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#define BIT16_MASK (0xFFFF)
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#define BIT32_MSK (0xFFFFFFFF)
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2048)
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#define LTC2620_MIN_VAL \
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(0) // including LTC defines instead of LTC262.h (includes bit banging and
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// blackfin read and write)
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#define LTC2620_MAX_VAL (4095) // 12 bits
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#define DAC_MAX_STEPS (4096)
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#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS \
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(0x1FFFFFFF) // 29 bit register for max subframe exposure value
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#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
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#define HIGH_VOLTAGE_TOLERANCE (5)
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