mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-01-13 08:38:14 +01:00
Dhanya Thattil
3dd07bf2be
* basic ctb config api for register and bit names * tests for define and definelist pass. yet to implement using them for reg, setbit, clearbit and getbit * improved autocomplete for getbit,setbit, clearbit * validate autocomplete * definelist has no put * updating help * converting char array+int in runtimeerror compiles but throws at runtime.Fixed.Tested for it. Also check if string or int before using getregisterdefinitonbyvalue to see if it threw to call the other function. because both of it can throw and we should differentiate the issues for both * removed std::vector<std::pair<string,int> to std::map<string, int> for defiitions list * Dev/define cmd tie bit to reg (#1328) * strong type * moved everythign to bit_utils class * pybindings * added tests for python * removed duplicates * removed bit names in reg * changed BitPosition to BitAddress * Using define reg/bit from python (#1344) * define_bit, define_addr in python. * setBit/clearBit takes int or addr * added example using bits * split define into 2 commands define_reg and define_bit, definelist into 2: definelist_reg and definelist_bit * allow string for register and bit names in c++ api * refactor from github comments * naming refactoring (getRegisterDefnition to retunr name and address specifically * added marker for 8 cmd tests connected to define, changed macro to static constexpr * changed bitPosition from int to uint32_t * got rid of setbitposition and setaddress, instead overloaded constructor to take in strings so that the conversion from string to bit address members, takes place within the class for easy maintainance in case type changes * Removing implicit conversions: RegisterAddresss and RegisterValue: Removed the implicit conversions. RegisterAddress: Changed member name from address_ to value_ and method as well to value(). RegisterValue: Also added | operator to be able to concatenate with uint32_t. Same in python bindings (but could not find the tests to modify * Allowed concatenation with other RegisterValue, made them all constexpr * fix a ctbConfig test * Maponstack works with integration tests, but need unit tests * tests on mapstack * fixed ctb tests and FixedString being initialized with gibberish * removing parsing from string inside the class RegisterAddress, BitAddress and RegisterValue * updated python bindings * fixed bit utils test * renaming getRegisterDefintiionAddress/Name=>getRegisterAddress/Name and similary for getBitDefinitionAddress/Name * updated python bindings * fix tests (format) * a few python tests added and python bindings corrected * replaceing str with __str__ for bit.cpp * repr reimplemented for bit.cpp * removed make with registerAddress etc * starting server for tests per session and nor module * killprocess throws if no process found-> github runs fails, changed to pkill and not throw * clean shm shouldnt raise, in ci binary not found * ignoring these tests for CI, which fail on CI because simulators are not generated in CI. This is in another PR, where it should work --------- Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com> Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
385 lines
13 KiB
Python
385 lines
13 KiB
Python
'''
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cd python/tests
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Specific test: pytest -s -x test_CtbAPI.py::test_define_bit #-x=abort on first failure
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Specific test with specific server: pytest -s -x test_CtbAPI.py::test_define_reg[ctb]
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'''
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import pytest, sys, traceback
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from pathlib import Path
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current_dir = Path(__file__).resolve().parents[2]
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scripts_dir = current_dir / "tests" / "scripts"
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sys.path.append(str(scripts_dir))
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print(sys.path)
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from utils_for_test import (
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Log,
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LogLevel,
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cleanup,
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startDetectorVirtualServer,
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connectToVirtualServers,
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SERVER_START_PORTNO,
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)
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from slsdet import Detector, detectorType
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@pytest.fixture(
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scope="session",
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params=['ctb', 'xilinx_ctb', 'mythen3']
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)
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def simulator(request):
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"""Fixture to start the detector server once and clean up at the end."""
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det_name = request.param
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num_mods = 1
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fp = sys.stdout
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# set up: once per server
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Log(LogLevel.INFOBLUE, f'---- {det_name} ----')
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cleanup(fp)
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startDetectorVirtualServer(det_name, num_mods, fp)
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Log(LogLevel.INFOBLUE, f'Waiting for server to start up and connect')
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connectToVirtualServers(det_name, num_mods)
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yield det_name # tests run here
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cleanup(fp)
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@pytest.mark.withdetectorsimulators
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def test_define_reg(simulator, request):
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""" Test setting define_reg for ctb and xilinx_ctb."""
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det_name = simulator
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from slsdet import RegisterAddress
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d = Detector()
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d.hostname = f"localhost:{SERVER_START_PORTNO}"
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if det_name in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.define_reg(name="test_reg", addr=RegisterAddress(0x200)) # valid
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d.define_reg(name="test_reg", addr=addr1) # takes a register address
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d.define_reg(name="test_reg2", addr=0x202) # takes an int
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# not using keyword arguments
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with pytest.raises(TypeError) as exc_info:
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d.define_reg("randomreg", 0x203)
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# invalid value type
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg3", addr='0x203')
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assert "addr must int or RegisterAddress" in str(exc_info.value)
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# defining with duplicate value
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg3", addr=addr1)
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assert "Value already assigned" in str(exc_info.value)
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assert(d.getRegisterAddress("test_reg") == addr1)
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assert(d.getRegisterName(addr1) == "test_reg")
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# accessing non existent reg name
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with pytest.raises(Exception) as exc_info:
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d.reg['random_reg']
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assert "No entry found for key" in str(exc_info.value)
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# get non existing reg address
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with pytest.raises(Exception) as exc_info:
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d.getRegisterName(RegisterAddress(0x300))
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assert "No entry found for value" in str(exc_info.value)
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d.clearRegisterDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_reg(name="test_reg", addr=0x201)
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assert "Register Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.withdetectorsimulators
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def test_define_bit(simulator, request):
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""" Test setting define_bit for ctb and xilinx_ctb."""
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det_name = simulator
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from slsdet import RegisterAddress, BitAddress
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# setup
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d = Detector()
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d.hostname = f"localhost:{SERVER_START_PORTNO}"
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if det_name in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.define_reg(name="test_reg1", addr=addr1)
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d.define_reg(name="test_reg2", addr=addr2)
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# not using keyword arguments
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with pytest.raises(TypeError) as exc_info:
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d.define_bit("randombit", 0x203, 1)
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# invalid value type (bit=string)
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with pytest.raises(ValueError) as exc_info:
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position='1')
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# invalid bit_position
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position=32)
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assert "Bit position must be between 0 and 31" in str(exc_info.value)
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# defining with random reg value
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name='test_bit1', addr='random_reg', bit_position=1)
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assert "No entry found for key" in str(exc_info.value)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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# defining bit address with bit_position as well
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with pytest.raises(ValueError) as exc_info:
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d.define_bit(name='test_bit1', addr=bit1, bit_position=1)
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assert "bit_position must be None" in str(exc_info.value)
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d.define_bit(name="test_bit1", addr='test_reg2', bit_position=1)
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d.define_bit(name="test_bit1", addr='test_reg1', bit_position=1) # modify reg
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d.define_bit(name='test_bit1', addr=bit1) # modify pos
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d.define_bit(name="test_bit2", addr=0x201, bit_position=4) # int addr
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d.define_bit(name="test_bit3", addr=addr2, bit_position=3) # RegisterAddress addr
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assert(d.getBitAddress('test_bit1') == bit1)
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assert(d.getBitAddress('test_bit2') == bit2)
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assert(d.getBitAddress('test_bit3') == bit3)
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assert(d.getBitAddress('test_bit1').address() == addr1)
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assert(d.getBitAddress('test_bit1').bitPosition() == 2)
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assert(d.getBitAddress('test_bit2') == BitAddress(addr1, 4))
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assert(d.getBitName(bit1) == 'test_bit1')
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assert(d.getBitName(bit2) == 'test_bit2')
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assert(d.getBitName(bit3) == 'test_bit3')
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assert(d.getBitName(BitAddress(addr2,3)) == 'test_bit3')
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# bit doesnt exist for that reg
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with pytest.raises(Exception) as exc_info:
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d.getBitName(BitAddress(addr1, 5))
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assert "No entry found for value" in str(exc_info.value)
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# addr doesnt exist for that reg
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with pytest.raises(Exception) as exc_info:
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d.getBitName(BitAddress(RegisterAddress(0x300), 5))
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assert "No entry found for value" in str(exc_info.value)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.withdetectorsimulators
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def test_using_defined_reg_and_bit(simulator, request):
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""" Test using defined reg and bit define_bit for ctb and xilinx_ctb."""
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det_name = simulator
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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# setup
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d = Detector()
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d.hostname = f"localhost:{SERVER_START_PORTNO}"
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if det_name in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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d.setRegisterDefinition('test_reg1', addr1)
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d.setRegisterDefinition('test_reg2', addr2)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setBitDefinition('test_bit1', bit1)
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d.setBitDefinition('test_bit2', bit2)
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d.setBitDefinition('test_bit3', bit3)
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prev_val_addr1 = d.reg[addr1]
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prev_val_addr2 = d.reg[addr2]
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# reg name doesnt exist
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with pytest.raises(Exception) as exc_info:
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d.reg['random_reg']
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.setBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.clearBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.getBit('random_reg')
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assert "No entry found for key" in str(exc_info.value)
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# bit name doesnt exist
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with pytest.raises(Exception) as exc_info:
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d.setBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.clearBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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with pytest.raises(Exception) as exc_info:
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d.getBit('test_bit1', bit_position=5)
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assert "bit_position must be None" in str(exc_info.value)
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d.reg['test_reg1'] = RegisterValue(0x0)
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assert(d.reg['test_reg1'].value() == 0x0)
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d.reg['test_reg1'] = RegisterValue(0x10)
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assert(d.reg['test_reg1'].value() == 0x10)
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d.setBit('test_bit1')
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assert(d.reg['test_reg1'].value() == 0x14) # 0x10 | (1 << 2)
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d.clearBit('test_bit1')
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assert(d.reg['test_reg1'].value() == 0x10)
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assert(d.getBit('test_bit1') == 0)
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# restore previous values
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d.reg[addr1] = prev_val_addr1
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d.reg[addr2] = prev_val_addr2
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.withdetectorsimulators
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def test_definelist_reg(simulator, request):
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""" Test using definelist_reg for ctb and xilinx_ctb."""
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det_name = simulator
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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# setup
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d = Detector()
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d.hostname = f"localhost:{SERVER_START_PORTNO}"
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if det_name in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setRegisterDefinitions({
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'test_reg1': RegisterAddress(0x201),
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'test_reg2': RegisterAddress(0x202)
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})
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res = d.getRegisterDefinitions()
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assert(res['test_reg1'] == addr1)
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assert(res['test_reg2'] == addr2)
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assert(len(res) == 2)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed")
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@pytest.mark.withdetectorsimulators
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def test_definelist_bit(simulator, request):
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""" Test using definelist_bit for ctb and xilinx_ctb."""
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det_name = simulator
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from slsdet import RegisterAddress, BitAddress, RegisterValue
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# setup
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d = Detector()
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d.hostname = f"localhost:{SERVER_START_PORTNO}"
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if det_name in ['ctb', 'xilinx_ctb']:
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prev_reg_defs = d.getRegisterDefinitions()
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prev_bit_defs = d.getBitDefinitions()
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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addr1 = RegisterAddress(0x201)
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addr2 = RegisterAddress(0x202)
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bit1 = BitAddress(addr1, 2)
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bit2 = BitAddress(addr1, 4)
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bit3 = BitAddress(addr2, 3)
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d.setRegisterDefinitions({
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'test_reg1': RegisterAddress(0x201),
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'test_reg2': RegisterAddress(0x202)
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})
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d.setBitDefinitions({
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'test_bit1': BitAddress(addr1, 2),
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'test_bit2': BitAddress(addr1, 4),
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'test_bit3': BitAddress(addr2, 3)
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})
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res = d.getBitDefinitions()
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assert(len(res) == 3)
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assert(res['test_bit1'] == bit1)
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assert(res['test_bit2'] == bit2)
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assert(res['test_bit3'] == bit3)
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assert(res['test_bit2'].address() == addr1)
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assert(res['test_bit2'].bitPosition() == 4)
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d.clearRegisterDefinitions()
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d.clearBitDefinitions()
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d.setRegisterDefinitions(prev_reg_defs)
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d.setBitDefinitions(prev_bit_defs)
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else:
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with pytest.raises(Exception) as exc_info:
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d.define_bit(name="test_bit", addr=0x300, bit_position=1)
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assert "Bit Definitions only for CTB" in str(exc_info.value)
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Log(LogLevel.INFOGREEN, f"✅ {request.node.name} passed") |