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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 15:00:02 +02:00
100 lines
3.7 KiB
C
Executable File
100 lines
3.7 KiB
C
Executable File
#pragma once
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#include "sls_detector_defs.h"
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#include "RegisterDefs.h"
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#define MIN_REQRD_VRSN_T_RD_API 0x181130
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#define REQRD_FRMWR_VRSN 0x190402
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#define CTRL_SRVR_INIT_TIME_US (1 * 1000 * 1000)
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/* Struct Definitions */
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typedef struct ip_header_struct {
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uint16_t ip_len;
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uint8_t ip_tos;
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uint8_t ip_ihl:4 ,ip_ver:4;
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uint16_t ip_offset:13,ip_flag:3;
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uint16_t ip_ident;
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uint16_t ip_chksum;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint32_t ip_sourceip;
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uint32_t ip_destip;
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} ip_header;
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/* Enums */
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enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
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enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D};
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enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
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D10, D11, D12, D13, D14, D15, D16, D17,
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D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
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/* Hardware Definitions */
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#define NCHAN (36)
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#define NCHAN_ANALOG (32)
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#define NCHAN_DIGITAL (64)
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#define NCHIP (1)
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#define NDAC (24)
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#define NPWR (6)
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#define NDAC_ONLY (NDAC - NPWR)
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define CLK_FREQ (156.25) /* MHz */
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#define I2C_POWER_VIO_DEVICE_ID (0x40)
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#define I2C_POWER_VA_DEVICE_ID (0x41)
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#define I2C_POWER_VB_DEVICE_ID (0x42)
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#define I2C_POWER_VC_DEVICE_ID (0x43)
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#define I2C_POWER_VD_DEVICE_ID (0x44)
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#define I2C_SHUNT_RESISTER_OHMS (0.005)
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/** Default Parameters */
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#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define DEFAULT_NUM_SAMPLES (1)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_EXPTIME (0)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_VLIMIT (-100)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_RUN_CLK (40)
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#define DEFAULT_ADC_CLK (20)
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#define DEFAULT_SYNC_CLK (20)
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#define DEFAULT_DBIT_CLK (200)
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#define HIGHVOLTAGE_MIN (60)
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#define HIGHVOLTAGE_MAX (200) // min dac val
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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#define VCHIP_MIN_MV (1673)
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#define VCHIP_MAX_MV (2668) // min dac val
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#define POWER_RGLTR_MIN (636)
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#define POWER_RGLTR_MAX (2638) // min dac val (not vchip-max) because of dac conversions
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#define VCHIP_POWER_INCRMNT (200)
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#define VIO_MIN_MV (1200) // for fpga to function
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/* Defines in the Firmware */
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#define MAX_PATTERN_LENGTH (0x7FFF)
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#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
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#define MAX_PHASE_SHIFTS_STEPS (8)
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#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
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#define WAIT_TIME_US_PLL (10 * 1000)
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#define WAIT_TIME_US_STP_ACQ (100)
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#define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
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#define WAIT_TIME_PATTERN_READ (10)
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#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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#define LSB_OF_64_BIT_REG_OFST (0)
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#define BIT_32_MSK (0xFFFFFFFF)
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#define IP_PACKETSIZE (0x2032)
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#define ADC_PORT_INVERT_VAL (0x453b2593)
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#define MAXIMUM_ADC_CLK (65)
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#define PLL_VCO_FREQ_MHZ (800)
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