mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-19 18:40:01 +02:00
Dhanya Thattil
c13049f144
* changed common.c readADCFromFile to make it more general and move temperature calculation for Eiger out of this function and inside whereever it is called. * g2 and m2: gethighvoltage was just a variable set in server, it is now moved to a get inside DAC5671 implementation (but not reading a measured value, instead what is set from a file), high voltage variable used inside DAC5671 for virtual servers * g2: switching off hv (ifrom non zero to zero value) will wait for 10s; powering on chip reconfigures chip; powering off chip unconfigures chip; powering off chip also includes check if hv = 0, if not throw exception; chip configuration checked before acquring; at start up: hv switched off and chip powered on, so does not wait 10s to switch off hv; * included test to check powering off chip when hv is on should throw an exception * g2: check if chip configured before acquiring * nios: read hv value set from file and virtual still goes into DAC5671 for conversions to and fro dac to V, change common readadc to readparameter to generalize, make sethighvoltage into a get and set to catch errors in get as well, g2: if not at startup, remmeber hv value before setting it and after check if value was being switched off (from a non zero value) and wait 10s if it was (10s wait only for switching off from non zero and not at startup)
234 lines
8.4 KiB
C
234 lines
8.4 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include "sls/sls_detector_defs.h"
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#define REQRD_FRMWRE_VRSN (0x221123)
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#define KERNEL_DATE_VRSN "Mon May 10 18:00:21 CEST 2021"
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#define ID_FILE "detid_gotthard2.txt"
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#define NUM_HARDWARE_VERSIONS (2)
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#define HARDWARE_VERSION_NUMBERS {0x0, 0x2};
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#define HARDWARE_VERSION_NAMES \
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{ "1.0", "1.2" }
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#define LINKED_SERVER_NAME "gotthard2DetectorServer"
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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/* Hardware Definitions */
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#define NCHAN (128)
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#define NCHIP (10)
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#define NDAC (16)
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#define NADC (32)
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#define ONCHIP_NDAC (7)
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#define DYNAMIC_RANGE (16)
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#define HV_SOFT_MAX_VOLTAGE (500)
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#define HV_HARD_MAX_VOLTAGE (530)
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#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
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#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
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#define ONCHIP_DAC_DRIVER_FILE_NAME ("/etc/devlinks/chipdac")
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#define TYPE_FILE_NAME ("/etc/devlinks/type")
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#ifdef VIRTUAL
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#define TEMPERATURE_FILE_NAME ("/tmp/temp.txt")
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#else
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#define TEMPERATURE_FILE_NAME ("/sys/class/hwmon/hwmon0/temp1_input")
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#endif
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#define CONFIG_FILE ("config_gotthard2.txt")
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2048)
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#define ONCHIP_DAC_MAX_VAL (0x3FF)
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#define ADU_MAX_VAL (0xFFF)
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#define ADU_MAX_BITS (12)
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#define MAX_FRAMES_IN_BURST_MODE (2720)
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#define TYPE_GOTTHARD2_MODULE_VAL (536)
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#define TYPE_GOTTHARD2_25UM_MASTER_HD1_V1_VAL (683)
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#define TYPE_GOTTHARD2_25UM_SLAVE_HDI_V1_VAL (704)
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#define TYPE_GOTTHARD2_25UM_MASTER_HD1_V2_VAL (723)
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#define TYPE_GOTTHARD2_25UM_SLAVE_HDI_V2_VAL (747)
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#define TYPE_GOTTHARD2_MODULE_VAL (536)
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#define TYPE_TOLERANCE (10)
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#define TYPE_NO_MODULE_STARTING_VAL (800)
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#define INITIAL_STARTUP_WAIT (1 * 1000 * 1000)
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#define WAIT_HIGH_VOLTAGE_SETTLE_TIME_S (10) // 10s
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/** Default Parameters */
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#define DEFAULT_BURST_MODE (BURST_INTERNAL)
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#define DEFAULT_FILTER_RESISTOR (0)
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#define DEFAILT_CDS_GAIN (0)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_NUM_BURSTS (1)
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#define DEFAULT_EXPTIME (0) // 0 ms (220ns in firmware)
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#define DEFAULT_PERIOD (0) // 0 ms
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#define DEFAULT_DELAY_AFTER_TRIGGER (0)
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#define DEFAULT_BURST_PERIOD (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_CURRENT_SOURCE (0)
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#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
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#define DEFAULT_ALGORITHM (ALG_HITS)
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#define DEFAULT_READOUT_C0 (8) //(108333336) // rdo_clk, 144 MHz
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#define DEFAULT_READOUT_C1 (8) //(108333336) // rdo_x2_clk, 144 MHz
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#define DEFAULT_SYSTEM_C0 (5) //(144444448) // run_clk, 144 MHz
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#define DEFAULT_SYSTEM_C1 (10) //(72222224) // chip_clk, 72 MHz
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#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
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#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
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#define DEFAULT_CNTNS_SYSTEM_C0 (10) // (72222224) run_clk, 72 MHz
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#define DEFAULT_CNTNS_SYSTEM_C1 (20) // (36111112) chip_clk, 36 MHz
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#define DEFAULT_CNTNS_SYSTEM_C2 (10) // (72222224) sync_clk, 72 MHz
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#define DEFAULT_BURST_SYSTEM_C0 (5) // (144444448) run_clk, 144 MHz
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#define DEFAULT_BURST_SYSTEM_C1 (10) // (72222224) chip_clk, 72 MHz
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#define DEFAULT_BURST_SYSTEM_C2 (5) // (144444448) sync_clk, 144 MHz
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#define DEFAULT_READOUT_SPEED (G2_108MHZ)
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#define SPEED_144_CLKDIV_0 (6)
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#define SPEED_144_CLKDIV_1 (6)
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#define SPEED_144_CLKPHASE_DEG_1 (122) // 125 not possible
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#define SPEED_144_DBIT_PIPELINE (1)
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#define SPEED_108_CLKDIV_0 (8)
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#define SPEED_108_CLKDIV_1 (8)
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#define SPEED_108_CLKPHASE_DEG_1 (268) // 270 not possible
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#define SPEED_108_DBIT_PIPELINE (1)
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/* Firmware Definitions */
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#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
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#define INT_SYSTEM_C0_FREQUENCY (144000000) // 144 MHz
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#define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (722222224) // 722 MHz
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#define DEFAULT_CLK1_PHASE_DEG (270)
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#define DEFAULT_DBIT_PIPELINE (1)
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#define DEFAULT_ASIC_DOUT_RDY_SRC (0x5)
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#define DEFAULT_ASIC_DOUT_RDY_DLY (0x3)
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#define GAIN_VAL_OFST (12)
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#define GAIN_VAL_MSK (0x3 << GAIN_VAL_OFST)
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#define VETO_DATA_SIZE (160)
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typedef struct {
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uint64_t frameNumber;
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uint64_t bunchId;
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} veto_header;
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/** Other Definitions */
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#define BIT16_MASK (0xFFFF)
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/* Enums */
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enum DACINDEX {
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G2_VREF_H_ADC, /* 0 */
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G2_DAC_UNUSED, /* 1 */
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G2_VB_COMP_FE, /* 2 */
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G2_VB_COMP_ADC, /* 3 */
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G2_VCOM_CDS, /* 4 */
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G2_VREF_RSTORE, /* 5 */
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G2_VB_OPA_1ST, /* 6 */
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G2_VREF_COMP_FE, /* 7 */
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G2_VCOM_ADC1, /* 8 */
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G2_VREF_PRECH, /* 9 */
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G2_VREF_L_ADC, /* 10 */
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G2_VREF_CDS, /* 11 */
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G2_VB_CS, /* 12 */
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G2_VB_OPA_FD, /* 13 */
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G2_DAC_UNUSED2, /* 14 */
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G2_VCOM_ADC2 /* 15*/
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};
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#define DAC_NAMES \
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"vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", \
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"vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", \
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"vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", \
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"dac_unused2", "vcom_adc2"
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enum ONCHIP_DACINDEX {
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G2_VCHIP_COMP_FE, /* 0 */
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G2_VCHIP_OPA_1ST, /* 1 */
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G2_VCHIP_OPA_FD, /* 2 */
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G2_VCHIP_COMP_ADC, /* 3 */
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G2_VCHIP_UNUSED, /* 4 */
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G2_VCHIP_REF_COMP_FE, /* 5 */
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G2_VCHIP_CS /* 6 */
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};
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#define ONCHIP_DAC_NAMES \
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"vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", \
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"vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
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enum CLKINDEX {
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READOUT_C0,
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READOUT_C1,
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SYSTEM_C0,
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SYSTEM_C1,
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SYSTEM_C2,
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SYSTEM_C3,
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NUM_CLOCKS
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};
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#define CLK_NAMES \
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"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", \
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"SYSTEM_C3"
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enum ADCINDEX { TEMP_FPGA };
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enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
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enum MASTERINDEX { MASTER_HARDWARE, OW_MASTER, OW_SLAVE };
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#define MASTER_NAMES "hardware (master/slave)", "master", "slave"
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/** Chip Definitions */
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#define ASIC_ADDR_MAX_BITS (4)
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#define ASIC_CURRENT_INJECT_ADDR (0x9)
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#define ASIC_VETO_REF_ADDR (0xA)
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#define ASIC_CONF_ADC_ADDR (0xB)
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#define ASIC_CONF_GLOBAL_SETT (0xC)
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#define ASIC_GAIN_MAX_BITS (2)
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#define ASIC_GAIN_MSK (0x3)
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#define ASIC_G0_VAL ((0x0 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
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#define ASIC_G1_VAL ((0x1 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
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#define ASIC_G2_VAL ((0x3 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
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#define ASIC_CONTINUOUS_MODE_MSK (0x7)
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#define ASIC_ADC_MAX_BITS (7)
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#define ASIC_ADC_MAX_VAL (0x7F)
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#define ASIC_GLOBAL_SETT_MAX_BITS (6)
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#define ASIC_EXT_MEMCTRL_OFST (0)
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#define ASIC_EXT_MEMCTRL_MSK (0x1 << ASIC_EXT_MEMCTRL_OFST)
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#define ASIC_EXT_TIMING_OFST (1)
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#define ASIC_EXT_TIMING_MSK (0x1 << ASIC_EXT_TIMING_OFST)
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#define ASIC_CONT_MODE_OFST (2)
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#define ASIC_CONT_MODE_MSK (0x1 << ASIC_CONT_MODE_OFST)
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#define ASIC_FILTER_OFST (3)
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#define ASIC_FILTER_MSK (0x3 << ASIC_FILTER_OFST)
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#define ASIC_FILTER_MAX_RES_VALUE (3)
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#define ASIC_CDS_GAIN_OFST (5)
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#define ASIC_CDS_GAIN_MSK (0x1 << ASIC_CDS_GAIN_OFST)
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl : 4, ip_ver : 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset : 13, ip_flags : 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define IP_HEADER_SIZE (20)
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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