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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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169 lines
6.5 KiB
C
169 lines
6.5 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include "sls/sls_detector_defs.h"
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#define REQRD_FRMWRE_VRSN (0x210910)
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#define KERNEL_DATE_VRSN "Mon May 10 18:00:21 CEST 2021"
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#define ID_FILE "detid_mythen3.txt"
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#define LINKED_SERVER_NAME "mythen3DetectorServer"
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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/* Hardware Definitions */
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#define NCOUNTERS (3)
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#define MAX_COUNTER_MSK (0x7)
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#define NCHAN_1_COUNTER (128)
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#define NCHAN (128 * NCOUNTERS)
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#define NCHIP (10)
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#define NDAC (16)
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#define HV_SOFT_MAX_VOLTAGE (500)
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#define HV_HARD_MAX_VOLTAGE (530)
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#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
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#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
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#define TYPE_FILE_NAME ("/etc/devlinks/type")
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#define DAC_MAX_MV (2048)
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#define TYPE_MYTHEN3_MODULE_VAL (93)
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#define TYPE_TOLERANCE (5)
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#define TYPE_NO_MODULE_STARTING_VAL (800)
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#define MAX_EXT_SIGNALS (8)
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/** Default Parameters */
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#define DEFAULT_PATTERN_FILE ("DefaultPattern_mythen3.txt")
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#define DEFAULT_INTERNAL_GATES (1)
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#define DEFAULT_EXTERNAL_GATES (1)
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#define DEFAULT_DYNAMIC_RANGE (32)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_GATE_WIDTH (100 * 1000 * 1000) // ns
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#define DEFAULT_GATE_DELAY (0)
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#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
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#define DEFAULT_DELAY_AFTER_TRIGGER (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_SETTINGS (STANDARD)
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#define DEFAULT_TRIMBIT_VALUE (0)
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#define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
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#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
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#define DEFAULT_READOUT_C1 (10) //(100000000) // smp sample clk (x2), 100 MHz
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#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
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#define DEFAULT_SYSTEM_C1 (10) //(100000000) // sync_clk, 100 MHz
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#define DEFAULT_SYSTEM_C2 (10) //(100000000) // str_clk, 100 MHz
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#define DEFAULT_SYSTEM_C3 (5) //(200000000) // smp_clk, 200 MHz
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// (DEFAULT_SYSTEM_C3 only for timing receiver) should not be changed
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#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
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#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
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#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
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#define DEFAULT_ADIF_PIPELINE_VAL (8)
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#define DEFAULT_ADIF_ADD_OFST_VAL (0)
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/* Firmware Definitions */
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#define MAX_TIMESLOT_VAL (0xFFFFFF)
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#define IP_HEADER_SIZE (20)
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#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
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#define READOUT_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (1000000000) // 1GHz
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#define MAX_NUM_DESERIALIZERS (40)
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/** Other Definitions */
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#define BIT16_MASK (0xFFFF)
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#define MAX_TRIMBITS_VALUE (63)
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/* Enums */
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enum DACINDEX {
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M_VCASSH,
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M_VTH2,
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M_VRSHAPER,
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M_VRSHAPER_N,
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M_VIPRE_OUT,
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M_VTH3,
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M_VTH1,
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M_VICIN,
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M_VCAS,
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M_VRPREAMP,
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M_VCAL_N,
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M_VIPRE,
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M_VISHAPER,
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M_VCAL_P,
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M_VTRIM,
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M_VDCSH,
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M_VTHRESHOLD
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};
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#define DAC_NAMES \
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"vcassh", "vth2", "vrshaper", "vrshaper_n", "vipre_out", "vth3", "vth1", \
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"vicin", "vcas", "vrpreamp", "vcal_n", "vipre", "vishaper", "vcal_p", \
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"vtrim", "vdcsh", "vthreshold"
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#define DEFAULT_DAC_VALS \
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{ \
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1200, /* casSh */ \
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2800, /* Vth2 */ \
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1280, /* Vrshaper */ \
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2800, /* Vrshaper_n */ \
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1220, /* vIpreOut */ \
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2800, /* Vth3 */ \
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2800, /* Vth1 */ \
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1708, /* vIcin */ \
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1800, /* cas */ \
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1100, /* Vrpreamp */ \
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1100, /* Vcal_n */ \
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2624, /* vIpre */ \
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1708, /* vishaper */ \
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1712, /* Vcal_p */ \
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2800, /* vTrim */ \
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800 /* VdcSh */ \
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};
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#define NUMSETTINGS (3)
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#define NSPECIALDACS (2)
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#define SPECIALDACINDEX {M_VRPREAMP, M_VRSHAPER};
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#define SPECIAL_DEFAULT_STANDARD_DAC_VALS \
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{ 1100, 1280 }
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#define SPECIAL_DEFAULT_FAST_DAC_VALS \
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{ 300, 1500 }
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#define SPECIAL_DEFAULT_HIGHGAIN_DAC_VALS \
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{ 1300, 1100 }
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enum CLKINDEX {
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READOUT_C0,
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READOUT_C1,
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SYSTEM_C0,
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SYSTEM_C1,
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SYSTEM_C2,
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SYSTEM_C3,
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NUM_CLOCKS
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};
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#define CLK_NAMES \
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"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", \
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"SYSTEM_C3"
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enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl : 4, ip_ver : 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset : 13, ip_flags : 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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#define PACKETS_PER_FRAME_10G (2)
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#define PACKETS_PER_FRAME_1G (20)
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