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* voltage regulators only looks at dac and not at ctrl_reg * xilinx: change dac max to 2048, setting dac ist not inverse conversion from dac to voltage anymore, but setting power is inverse, also there is max and min to power, a different min for vio and this is checked at funcs interface, not printign or converting to mv in dac for power regulators (as its conversion max and min are different) * Use links for dacs/adc and adapt power rglt thresholds * Remove wait for transceiver reset * adc and dac device not used anymore and hence removed * udp restucturing: arm has to be multiple of 16 and no byteswap in udp_gen, option to compile locally in arm architecture, memsize of the second udp memory has to be limited --------- Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>
12 lines
322 B
C
12 lines
322 B
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include <sys/types.h>
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int resetFPGA(char *mess);
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int loadDeviceTree(char *mess);
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int checksBeforeCreatingDeviceTree(char *mess);
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int createDeviceTree(char *mess);
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int verifyDeviceTree(char *mess); |