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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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168 lines
6.7 KiB
C
168 lines
6.7 KiB
C
/*
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* mythen3Server_defs.h
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*
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* Created on: Jan 24, 2013
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* Author: l_maliakal_d, changed my Marie A.
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*/
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#ifndef SLSDETECTORSERVER_DEFS_H_
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#define SLSDETECTORSERVER_DEFS_H_
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#include "sls_detector_defs.h"
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#include <stdint.h>
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/** This is only an example file!!! */
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#define GOODBYE (-200)
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enum DACINDEX {vIpre, vIbias, Vrf, VrfSh, vIinSh, VdcSh, Vth2, VPL, Vth1, Vth3, Vtrim, casSh, cas, vIbiasSh, vIcin, VPH, NC, vIpreOut, V_D, V_CHIP, V_C, V_B, V_A, V_IO, V_LIM}; // Mythen 3.01
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enum PWRINDEX {PWR_IO, PWR_A, PWR_B, PWR_C, PWR_D, PWR_CHIP=-1, PWR_LIMIT=-1};
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enum CLKINDEX {RUN_CLK_C, ADC_CLK_C, SYNC_CLK_C, DBIT_CLK_C};
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#define DEFAULT_DAC_VALS { 2150, /* vIpre */ \
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1200, /* vIbias */ \
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900, /* Vrf */ \
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1050, /* VrfSh */ \
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1400, /* vIinSh */ \
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655, /* VdcSh */ \
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850, /* Vth2 */ \
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1400, /* VPL */ \
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850, /* Vth1 */ \
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850, /* Vth3 */ \
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2294, /* Vtrim */ \
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983, /* casSh */ \
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1474, /* cas */ \
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1200, /* vIbiasSh */ \
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1600, /* vIcin */ \
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1520, /* VPH */ \
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0, /* NC */ \
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1000 /* vIpreOut */ \
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0 /* V_D */ \
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0 /* V_CHIP */ \
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0 /* V_C */ \
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1335 /* V_B */ \
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1335 /* V_A */ \
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1350 /* V_IO */ \
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};
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#define DEFAULT_DAC_NAMES { "vIpre", \
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"vIbias", \
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"Vrf", \
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"VrfSh", \
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"vIinSh", \
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"VdcSh", \
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"Vth2", \
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"VPL", \
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"Vth1", \
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"Vth3", \
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"Vtrim", \
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"casSh", \
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"cas", \
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"vIbiasSh", \
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"vIcin", \
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"VPH", \
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"NC", \
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"vIpreOut" \
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"v_d" \
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"v_chip" \
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"v_c" \
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"v_b" \
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"v_a" \
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"v_io" \
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};
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/*Hardware Definitions */
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#define NMAXMOD (1)
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#define NMOD (1)
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#define NCHAN (32)
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#define NCHIP (1)
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#define NADC (0)
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#define NDAC (24)
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#define NDAC_PER_SET (8)
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#define NPWR (5)
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#define MAX_DACVOLTVAL (2500) //mV
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#define MAX_DACVAL (4096) // dac val
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#define MAX_VCHIPVAL (2700) //mV /** name ???? */
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#define MIN_VCHIP_OFSTVAL (200) //mV /** name ???? */
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#define MIN_VCHIP_VAL (600) //mV /** name ???? */
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (200*1000) //ns
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#define DEFAULT_PERIOD (1*1000*1000) //ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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/* Defines in the Firmware */
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#define FIX_PATT_VAL (0xACDC1980)
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/* LTC2620 DAC DEFINES */
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#define LTC2620_DAC_CMD_OFST (20)
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#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_ADDR_OFST (16)
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#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
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#define LTC2620_DAC_DATA_OFST (4)
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#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
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#define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST)
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#define LTC2620_DAC_NUMBITS (24)
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/** PLL Reconfiguration Registers */
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//https://www.altera.com/documentation/mcn1424769382940.html
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#define PLL_MODE_REG (0x00)
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#define PLL_STATUS_REG (0x01)
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#define PLL_START_REG (0x02)
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#define PLL_N_COUNTER_REG (0x03)
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#define PLL_M_COUNTER_REG (0x04)
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#define PLL_C_COUNTER_REG (0x05)
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#define PLL_PHASE_SHIFT_REG (0x06)
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#define PLL_SHIFT_NUM_SHIFTS_OFST (0)
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#define PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << PLL_SHIFT_NUM_SHIFTS_OFST)
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#define PLL_SHIFT_CNT_SELECT_OFST (16)
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#define PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << PLL_SHIFT_CNT_SELECT_OFST)
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#define PLL_SHIFT_CNT_SLCT_C0_VAL ((0x0 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C1_VAL ((0x1 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C2_VAL ((0x2 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C3_VAL ((0x3 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C4_VAL ((0x4 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C5_VAL ((0x5 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C6_VAL ((0x6 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C7_VAL ((0x7 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C8_VAL ((0x8 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C9_VAL ((0x9 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C10_VAL ((0x10 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C11_VAL ((0x11 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C12_VAL ((0x12 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C13_VAL ((0x13 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C14_VAL ((0x14 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C15_VAL ((0x15 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C16_VAL ((0x16 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_CNT_SLCT_C17_VAL ((0x17 << PLL_SHIFT_CNT_SELECT_OFST) & PLL_SHIFT_CNT_SELECT_MSK)
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#define PLL_SHIFT_UP_DOWN_OFST (21)
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#define PLL_SHIFT_UP_DOWN_MSK (0x00000001 << PLL_SHIFT_UP_DOWN_OFST)
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#define PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
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#define PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << PLL_SHIFT_UP_DOWN_OFST) & PLL_SHIFT_UP_DOWN_MSK)
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#define PLL_K_COUNTER_REG (0x07)
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#define PLL_BANDWIDTH_REG (0x08)
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#define PLL_CHARGEPUMP_REG (0x09)
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#define PLL_VCO_DIV_REG (0x1c)
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#define PLL_MIF_REG (0x1f)
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#define PLL_VCO_FREQ_MHZ 400
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#endif /* SLSDETECTORSERVER_DEFS_H_ */
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