mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-02-08 03:58:40 +01:00
e7a91d38f2
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#include "arm64.h"
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#include "RegisterDefs.h"
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#include "clogger.h"
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#include "common.h"
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#include "sls/ansi.h"
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#include "sls/sls_detector_defs.h"
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#include <fcntl.h> // open
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#include <sys/mman.h> // mmap
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/* global variables */
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#define CSP0 (0xB0080000)
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#define CSP1 (0xB0050000) // udp
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#define CSP2 (0xA0000000)
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#define MEM_SIZE_CSP0 (0x20000)
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#define MEM_SIZE_CSP1 (0x2000) // smaller size for udp
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#define MEM_SIZE_CSP2 (0x4000)
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u_int32_t *csp0base = 0;
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u_int32_t *csp1base = 0;
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u_int32_t *csp2base = 0;
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void bus_w(u_int32_t offset, u_int32_t data) {
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volatile u_int32_t *ptr1;
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ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
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*ptr1 = data;
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}
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u_int32_t bus_r(u_int32_t offset) {
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volatile u_int32_t *ptr1;
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ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
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return *ptr1;
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}
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void bus_w_csp2(u_int32_t offset, u_int32_t data) {
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volatile u_int32_t *ptr1;
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ptr1 = (u_int32_t *)(csp2base + offset / (sizeof(u_int32_t)));
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*ptr1 = data;
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}
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u_int32_t bus_r_csp2(u_int32_t offset) {
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volatile u_int32_t *ptr1;
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ptr1 = (u_int32_t *)(csp2base + offset / (sizeof(u_int32_t)));
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return *ptr1;
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}
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uint64_t getU64BitReg(int aLSB, int aMSB) {
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uint64_t retval = bus_r(aMSB);
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retval = (retval << 32) | bus_r(aLSB);
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return retval;
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}
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void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
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bus_w(aLSB, value & (0xffffffff));
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bus_w(aMSB, (value >> 32) & (0xffffffff));
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}
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u_int32_t readRegister(u_int32_t offset) { return bus_r(offset); }
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u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
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bus_w(offset, data);
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return readRegister(offset);
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}
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int mapCSP0(void) {
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LOG(logINFO, ("Mapping memory\n"));
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u_int32_t csps[3] = {CSP0, CSP1, CSP2};
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u_int32_t **cspbases[3] = {&csp0base, &csp1base, &csp2base};
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u_int32_t memsize[3] = {MEM_SIZE_CSP0, MEM_SIZE_CSP1, MEM_SIZE_CSP2};
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char names[3][10] = {"csp0base", "csp1base", "csp2base"};
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for (int i = 0; i < 3; ++i) {
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// if not mapped
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if (*cspbases[i] == 0) {
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LOG(logINFO, ("\tMapping memory for %s\n", names[i]));
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#ifdef VIRTUAL
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*cspbases[i] = malloc(memsize[i]);
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if (*cspbases[i] == NULL) {
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LOG(logERROR,
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("Could not allocate virtual memory of size %d for %s.\n",
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memsize[i], names[i]));
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return FAIL;
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}
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LOG(logINFO, ("\tmemory allocated for %s\n", names[i]));
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#else
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int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
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if (fd == -1) {
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LOG(logERROR, ("Can't find /dev/mem for %s\n", names[i]));
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return FAIL;
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}
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LOG(logDEBUG1,
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("\t/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
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*cspbases[i] =
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(u_int32_t *)mmap(0, memsize[i], PROT_READ | PROT_WRITE,
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MAP_FILE | MAP_SHARED, fd, csps[i]);
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if (*cspbases[i] == MAP_FAILED) {
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LOG(logERROR, ("Can't map memmory area for %s\n", names[i]));
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return FAIL;
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}
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#endif
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LOG(logINFO,
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("\t%s mapped of size %d from %p to %p,(CSP:0x%x) \n", names[i],
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memsize[i], *cspbases[i], *cspbases[i] + memsize[i], csps[i]));
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// LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
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} else
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LOG(logINFO, ("\tMemory %s already mapped before\n", names[i]));
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}
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return OK;
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}
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u_int32_t *Arm_getUDPBaseAddress() { return csp1base; }
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