Dhanya Thattil ce7f01bdc4
Dev: m3 clkdiv0 20 (#924)
* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max
2024-07-25 17:18:45 +02:00

15 lines
580 B
C

// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
/** API versions */
#define RELEASE "developer"
#define APILIB "developer 0x230224"
#define APIRECEIVER "developer 0x230224"
#define APICTB "developer 0x240207"
#define APIGOTTHARD "developer 0x240207"
#define APIGOTTHARD2 "developer 0x240207"
#define APIJUNGFRAU "developer 0x240207"
#define APIXILINXCTB "developer 0x240207"
#define APIEIGER "developer 0x240207"
#define APIMOENCH "developer 0x240703"
#define APIMYTHEN3 "developer 0x240715"