mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 06:50:02 +02:00
29141ac1a6
* set starting frame number of next acquisition for both jungfrau and eiger. firmware has not implemented a get, so workaround. tests included. frame number 0 not allowed due to Eiger. Eiger max frame is 48 bit, while jungfrau is 64 bit * made argument of setstartingframenumber const
91 lines
3.4 KiB
C
Executable File
91 lines
3.4 KiB
C
Executable File
#pragma once
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#include "sls_detector_defs.h"
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#define REQUIRED_FIRMWARE_VERSION (22)
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#define IDFILECOMMAND "more /home/root/executables/detid.txt"
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#define STATUS_IDLE 0
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#define STATUS_RUNNING 1
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#define STATUS_ERROR 2
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/* Enums */
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enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
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enum DACINDEX {SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
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#define DEFAULT_DAC_VALS { \
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0, /* SvP */ \
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2480, /* Vtr */ \
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3300, /* Vrf */ \
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1400, /* Vrs */ \
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4000, /* SvN */ \
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2556, /* Vtgstv */ \
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1000, /* Vcmp_ll */ \
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1000, /* Vcmp_lr */ \
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4000, /* cal */ \
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1000, /* Vcmp_rl */ \
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1100, /* rxb_rb */ \
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1100, /* rxb_lb */ \
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1000, /* Vcmp_rr */ \
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1000, /* Vcp */ \
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2000, /* Vcn */ \
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1550 /* Vis */ \
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};
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enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
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enum NETWORKINDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
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enum {E_PARALLEL, E_NON_PARALLEL, E_SAFE};
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/* Hardware Definitions */
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#define NCHAN (256 * 256)
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#define NCHIP (4)
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#define NDAC (16)
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#define TEN_GIGA_BUFFER_SIZE (4112)
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#define ONE_GIGA_BUFFER_SIZE (1040)
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#define TEN_GIGA_CONSTANT (4)
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#define ONE_GIGA_CONSTANT (16)
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#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
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#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
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#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
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#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
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#define DEFAULT_UDP_SOURCE_PORT (0xE185)
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_STARTING_FRAME_NUMBER (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (1E9) //ns
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#define DEFAULT_PERIOD (1E9) //ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_SUBFRAME_EXPOSURE (2621440) // 2.6ms
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#define DEFAULT_SUBFRAME_DEADTIME (0)
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#define DEFAULT_DYNAMIC_RANGE (16)
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#define DEFAULT_READOUT_MODE (NONPARALLEL)
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#define DEFAULT_READOUT_STOREINRAM_MODE (CONTINOUS_RO)
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#define DEFAULT_READOUT_OVERFLOW32_MODE (NOOVERFLOW)
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#define DEFAULT_CLK_SPEED (HALF_SPEED)
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#define DEFAULT_IO_DELAY (650)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_PHOTON_ENERGY (-1)
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#define DEFAULT_RATE_CORRECTION (0)
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#define DEFAULT_EXT_GATING_ENABLE (0)
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#define DEFAULT_EXT_GATING_POLARITY (1) //positive
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#define DEFAULT_TEST_MODE (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2048)
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#define LTC2620_MIN_VAL (0) // including LTC defines instead of LTC262.h (includes bit banging and blackfin read and write)
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#define LTC2620_MAX_VAL (4095) // 12 bits
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#define DAC_MAX_STEPS (4096)
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#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
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#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
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#define HIGH_VOLTAGE_TOLERANCE (5)
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