mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 15:00:02 +02:00
Dhanya Thattil
1873cc9310
* merge fix from 7.0.2: new jungfrau fw versions, incremented binary, hdf5 and json versions * moench: changed dac names and default values to old moench values * moench: remove interface clk polarity at start up * moench: default speed is half speed, default values for adc offset and adc phase for different speeds (only half speed confirmed), adc vref voltage to 2.0 like G1 * moench: connected adc pipeline to client * moench: receiver- default frames per file is 100k and discard partial frames as default * moench binary in * using tostring in gui for dacs * moved frame discard policy as a parameter to be configured with a default depending on detector * moench: 300 degrees for adc phase in full speed
149 lines
5.1 KiB
C
149 lines
5.1 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include "RegisterDefs.h"
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#include "sls/sls_detector_defs.h"
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#define REQRD_FRMWRE_VRSN_BOARD2 0x444445 // 1.0 pcb (version = 010)
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#define REQRD_FRMWRE_VRSN 0x230710 // 2.0 pcb (version = 011)
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#define NUM_HARDWARE_VERSIONS (2)
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#define HARDWARE_VERSION_NUMBERS \
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{ 0x2, 0x3 }
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#define HARDWARE_VERSION_NAMES \
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{ "1.0", "2.0" }
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#define ID_FILE ("detid_moench.txt")
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#define LINKED_SERVER_NAME "moenchDetectorServer"
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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/* Hardware Definitions */
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#define NCHAN (400 * 400)
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#define NCHIP (1)
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#define NDAC (8)
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define DATA_BYTES (NCHIP * NCHAN * NUM_BYTES_PER_PIXEL)
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#define CLK_RUN (40) // MHz
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#define ADC_CLK_INDEX (0)
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_STARTING_FRAME_NUMBER (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (10 * 1000) // ns
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#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_SETTINGS (G4_HIGHGAIN)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_TMP_THRSHLD (65 * 1000) // milli degree Celsius
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#define DEFAULT_FLIP_ROWS (0)
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#define DEFAULT_SPEED (HALF_SPEED)
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#define DEFAULT_PARALLEL_ENABLE (0)
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#define HIGHVOLTAGE_MIN (60)
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#define HIGHVOLTAGE_MAX (200)
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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#define MAX_FILTER_CELL_VAL (12)
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#define READ_N_ROWS_MULTIPLE (16) // 400 rows/50packets * 2 interfaces
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#define MIN_ROWS_PER_READOUT (16)
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#define MAX_ROWS_PER_READOUT (400)
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#define ROWS_PER_PACKET (8)
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/* Defines in the Firmware */
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#define MAX_TIMESLOT_VAL (0x1F)
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#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
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#define ACQ_TIME_MIN_CLOCK (2)
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#define ASIC_FILTER_MAX_RES_VALUE (1)
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#define MAX_SELECT_CHIP10_VAL (63)
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#define MAX_PHASE_SHIFTS (240)
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#define BIT16_MASK (0xFFFF)
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#define ADC_DECMT_QUARTER_SPEED (0x3)
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#define ADC_DECMT_HALF_SPEED (0x1)
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#define ADC_DECMT_FULL_SPEED (0x0)
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#define ADC_PHASE_DEG_QUARTER_SPEED (0)
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#define ADC_PHASE_DEG_HALF_SPEED (0)
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#define ADC_PHASE_DEG_FULL_SPEED (300)
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#define ADC_OFST_QUARTER_SPEED (0x12)
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#define ADC_OFST_HALF_SPEED (0x12)
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#define ADC_OFST_FULL_SPEED (0x12)
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// pipeline
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#define ADC_PORT_INVERT_VAL (0x55555555)
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#define SAMPLE_ADC_FULL_SPEED \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL) // 0x0
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl : 4, ip_ver : 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset : 13, ip_flags : 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define IP_HEADER_SIZE (20)
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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/* Enums */
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enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
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enum DACINDEX {
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MO_VBP_COLBUF,
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MO_VIPRE,
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MO_VIN_CM,
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MO_VB_SDA,
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MO_VCASC_SFP,
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MO_VOUT_CM,
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MO_VIPRE_CDS,
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MO_IBIAS_SFP
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};
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#define DAC_NAMES \
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"vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", \
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"vipre_cds", "ibias_sfp"
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#define DEFAULT_DAC_VALS \
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{ \
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1300, /* MO_VBP_COLBUF */ \
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1000, /* MO_VIPRE */ \
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1400, /* MO_VIN_CM */ \
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680, /* MO_VB_SDA */ \
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1428, /* MO_VCASC_SFP */ \
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1200, /* MO_VOUT_CM */ \
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800, /* MO_VIPRE_CDS */ \
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900 /* MO_IBIAS_SFP */ \
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};
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enum MASTERINDEX { MASTER_HARDWARE, OW_MASTER, OW_SLAVE };
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#define MASTER_NAMES "hardware", "master", "slave"
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#define NUMSETTINGS (0)
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enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
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enum CLKINDEX { RUN_CLK, ADC_CLK, NUM_CLOCKS };
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#define CLK_NAMES "run", "adc", "dbit"
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