mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-05-17 01:40:42 +02:00
Dhanya Thattil
3d21bb64c4
* period and exptime(patternwaittime level 0) * added new regsieterdefs and updated api version and fixedpattern reg * autogenerate commands * formatting * minor * wip resetflow, readout mode, transceiver mask, transceiver enable * acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw * programming fpga and device tree done * most configuration done, need to connect configuretransceiver to client * stuck at resetting transciever timed out * minor * fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber * configuretransceiver from client, added help in client * make formatt and command generation * tests for xilinx ctb works * command generation * dacs added and tested, power not done * power added * added temp_fpga * binaries in * ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed * start works * virtual server sends * receiver works * tests * python function and enum generation, commands generatorn and autocomplete, formatting, tests * tests fail at start(transceiver not aligned) * tests passed * all binaries compiled * eiger binary in * added --nomodule cehck for xilinx
95 lines
3.0 KiB
C
95 lines
3.0 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#include "arm64.h"
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#include "RegisterDefs.h"
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#include "clogger.h"
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#include "common.h"
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#include "sls/ansi.h"
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#include "sls/sls_detector_defs.h"
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#include <fcntl.h> // open
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#include <sys/mman.h> // mmap
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/* global variables */
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#define CSP0 (0xB0080000)
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#define CSP1 (0xB0050000) // udp
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#define MEM_SIZE (0x10000)
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//#define MEM_SIZE_CSP0 (4096)
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//#define MEM_SIZE_CSP1 (2 * 4096)
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u_int32_t *csp0base = 0;
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u_int32_t *csp1base = 0;
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void bus_w(u_int32_t offset, u_int32_t data) {
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volatile u_int32_t *ptr1;
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ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
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*ptr1 = data;
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}
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u_int32_t bus_r(u_int32_t offset) {
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volatile u_int32_t *ptr1;
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ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
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return *ptr1;
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}
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uint64_t getU64BitReg(int aLSB, int aMSB) {
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uint64_t retval = bus_r(aMSB);
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retval = (retval << 32) | bus_r(aLSB);
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return retval;
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}
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void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
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bus_w(aLSB, value & (0xffffffff));
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bus_w(aMSB, (value >> 32) & (0xffffffff));
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}
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u_int32_t readRegister(u_int32_t offset) { return bus_r(offset); }
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u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
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bus_w(offset, data);
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return readRegister(offset);
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}
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int mapCSP0(void) {
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u_int32_t csps[2] = {CSP0, CSP1};
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u_int32_t **cspbases[2] = {&csp0base, &csp1base};
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char names[2][10] = {"csp0base", "csp1base"};
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for (int i = 0; i < 2; ++i) {
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// if not mapped
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if (*cspbases[i] == 0) {
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LOG(logINFO, ("Mapping memory for %s\n", names[i]));
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#ifdef VIRTUAL
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*cspbases[i] = malloc(MEM_SIZE);
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if (*cspbases[i] == NULL) {
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LOG(logERROR,
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("Could not allocate virtual memory for %s.\n", names[i]));
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return FAIL;
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}
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LOG(logINFO, ("memory allocated for %s\n", names[i]));
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#else
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int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
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if (fd == -1) {
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LOG(logERROR, ("Can't find /dev/mem for %s\n", names[i]));
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return FAIL;
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}
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LOG(logDEBUG1,
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("/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
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*cspbases[i] =
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(u_int32_t *)mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE,
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MAP_FILE | MAP_SHARED, fd, csps[i]);
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if (*cspbases[i] == MAP_FAILED) {
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LOG(logERROR, ("Can't map memmory area for %s\n", names[i]));
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return FAIL;
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}
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#endif
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LOG(logINFO, ("%s mapped from %p to %p,(CSP:0x%x) \n", names[i],
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*cspbases[i], *cspbases[i] + MEM_SIZE, csps[i]));
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// LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
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} else
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LOG(logINFO, ("Memory %s already mapped before\n", names[i]));
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}
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return OK;
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}
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u_int32_t *Arm_getUDPBaseAddress() { return csp1base; }
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