mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-27 08:40:02 +02:00
Dhanya Thattil
65b8c9c5c1
* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers * added parallel command * remove gain plot for moench * moench: updated adc invert val * moench: update adcoffset to 0xf and adcphase to 140 degrees * removed sync clock in moench * updated min fw version * removing config file in moench server
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include <inttypes.h>
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#if defined(JUNGFRAUD)
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/**
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* Set Defines
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* @param creg control register
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* @param preg parameter register
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* @param rprmsk reconfig parameter reset mask
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* @param wpmsk write parameter mask
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* @param prmsk pll reset mask
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* @param amsk address mask
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* @param aofst address offset
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* @param wd2msk write parameter mask for pll for dbit clock (Jungfrau only)
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* @param clk2Index clkIndex of second pll (Jungfrau only)
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*/
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void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
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uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
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int aofst, uint32_t wd2msk, int clk2Index);
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#else
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/**
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* Set Defines
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* @param creg control register
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* @param preg parameter register
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* @param rprmsk reconfig parameter reset mask
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* @param wpmsk write parameter mask
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* @param prmsk pll reset mask
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* @param amsk address mask
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* @param aofst address offset
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*/
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void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
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uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
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int aofst);
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#endif
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/**
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* Reset only PLL
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*/
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void ALTERA_PLL_ResetPLL();
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/**
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* Reset PLL Reconfiguration and PLL
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*/
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void ALTERA_PLL_ResetPLLAndReconfiguration();
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/**
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* Set PLL Reconfig register
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* @param reg register
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* @param val value
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* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use
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* second WR mask)
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*/
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void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
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int useSecondWRMask);
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/**
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* Write Phase Shift
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* @param phase phase shift
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* @param clkIndex clock index
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* @param pos 1 if up down direction of shift is positive, else 0
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*/
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void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos);
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/**
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* Set PLL mode register to polling mode
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*/
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void ALTERA_PLL_SetModePolling();
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/**
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* Calculate and write output frequency
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* @param clkIndex clock index
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* @param pllVCOFreqMhz PLL VCO Frequency in Mhz
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* @param value frequency to set to
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* @param frequency set
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*/
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int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value);
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