mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
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2f2fe4dd47
* Setting pattern from memory (#218) * ToString accepts c-style arrays * fixed patwait time bug in validation * Introduced pattern class * compile for servers too * Python binding for Pattern * added scanParameters in Python * slsReceiver: avoid potential memory leak around Implementation::generalData * additional constructors for scanPrameters in python * bugfix: avoid potentital memory leak in receiver if called outside constructor context * added scanParameters in Python * additional constructors for scanPrameters in python * M3defaultpattern (#227) * default pattern for m3 and moench including Python bindings * M3settings (#228) * some changes to compile on RH7 and in the server to load the default chip status register at startup * Updated mythen3DeectorServer_developer executable with correct initialization at startup Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com> Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch> * Pattern.h as a public header files (#229) * fixed buffer overflow but caused by using global instead of local enum * replacing out of range trimbits with edge values * replacing dac values that are out of range after interpolation * updated pybind11 to 2.6.2 * Mythen3 improved synchronization (#231) Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready startDetector first starts the slaves then the master acquire firs calls startDetector for the slaves then acquire on the master getMaster to read back from hardware which one is master * New server for JF to go with the new FW (#232) * Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218 * Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed. * fix for m3 scan with single module * m3 fw version * m3 server * bugfix for bottom when setting quad * new strategy for finding zmq based on cppzmq Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch> Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com> Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr> Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch> Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com> Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
34 lines
777 B
Plaintext
Executable File
34 lines
777 B
Plaintext
Executable File
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#onchip dacs chip index value (max 0x3ff)
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vchip_comp_fe -1 0x137
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vchip_opa_1st -1 0x000
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vchip_opa_fd -1 0x134
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vchip_comp_adc -1 0x3FF
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vchip_ref_comp_fe -1 0x180
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vchip_cs -1 0x0D0
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#dacs value (max 4096)
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vref_h_adc 2116
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vb_comp_fe 0
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vb_comp_adc 0
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vcom_cds 705
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vref_rstore 150
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vb_opa_1st 0
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vref_comp_fe 0
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vcom_adc1 705
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vref_prech 869
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vref_l_adc 700
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vref_cds 700
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vb_cs 2799
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vb_opa_fd 0
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vcom_adc2 704
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#configure adc chip index adc index value(max 0x7F)
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confadc -1 -1 0x22
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#vetoreference gain index value(max 4095)
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vetoref 1 0
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