mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-01-13 15:34:48 +01:00
717 lines
20 KiB
C
717 lines
20 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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// clang-format off
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#define REG_OFFSET (4)
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#define PATTERN_STEP0_MSB_REG (0x10004)
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#define PATTERN_STEP0_LSB_REG (0x10000)
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#ifndef __CHEBY__XCTB__H__
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#define __CHEBY__XCTB__H__
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#define XCTB_SIZE 49924 /* 0xc304 */
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/* REG CTRL_Reg */
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#define CTRL_REG 0x8000UL
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#define POWER_VIO 0x1UL
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#define POWER_VIO_MSK 0x1UL
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#define POWER_VIO_OFST 0
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#define POWER_VCC_A 0x2UL
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#define POWER_VCC_A_MSK 0x2UL
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#define POWER_VCC_A_OFST 1
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#define POWER_VCC_B 0x4UL
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#define POWER_VCC_B_MSK 0x4UL
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#define POWER_VCC_B_OFST 2
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#define POWER_VCC_C 0x8UL
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#define POWER_VCC_C_MSK 0x8UL
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#define POWER_VCC_C_OFST 3
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#define POWER_VCC_D 0x10UL
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#define POWER_VCC_D_MSK 0x10UL
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#define POWER_VCC_D_OFST 4
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/* REG Status_Reg */
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#define STATUS_REG 0x8004UL
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#define PATTERN_RUNNING 0x1UL
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#define PATTERN_RUNNING_MSK 0x1UL
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#define PATTERN_RUNNING_OFST 0
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#define RX_BUSY 0x2UL
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#define RX_BUSY_MSK 0x2UL
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#define RX_BUSY_OFST 1
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#define PROCESSING_BUSY 0x4UL
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#define PROCESSING_BUSY_MSK 0x4UL
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#define PROCESSING_BUSY_OFST 2
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#define UDP_GEN_BUSY 0x8UL
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#define UDP_GEN_BUSY_MSK 0x8UL
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#define UDP_GEN_BUSY_OFST 3
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#define NETWORK_BUSY 0x10UL
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#define NETWORK_BUSY_MSK 0x10UL
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#define NETWORK_BUSY_OFST 4
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#define WAIT_FOR_TRIGGER 0x20UL
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#define WAIT_FOR_TRIGGER_MSK 0x20UL
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#define WAIT_FOR_TRIGGER_OFST 5
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#define RX_NOT_GOOD 0x40UL
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#define RX_NOT_GOOD_MSK 0x40UL
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#define RX_NOT_GOOD_OFST 6
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/* REG Status_Reg2 */
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#define STATUS_REG2 0x8008UL
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#define STATUS_REG2_PRESET 0x0UL
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/* REG FPGAVersionReg */
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#define FPGAVERSIONREG 0x800cUL
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#define FPGACOMPDATE_MSK 0xffffffUL
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#define FPGACOMPDATE_OFST 0
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#define FPGADETTYPE_MSK 0xff000000UL
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#define FPGADETTYPE_OFST 24
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#define FPGADETTYPE_PRESET 0x8UL
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/* REG FPGA_GIT_HEAD */
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#define FPGA_GIT_HEAD 0x8010UL
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#define FPGA_GIT_HEAD_PRESET 0x0UL
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/* REG FixedPatternReg */
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#define FIXEDPATTERNREG 0x8014UL
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#define FIXEDPATTERNREG_PRESET 0xacdc2016UL
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/* REG ApiVersionReg */
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#define APIVERSIONREG 0x8018UL
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#define APICOMPDATE_MSK 0xffffffUL
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#define APICOMPDATE_OFST 0
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#define APIDETTYPE_MSK 0xff000000UL
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#define APIDETTYPE_OFST 24
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#define APIDETTYPE_PRESET 0x8UL
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/* REG datagen_ctrl */
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#define DATAGEN_CTRL 0xc300UL
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#define DATAGEN_MH1_ENABLE 0x1UL
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#define DATAGEN_MH1_ENABLE_MSK 0x1UL
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#define DATAGEN_MH1_ENABLE_OFST 0
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#define DATAGEN_MH1_RESETN 0x2UL
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#define DATAGEN_MH1_RESETN_MSK 0x2UL
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#define DATAGEN_MH1_RESETN_OFST 1
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/* REG FIFO_To_Gb_Control_Reg */
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#define FIFO_TO_GB_CONTROL_REG 0xa000UL
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#define ENABLED_CHANNELS_ADC_MSK 0xffUL
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#define ENABLED_CHANNELS_ADC_OFST 0
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#define ENABLED_CHANNELS_D 0x100UL
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#define ENABLED_CHANNELS_D_MSK 0x100UL
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#define ENABLED_CHANNELS_D_OFST 8
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#define ENABLED_CHANNELS_X_MSK 0x1e00UL
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#define ENABLED_CHANNELS_X_OFST 9
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#define RO_MODE_ADC 0x2000UL
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#define RO_MODE_ADC_MSK 0x2000UL
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#define RO_MODE_ADC_OFST 13
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#define RO_MODE_D 0x4000UL
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#define RO_MODE_D_MSK 0x4000UL
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#define RO_MODE_D_OFST 14
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#define RO_MODE_X 0x8000UL
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#define RO_MODE_X_MSK 0x8000UL
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#define RO_MODE_X_OFST 15
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#define COUNT_FRAMES_FROM_UPDATE 0x10000UL
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#define COUNT_FRAMES_FROM_UPDATE_MSK 0x10000UL
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#define COUNT_FRAMES_FROM_UPDATE_OFST 16
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#define START_STREAMING_P 0x20000UL
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#define START_STREAMING_P_MSK 0x20000UL
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#define START_STREAMING_P_OFST 17
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#define STREAM_BUFFER_CLEAR 0x40000UL
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#define STREAM_BUFFER_CLEAR_MSK 0x40000UL
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#define STREAM_BUFFER_CLEAR_OFST 18
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/* REG no_Samples_D_Reg */
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#define NO_SAMPLES_D_REG 0xa004UL
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#define NO_SAMPLES_D_MSK 0x3fffUL
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#define NO_SAMPLES_D_OFST 0
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/* REG no_Samples_A_Reg */
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#define NO_SAMPLES_A_REG 0xa008UL
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#define NO_SAMPLES_A_MSK 0x3fffUL
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#define NO_SAMPLES_A_OFST 0
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/* REG no_Samples_X_Reg */
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#define NO_SAMPLES_X_REG 0xa00cUL
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#define NO_SAMPLES_X_MSK 0x1fffUL
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#define NO_SAMPLES_X_OFST 0
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/* REG count_Frames_From_Reg_1 */
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#define COUNT_FRAMES_FROM_REG_1 0xa010UL
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#define COUNT_FRAMES_FROM_REG_1_PRESET 0x0UL
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/* REG count_Frames_From_Reg_2 */
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#define COUNT_FRAMES_FROM_REG_2 0xa014UL
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#define COUNT_FRAMES_FROM_REG_2_PRESET 0x0UL
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/* REG local_Frame_Number_Reg_1 */
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#define LOCAL_FRAME_NUMBER_REG_1 0xa018UL
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#define LOCAL_FRAME_NUMBER_REG_1_PRESET 0x0UL
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/* REG local_Frame_Number_Reg_2 */
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#define LOCAL_FRAME_NUMBER_REG_2 0xa01cUL
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#define LOCAL_FRAME_NUMBER_REG_2_PRESET 0x0UL
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/* REG TransceiverRXCTRL0Reg1 */
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#define TRANSCEIVERRXCTRL0REG1 0xc100UL
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#define TRANSCEIVERRXCTRL0REG1_PRESET 0x0UL
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/* REG TransceiverRXCTRL0Reg2 */
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#define TRANSCEIVERRXCTRL0REG2 0xc104UL
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#define TRANSCEIVERRXCTRL0REG2_PRESET 0x0UL
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/* REG TransceiverRXCTRL1Reg1 */
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#define TRANSCEIVERRXCTRL1REG1 0xc108UL
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#define TRANSCEIVERRXCTRL1REG1_PRESET 0x0UL
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/* REG TransceiverRXCTRL1Reg2 */
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#define TRANSCEIVERRXCTRL1REG2 0xc10cUL
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#define TRANSCEIVERRXCTRL1REG2_PRESET 0x0UL
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/* REG TransceiverRXCTRL2Reg */
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#define TRANSCEIVERRXCTRL2REG 0xc110UL
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#define TRANSCEIVERRXCTRL2REG_PRESET 0x0UL
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/* REG TransceiverRXCTRL3Reg */
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#define TRANSCEIVERRXCTRL3REG 0xc114UL
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#define TRANSCEIVERRXCTRL3REG_PRESET 0x0UL
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/* REG TransceiverSTATUS */
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#define TRANSCEIVERSTATUS 0xc118UL
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#define LINKDOWNLATCHEDOUT 0x1UL
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#define LINKDOWNLATCHEDOUT_MSK 0x1UL
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#define LINKDOWNLATCHEDOUT_OFST 0
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#define TXUSERCLKACTIVE 0x2UL
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#define TXUSERCLKACTIVE_MSK 0x2UL
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#define TXUSERCLKACTIVE_OFST 1
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#define RXUSERCLKACTIVE 0x4UL
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#define RXUSERCLKACTIVE_MSK 0x4UL
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#define RXUSERCLKACTIVE_OFST 2
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#define RXCOMMADET_MSK 0x78UL
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#define RXCOMMADET_OFST 3
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#define RXBYTEREALIGN_MSK 0x780UL
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#define RXBYTEREALIGN_OFST 7
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#define RXBYTEISALIGNED_MSK 0x7800UL
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#define RXBYTEISALIGNED_OFST 11
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#define GTWIZRXCDRSTABLE 0x8000UL
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#define GTWIZRXCDRSTABLE_MSK 0x8000UL
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#define GTWIZRXCDRSTABLE_OFST 15
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#define RESETTXDONE 0x10000UL
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#define RESETTXDONE_MSK 0x10000UL
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#define RESETTXDONE_OFST 16
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#define RESETRXDONE 0x20000UL
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#define RESETRXDONE_MSK 0x20000UL
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#define RESETRXDONE_OFST 17
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#define RXPMARESETDONE_MSK 0x3c0000UL
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#define RXPMARESETDONE_OFST 18
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#define TXPMARESETDONE_MSK 0x3c00000UL
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#define TXPMARESETDONE_OFST 22
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#define GTTPOWERGOOD_MSK 0x3c000000UL
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#define GTTPOWERGOOD_OFST 26
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/* REG TransceiverSTATUS2 */
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#define TRANSCEIVERSTATUS2 0xc11cUL
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#define RXLOCKED_MSK 0xfUL
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#define RXLOCKED_OFST 0
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/* REG TransceiverCONTROL */
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#define TRANSCEIVERCONTROL 0xc120UL
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#define GTWIZRESETALL 0x1UL
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#define GTWIZRESETALL_MSK 0x1UL
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#define GTWIZRESETALL_OFST 0
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#define RESETTXPLLANDDATAPATH 0x2UL
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#define RESETTXPLLANDDATAPATH_MSK 0x2UL
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#define RESETTXPLLANDDATAPATH_OFST 1
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#define RESETTXDATAPATHIN 0x4UL
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#define RESETTXDATAPATHIN_MSK 0x4UL
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#define RESETTXDATAPATHIN_OFST 2
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#define RESETRXPLLANDDATAPATH 0x8UL
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#define RESETRXPLLANDDATAPATH_MSK 0x8UL
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#define RESETRXPLLANDDATAPATH_OFST 3
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#define RESETRXDATAPATHIN 0x10UL
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#define RESETRXDATAPATHIN_MSK 0x10UL
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#define RESETRXDATAPATHIN_OFST 4
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#define RXPOLARITY_MSK 0x1e0UL
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#define RXPOLARITY_OFST 5
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#define RXERRORCNTRESET_MSK 0x1e00UL
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#define RXERRORCNTRESET_OFST 9
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#define RXMSBLSBINVERT_MSK 0x1e000UL
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#define RXMSBLSBINVERT_OFST 13
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#define RXWORDALIGNINVERT_MSK 0x1e0000UL
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#define RXWORDALIGNINVERT_OFST 17
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#define ENABLEDVALIDLOCK 0x200000UL
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#define ENABLEDVALIDLOCK_MSK 0x200000UL
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#define ENABLEDVALIDLOCK_OFST 21
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#define ENABLEMANUALWORDALIGN 0x400000UL
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#define ENABLEMANUALWORDALIGN_MSK 0x400000UL
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#define ENABLEMANUALWORDALIGN_OFST 22
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/* REG TransceiverErrCnt_Reg0 */
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#define TRANSCEIVERERRCNT_REG0 0xc124UL
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#define TRANSCEIVERERRCNT_REG0_PRESET 0x0UL
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/* REG TransceiverErrCnt_Reg1 */
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#define TRANSCEIVERERRCNT_REG1 0xc128UL
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#define TRANSCEIVERERRCNT_REG1_PRESET 0x0UL
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/* REG TransceiverErrCnt_Reg2 */
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#define TRANSCEIVERERRCNT_REG2 0xc12cUL
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#define TRANSCEIVERERRCNT_REG2_PRESET 0x0UL
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/* REG TransceiverErrCnt_Reg3 */
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#define TRANSCEIVERERRCNT_REG3 0xc130UL
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#define TRANSCEIVERERRCNT_REG3_PRESET 0x0UL
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/* REG TransceiverAlignCnt_Reg0 */
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#define TRANSCEIVERALIGNCNT_REG0 0xc134UL
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#define RXALIGNCNTCH0_MSK 0xffffUL
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#define RXALIGNCNTCH0_OFST 0
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/* REG TransceiverAlignCnt_Reg1 */
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#define TRANSCEIVERALIGNCNT_REG1 0xc138UL
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#define RXALIGNCNTCH1_MSK 0xffffUL
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#define RXALIGNCNTCH1_OFST 0
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/* REG TransceiverAlignCnt_Reg2 */
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#define TRANSCEIVERALIGNCNT_REG2 0xc13cUL
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#define RXALIGNCNTCH2_MSK 0xffffUL
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#define RXALIGNCNTCH2_OFST 0
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/* REG TransceiverAlignCnt_Reg3 */
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#define TRANSCEIVERALIGNCNT_REG3 0xc140UL
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#define RXALIGNCNTCH3_MSK 0xffffUL
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#define RXALIGNCNTCH3_OFST 0
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/* REG TransceiverLastWord_Reg0 */
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#define TRANSCEIVERLASTWORD_REG0 0xc144UL
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#define RXDATACH0_MSK 0xffffUL
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#define RXDATACH0_OFST 0
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/* REG TransceiverLastWord_Reg1 */
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#define TRANSCEIVERLASTWORD_REG1 0xc148UL
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#define RXDATACH1_MSK 0xffffUL
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#define RXDATACH1_OFST 0
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/* REG TransceiverLastWord_Reg2 */
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#define TRANSCEIVERLASTWORD_REG2 0xc14cUL
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#define RXDATACH2_MSK 0xffffUL
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#define RXDATACH2_OFST 0
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/* REG TransceiverLastWord_Reg3 */
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#define TRANSCEIVERLASTWORD_REG3 0xc150UL
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#define RXDATACH3_MSK 0xffffUL
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#define RXDATACH3_OFST 0
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/* REG PktPacketLengthReg */
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#define PKTPACKETLENGTHREG 0xa020UL
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#define PACKETLENGTH1G_MSK 0xffffUL
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#define PACKETLENGTH1G_OFST 0
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#define PACKETLENGTH10G_MSK 0xffff0000UL
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#define PACKETLENGTH10G_OFST 16
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/* REG PktNoPacketsReg */
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#define PKTNOPACKETSREG 0xa024UL
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#define NOPACKETS1G_MSK 0x3fUL
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#define NOPACKETS1G_OFST 0
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#define NOPACKETS10G_MSK 0x3f0000UL
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#define NOPACKETS10G_OFST 16
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/* REG PktCtrlReg */
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#define PKTCTRLREG 0xa028UL
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#define NOSERVERS_MSK 0x3fUL
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#define NOSERVERS_OFST 0
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#define SERVERSTART_MSK 0x1f00UL
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#define SERVERSTART_OFST 8
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#define ETHINTERF 0x10000UL
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#define ETHINTERF_MSK 0x10000UL
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#define ETHINTERF_OFST 16
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/* REG PktCoordReg1 */
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#define PKTCOORDREG1 0xa02cUL
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#define COORDX_MSK 0xffffUL
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#define COORDX_OFST 0
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#define COORDY_MSK 0xffff0000UL
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#define COORDY_OFST 16
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/* REG PktCoordReg2 */
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#define PKTCOORDREG2 0xa030UL
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#define COORDZ_MSK 0xffffUL
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#define COORDZ_OFST 0
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/* REG pattern_out_lsb_reg */
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#define PATTERN_OUT_LSB_REG 0xb000UL
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#define PATTERN_OUT_LSB_REG_PRESET 0x0UL
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/* REG pattern_out_msb_reg */
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#define PATTERN_OUT_MSB_REG 0xb004UL
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#define PATTERN_OUT_MSB_REG_PRESET 0x0UL
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/* REG pattern_in_lsb_reg */
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#define PATTERN_IN_LSB_REG 0xb008UL
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#define PATTERN_IN_LSB_REG_PRESET 0x0UL
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/* REG pattern_in_msb_reg */
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#define PATTERN_IN_MSB_REG 0xb00cUL
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#define PATTERN_IN_MSB_REG_PRESET 0x0UL
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/* REG pattern_mask_lsb_reg */
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#define PATTERN_MASK_LSB_REG 0xb010UL
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#define PATTERN_MASK_LSB_REG_PRESET 0x0UL
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/* REG pattern_mask_msb_reg */
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#define PATTERN_MASK_MSB_REG 0xb014UL
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#define PATTERN_MASK_MSB_REG_PRESET 0x0UL
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/* REG pattern_set_lsb_reg */
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#define PATTERN_SET_LSB_REG 0xb018UL
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#define PATTERN_SET_LSB_REG_PRESET 0x0UL
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/* REG pattern_set_msb_reg */
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#define PATTERN_SET_MSB_REG 0xb01cUL
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#define PATTERN_SET_MSB_REG_PRESET 0x0UL
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/* REG pattern_cntrl_reg */
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#define PATTERN_CNTRL_REG 0xb020UL
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#define PATTERN_CNTRL_WR 0x1UL
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#define PATTERN_CNTRL_WR_MSK 0x1UL
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#define PATTERN_CNTRL_WR_OFST 0
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#define PATTERN_CNTRL_RD 0x2UL
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#define PATTERN_CNTRL_RD_MSK 0x2UL
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#define PATTERN_CNTRL_RD_OFST 1
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#define PATTERN_CNTRL_ADDR_MSK 0x1fff0000UL
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#define PATTERN_CNTRL_ADDR_OFST 16
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/* REG pattern_limit_reg */
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#define PATTERN_LIMIT_REG 0xb024UL
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#define PATTERN_LIMIT_STRT_MSK 0x1fffUL
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#define PATTERN_LIMIT_STRT_OFST 0
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#define PATTERN_LIMIT_STP_MSK 0x1fff0000UL
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#define PATTERN_LIMIT_STP_OFST 16
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/* REG pattern_io_cntrl_lsb_reg */
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#define PATTERN_IO_CNTRL_LSB_REG 0xb028UL
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#define PATTERN_IO_CNTRL_LSB_REG_PRESET 0x0UL
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/* REG pattern_io_cntrl_msb_reg */
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#define PATTERN_IO_CNTRL_MSB_REG 0xb02cUL
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#define PATTERN_IO_CNTRL_MSB_REG_PRESET 0x0UL
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/* REG Flow_Control_Reg */
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#define FLOW_CONTROL_REG 0xb030UL
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#define START_F 0x1UL
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#define START_F_MSK 0x1UL
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#define START_F_OFST 0
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#define STOP_F 0x2UL
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#define STOP_F_MSK 0x2UL
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#define STOP_F_OFST 1
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#define RST_F 0x4UL
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#define RST_F_MSK 0x4UL
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#define RST_F_OFST 2
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#define SW_TRIGGER_F 0x8UL
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#define SW_TRIGGER_F_MSK 0x8UL
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#define SW_TRIGGER_F_OFST 3
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#define TRIGGER_ENABLE 0x10UL
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#define TRIGGER_ENABLE_MSK 0x10UL
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#define TRIGGER_ENABLE_OFST 4
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#define RSM_BUSY 0x20UL
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#define RSM_BUSY_MSK 0x20UL
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#define RSM_BUSY_OFST 5
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#define RSM_TRG_WAIT 0x40UL
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#define RSM_TRG_WAIT_MSK 0x40UL
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#define RSM_TRG_WAIT_OFST 6
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#define CSM_BUSY 0x80UL
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#define CSM_BUSY_MSK 0x80UL
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#define CSM_BUSY_OFST 7
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/* REG delay_In_Reg_1 */
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#define DELAY_IN_REG_1 0xb034UL
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#define DELAY_IN_REG_1_PRESET 0x0UL
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/* REG delay_In_Reg_2 */
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#define DELAY_IN_REG_2 0xb038UL
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#define DELAY_IN_REG_2_PRESET 0x0UL
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/* REG cycles_In_Reg_1 */
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#define CYCLES_IN_REG_1 0xb03cUL
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#define CYCLES_IN_REG_1_PRESET 0x0UL
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/* REG cycles_In_Reg_2 */
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#define CYCLES_IN_REG_2 0xb040UL
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#define CYCLES_IN_REG_2_PRESET 0x0UL
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/* REG frames_In_Reg_1 */
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#define FRAMES_IN_REG_1 0xb044UL
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#define FRAMES_IN_REG_1_PRESET 0x0UL
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/* REG frames_In_Reg_2 */
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#define FRAMES_IN_REG_2 0xb048UL
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#define FRAMES_IN_REG_2_PRESET 0x0UL
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/* REG period_In_Reg_1 */
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#define PERIOD_IN_REG_1 0xb04cUL
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#define PERIOD_IN_REG_1_PRESET 0x0UL
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/* REG period_In_Reg_2 */
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#define PERIOD_IN_REG_2 0xb050UL
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#define PERIOD_IN_REG_2_PRESET 0x0UL
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/* REG pattern_test_reg */
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#define PATTERN_TEST_REG 0xb054UL
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#define PATTERN_TEST_REG_PRESET 0x0UL
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/* REG pattern_firmware_reg */
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#define PATTERN_FIRMWARE_REG 0xb058UL
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#define PATTERN_WIDTH_MSK 0xffUL
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#define PATTERN_WIDTH_OFST 0
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#define PATTERN_ADDR_WIDTH_MSK 0xff00UL
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#define PATTERN_ADDR_WIDTH_OFST 8
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#define PATTERN_NLOOPS_NWAITS_MSK 0xff0000UL
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#define PATTERN_NLOOPS_NWAITS_OFST 16
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#define DIRECT_PATTERN_RAM 0x1000000UL
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#define DIRECT_PATTERN_RAM_MSK 0x1000000UL
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#define DIRECT_PATTERN_RAM_OFST 24
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/* REG time_From_Start_Out_Reg_1 */
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#define TIME_FROM_START_OUT_REG_1 0xb05cUL
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#define TIME_FROM_START_OUT_REG_1_PRESET 0x0UL
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/* REG time_From_Start_Out_Reg_2 */
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#define TIME_FROM_START_OUT_REG_2 0xb060UL
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#define TIME_FROM_START_OUT_REG_2_PRESET 0x0UL
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/* REG frames_From_Start_Out_Reg_1 */
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#define FRAMES_FROM_START_OUT_REG_1 0xb064UL
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#define FRAMES_FROM_START_OUT_REG_1_PRESET 0x0UL
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/* REG frames_From_Start_Out_Reg_2 */
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#define FRAMES_FROM_START_OUT_REG_2 0xb068UL
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#define FRAMES_FROM_START_OUT_REG_2_PRESET 0x0UL
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/* REG frame_Time_Out_Reg_1 */
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#define FRAME_TIME_OUT_REG_1 0xb06cUL
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#define FRAME_TIME_OUT_REG_1_PRESET 0x0UL
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/* REG frame_Time_Out_Reg_2 */
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#define FRAME_TIME_OUT_REG_2 0xb070UL
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#define FRAME_TIME_OUT_REG_2_PRESET 0x0UL
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/* REG pattern_loopdef_base */
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#define PATTERN_LOOPDEF_BASE 0xb080UL
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#define PATTERN_LOOP_ADDR_WORD 0x1UL
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#define PATTERN_LOOP_ADDR_WORD_MSK 0x1UL
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#define PATTERN_LOOP_ADDR_WORD_OFST 0
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#define PATTERN_LOOP_ITERATION_WORD 0x2UL
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#define PATTERN_LOOP_ITERATION_WORD_MSK 0x2UL
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#define PATTERN_LOOP_ITERATION_WORD_OFST 1
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#define PATTERN_WAIT_ADDR_WORD 0x4UL
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#define PATTERN_WAIT_ADDR_WORD_MSK 0x4UL
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#define PATTERN_WAIT_ADDR_WORD_OFST 2
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#define PATTERN_WAIT_TIMER_LSB_WORD 0x8UL
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#define PATTERN_WAIT_TIMER_LSB_WORD_MSK 0x8UL
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#define PATTERN_WAIT_TIMER_LSB_WORD_OFST 3
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#define PATTERN_WAIT_TIMER_MSB_WORD 0x10UL
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#define PATTERN_WAIT_TIMER_MSB_WORD_MSK 0x10UL
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#define PATTERN_WAIT_TIMER_MSB_WORD_OFST 4
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#define PATTERN_LOOPDEF_NWORDS 0x20UL
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#define PATTERN_LOOPDEF_NWORDS_MSK 0x20UL
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#define PATTERN_LOOPDEF_NWORDS_OFST 5
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/* REG pattern_loopdef_base_helper1 */
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#define PATTERN_LOOPDEF_BASE_HELPER1 0xb084UL
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#define PATTERN_WAIT_ADDR_MSK 0x1fffUL
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#define PATTERN_WAIT_ADDR_OFST 0
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/* REG pattern_loopdef_base_helper2 */
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#define PATTERN_LOOPDEF_BASE_HELPER2 0xb088UL
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#define PATTERN_LOOP_ADDR_STRT_MSK 0x1fffUL
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#define PATTERN_LOOP_ADDR_STRT_OFST 0
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#define PATTERN_LOOP_ADDR_STP_MSK 0x1fff0000UL
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#define PATTERN_LOOP_ADDR_STP_OFST 16
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/* REG pattern_bypass */
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#define PATTERN_BYPASS 0xc200UL
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#define PATTERN_BYPASS_PRESET 0x0UL
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/* REG pattern_bypass_enable */
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#define PATTERN_BYPASS_ENABLE 0xc204UL
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#define PATTERN_BYPASS_ENABLE_PRESET 0x0UL
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/* REG pattern_MOSI_bitselect */
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#define PATTERN_MOSI_BITSELECT 0xc208UL
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#define PATTERN_MOSI_BITSELECT_PRESET 0x0UL
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/* REG pattern_SCLK_bitselect */
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#define PATTERN_SCLK_BITSELECT 0xc20cUL
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#define PATTERN_SCLK_BITSELECT_PRESET 0x0UL
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/* REG pattern_SPI_writedata */
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#define PATTERN_SPI_WRITEDATA 0xc210UL
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#define PATTERN_SPI_WRITEDATA_PRESET 0x0UL
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/* REG pattern_mux_ctrl */
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#define PATTERN_MUX_CTRL 0xc214UL
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#define SPI_FULL 0x2UL
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#define SPI_FULL_MSK 0x2UL
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#define SPI_FULL_OFST 1
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#define MISO_FIFO_CLEAR 0x4UL
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#define MISO_FIFO_CLEAR_MSK 0x4UL
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#define MISO_FIFO_CLEAR_OFST 2
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#define MISO_FIFO_FULL 0x8UL
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#define MISO_FIFO_FULL_MSK 0x8UL
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#define MISO_FIFO_FULL_OFST 3
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#define MISO_FIFO_EMPTY 0x10UL
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#define MISO_FIFO_EMPTY_MSK 0x10UL
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#define MISO_FIFO_EMPTY_OFST 4
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#define ENABLE_CPU_SPI 0x20UL
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#define ENABLE_CPU_SPI_MSK 0x20UL
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#define ENABLE_CPU_SPI_OFST 5
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#define SPI_REVERSE_BITORDER 0x40UL
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#define SPI_REVERSE_BITORDER_MSK 0x40UL
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#define SPI_REVERSE_BITORDER_OFST 6
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/* REG MISO_data */
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#define MISO_DATA 0xc218UL
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#define MISO_DATA_PRESET 0x0UL
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/* REG pattern_CSN_bitselect */
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#define PATTERN_CSN_BITSELECT 0xc21cUL
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#define PATTERN_CSN_BITSELECT_PRESET 0x0UL
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/* REG SPI_nBits */
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#define SPI_NBITS 0xc220UL
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#define SPI_NBITS_MSK 0x1fUL
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#define SPI_NBITS_OFST 0
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/* REG DbitFIFOCTRLReg */
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#define DBITFIFOCTRLREG 0xc000UL
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#define DBITRD 0x1UL
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#define DBITRD_MSK 0x1UL
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#define DBITRD_OFST 0
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#define DBITRST 0x2UL
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#define DBITRST_MSK 0x2UL
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#define DBITRST_OFST 1
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#define DBITFULL 0x4UL
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#define DBITFULL_MSK 0x4UL
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#define DBITFULL_OFST 2
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#define DBITEMPTY 0x8UL
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#define DBITEMPTY_MSK 0x8UL
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#define DBITEMPTY_OFST 3
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#define DBITUNDERFLOW 0x10UL
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#define DBITUNDERFLOW_MSK 0x10UL
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#define DBITUNDERFLOW_OFST 4
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#define DBITOVERFLOW 0x20UL
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#define DBITOVERFLOW_MSK 0x20UL
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#define DBITOVERFLOW_OFST 5
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/* REG DbitFIFODataReg1 */
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#define DBITFIFODATAREG1 0xc004UL
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#define DBITFIFODATAREG1_PRESET 0x0UL
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/* REG DbitFIFODataReg2 */
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#define DBITFIFODATAREG2 0xc008UL
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#define DBITFIFODATAREG2_PRESET 0x0UL
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/* REG MatterhornSPIReg1 */
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#define MATTERHORNSPIREG1 0xc00cUL
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#define MATTERHORNSPIREG1_PRESET 0x0UL
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/* REG MatterhornSPIReg2 */
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#define MATTERHORNSPIREG2 0xc010UL
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#define MATTERHORNSPIREG2_PRESET 0x0UL
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/* REG MatterhornSPICTRL */
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#define MATTERHORNSPICTRL 0xc014UL
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#define CONFIGSTART_P 0x1UL
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#define CONFIGSTART_P_MSK 0x1UL
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#define CONFIGSTART_P_OFST 0
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#define PERIPHERYRST_P 0x2UL
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#define PERIPHERYRST_P_MSK 0x2UL
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#define PERIPHERYRST_P_OFST 1
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#define STARTREAD_P 0x4UL
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#define STARTREAD_P_MSK 0x4UL
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#define STARTREAD_P_OFST 2
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#define BUSY 0x8UL
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#define BUSY_MSK 0x8UL
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#define BUSY_OFST 3
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#define READOUTFROMASIC 0x10UL
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#define READOUTFROMASIC_MSK 0x10UL
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#define READOUTFROMASIC_OFST 4
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/* REG MISO_select */
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#define MISO_SELECT 0xc018UL
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#define MISO_SELECT_PRESET 0x0UL
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/* REG A_FIFO_Overflow_Status_Reg */
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#define A_FIFO_OVERFLOW_STATUS_REG 0x9000UL
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#define A_FIFO_OVERFLOW_STATUS_REG_PRESET 0x0UL
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/* REG A_FIFO_Empty_Status_Reg */
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#define A_FIFO_EMPTY_STATUS_REG 0x9004UL
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#define A_FIFO_EMPTY_STATUS_REG_PRESET 0x0UL
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/* REG A_FIFO_Full_Status_Reg */
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#define A_FIFO_FULL_STATUS_REG 0x9008UL
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#define A_FIFO_FULL_STATUS_REG_PRESET 0x0UL
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/* REG D_FIFO_Overflow_Status_Reg */
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#define D_FIFO_OVERFLOW_STATUS_REG 0x900cUL
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#define D_FIFO_OVERFLOW_STATUS 0x1UL
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#define D_FIFO_OVERFLOW_STATUS_MSK 0x1UL
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#define D_FIFO_OVERFLOW_STATUS_OFST 0
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/* REG D_FIFO_Empty_Status_Reg */
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#define D_FIFO_EMPTY_STATUS_REG 0x9010UL
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#define D_FIFO_EMPTY_STATUS 0x1UL
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#define D_FIFO_EMPTY_STATUS_MSK 0x1UL
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#define D_FIFO_EMPTY_STATUS_OFST 0
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/* REG D_FIFO_Full_Status_Reg */
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#define D_FIFO_FULL_STATUS_REG 0x9014UL
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#define D_FIFO_FULL_STATUS 0x1UL
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#define D_FIFO_FULL_STATUS_MSK 0x1UL
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#define D_FIFO_FULL_STATUS_OFST 0
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/* REG X_FIFO_Overflow_Status_Reg */
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#define X_FIFO_OVERFLOW_STATUS_REG 0x9018UL
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#define X_FIFO_OVERFLOW_STATUS_MSK 0xfUL
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#define X_FIFO_OVERFLOW_STATUS_OFST 0
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/* REG X_FIFO_Empty_Status_Reg */
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#define X_FIFO_EMPTY_STATUS_REG 0x901cUL
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#define X_FIFO_EMPTY_STATUS_MSK 0xfUL
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#define X_FIFO_EMPTY_STATUS_OFST 0
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/* REG X_FIFO_Full_Status_Reg */
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#define X_FIFO_FULL_STATUS_REG 0x9020UL
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#define X_FIFO_FULL_STATUS_MSK 0xfUL
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#define X_FIFO_FULL_STATUS_OFST 0
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/* REG A_FIFO_Clean_Reg */
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#define A_FIFO_CLEAN_REG 0x9024UL
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#define A_FIFO_CLEAN_REG_PRESET 0x0UL
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/* REG D_FIFO_Clean_Reg */
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#define D_FIFO_CLEAN_REG 0x9028UL
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#define D_FIFO_CLEAN 0x1UL
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#define D_FIFO_CLEAN_MSK 0x1UL
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#define D_FIFO_CLEAN_OFST 0
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/* REG X_FIFO_Clean_Reg */
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#define X_FIFO_CLEAN_REG 0x902cUL
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#define X_FIFO_CLEAN_MSK 0xfUL
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#define X_FIFO_CLEAN_OFST 0
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#endif /* __CHEBY__XCTB__H__ */
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// ----------------------------------------------------
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// TODO: fix these in the firmware reg generator:
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// ----------------------------------------------------:
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#define DELAY_OUT_REG_1 (0xB054)
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#define DELAY_OUT_REG_2 (0xB058)
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#define CYCLES_OUT_REG_1 (0xB05C)
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#define CYCLES_OUT_REG_2 (0xB060)
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#define FRAMES_OUT_REG_1 (0xB064)
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#define FRAMES_OUT_REG_2 (0xB068)
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#define PERIOD_OUT_REG_1 (0xB06C)
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#define PERIOD_OUT_REG_2 (0xB070)
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// clang-format on
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