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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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150 lines
5.4 KiB
C
150 lines
5.4 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include "RegisterDefs.h"
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#include "sls/sls_detector_defs.h"
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#define MIN_REQRD_VRSN_T_RD_API 0x180314
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#define REQRD_FRMWR_VRSN 0x220825
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#define LINKED_SERVER_NAME "moenchDetectorServer"
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#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl : 4, ip_ver : 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset : 13, ip_flags : 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define IP_HEADER_SIZE (20)
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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/* Enums */
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enum DACINDEX {
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MO_VBP_COLBUF,
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MO_VIPRE,
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MO_VIN_CM,
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MO_VB_SDA,
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MO_VCASC_SFP,
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MO_VOUT_CM,
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MO_VIPRE_CDS,
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MO_IBIAS_SFP
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};
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#define DAC_NAMES \
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"vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", \
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"vipre_cds", "ibias_sfp"
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#define DEFAULT_DAC_VALS \
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{ \
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1300, /* MO_VBP_COLBUF */ \
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1000, /* MO_VIPRE */ \
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1400, /* MO_VIN_CM */ \
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680, /* MO_VB_SDA */ \
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1428, /* MO_VCASC_SFP */ \
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1200, /* MO_VOUT_CM */ \
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800, /* MO_VIPRE_CDS */ \
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900 /* MO_IBIAS_SFP */ \
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};
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enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
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#define CLK_NAMES "run", "adc", "sync", "dbit"
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/* Hardware Definitions */
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#define NCHAN (32)
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#define NCHIP (1)
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#define NDAC (8)
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define CLK_FREQ (156.25) /* MHz */
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#define NSAMPLES_PER_ROW (25)
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#define NCHANS_PER_ADC (25)
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/** Default Parameters */
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#define DEFAULT_PATTERN_FILE ("DefaultPattern_moench.txt")
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#define DEFAULT_STARTING_FRAME_NUMBER (1)
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#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define DEFAULT_NUM_SAMPLES (5000)
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#define DEFAULT_EXPTIME (0)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_VLIMIT (-100)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_RUN_CLK_AT_STARTUP (200) // 40
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#define DEFAULT_ADC_CLK_AT_STARTUP (40) // 20
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#define DEFAULT_SYNC_CLK_AT_STARTUP (40) // 20
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#define DEFAULT_DBIT_CLK_AT_STARTUP (200)
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#define DEFAULT_RUN_CLK (40)
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#define DEFAULT_ADC_CLK (20)
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#define DEFAULT_DBIT_CLK (40)
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#define DEFAULT_ADC_PHASE_DEG (30)
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#define DEFAULT_PIPELINE (15)
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#define DEFAULT_SETTINGS (G4_HIGHGAIN)
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#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
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// settings
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#define DEFAULT_PATMASK (0x00000C800000800AULL)
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#define G1_HIGHGAIN_PATSETBIT (0x00000C0000008008ULL)
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#define G1_LOWGAIN_PATSETBIT (0x0000040000008000ULL)
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#define G2_HIGHCAP_HIGHGAIN_PATSETBIT (0x0000080000000008ULL)
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#define G2_HIGHCAP_LOWGAIN_PATSETBIT (0x0000000000000000ULL)
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#define G2_LOWCAP_HIGHGAIN_PATSETBIT (0x00000C800000800AULL)
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#define G2_LOWCAP_LOWGAIN_PATSETBIT (0x0000048000008002ULL)
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#define G4_HIGHGAIN_PATSETBIT (0x000008800000000AULL)
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#define G4_LOWGAIN_PATSETBIT (0x0000008000000002ULL)
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#define HIGHVOLTAGE_MIN (60)
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#define HIGHVOLTAGE_MAX (200) // min dac val
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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/* Defines in the Firmware */
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#define DIGITAL_IO_DELAY_MAXIMUM_PS \
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((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
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OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
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#define MAX_PHASE_SHIFTS_STEPS (8)
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#define WAIT_TME_US_FR_ACQDONE_REG \
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(100) // wait time in us after acquisition done to ensure there is no data
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// in fifo
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#define WAIT_TIME_US_PLL (10 * 1000)
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#define WAIT_TIME_US_STP_ACQ (100)
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#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
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#define WAIT_TIME_PATTERN_READ (10)
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#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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#define LSB_OF_64_BIT_REG_OFST (0)
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#define BIT32_MSK (0xFFFFFFFF)
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#define BIT16_MASK (0xFFFF)
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#define ADC_PORT_INVERT_VAL (0x4a342593)
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#define MAXIMUM_ADC_CLK (20)
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#define PLL_VCO_FREQ_MHZ (800)
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