mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 15:00:02 +02:00
Dhanya Thattil
3d21bb64c4
* period and exptime(patternwaittime level 0) * added new regsieterdefs and updated api version and fixedpattern reg * autogenerate commands * formatting * minor * wip resetflow, readout mode, transceiver mask, transceiver enable * acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw * programming fpga and device tree done * most configuration done, need to connect configuretransceiver to client * stuck at resetting transciever timed out * minor * fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber * configuretransceiver from client, added help in client * make formatt and command generation * tests for xilinx ctb works * command generation * dacs added and tested, power not done * power added * added temp_fpga * binaries in * ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed * start works * virtual server sends * receiver works * tests * python function and enum generation, commands generatorn and autocomplete, formatting, tests * tests fail at start(transceiver not aligned) * tests passed * all binaries compiled * eiger binary in * added --nomodule cehck for xilinx
177 lines
5.0 KiB
C
177 lines
5.0 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include "RegisterDefs.h"
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#include "sls/sls_detector_defs.h"
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#define MIN_REQRD_VRSN_T_RD_API 0x181130
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#define REQRD_FRMWR_VRSN 0x230705
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#define NUM_HARDWARE_VERSIONS (1)
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#define HARDWARE_VERSION_NUMBERS \
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{ 0x3f }
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#define HARDWARE_VERSION_NAMES \
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{ "5.1" }
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#define LINKED_SERVER_NAME "ctbDetectorServer"
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#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
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/* Hardware Definitions */
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#define NCHAN (40)
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#define NCHAN_ANALOG (32)
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#define NCHAN_DIGITAL (64)
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#define NCHAN_TRANSCEIVER (4)
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#define NBITS_PER_TRANSCEIVER (64)
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#define NCHIP (1)
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#define NDAC (24)
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#define NPWR (6)
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#define NDAC_ONLY (NDAC - NPWR)
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define CLK_FREQ (156.25) // MHz
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#define I2C_POWER_VIO_DEVICE_ID (0x40)
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#define I2C_POWER_VA_DEVICE_ID (0x41)
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#define I2C_POWER_VB_DEVICE_ID (0x42)
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#define I2C_POWER_VC_DEVICE_ID (0x43)
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#define I2C_POWER_VD_DEVICE_ID (0x44)
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#define I2C_SHUNT_RESISTER_OHMS (0.005)
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/** Default Parameters */
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#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define DEFAULT_STARTING_FRAME_NUMBER (1)
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#define DEFAULT_NUM_SAMPLES (1)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_EXPTIME (0)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_VLIMIT (-100)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_RUN_CLK (200) // 40
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#define DEFAULT_ADC_CLK (40) // 20
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#define DEFAULT_SYNC_CLK (40) // 20
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#define DEFAULT_DBIT_CLK (200)
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#define DEFAULT_TRANSCEIVER_MASK (0x3)
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#define MAX_TRANSCEIVER_MASK (0xF)
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#define MAX_TRANSCEIVER_SAMPLES (0xFFFF)
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#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
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#define HIGHVOLTAGE_MIN (60)
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#define HIGHVOLTAGE_MAX (200) // min dac val
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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#define VCHIP_MIN_MV (1673)
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#define VCHIP_MAX_MV (2668) // min dac val
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#define POWER_RGLTR_MIN (636)
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#define POWER_RGLTR_MAX \
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(2638) // min dac val (not vchip-max) because of dac conversions
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#define VCHIP_POWER_INCRMNT (200)
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#define VIO_MIN_MV (1200) // for fpga to function
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/* Defines in the Firmware */
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#define DIGITAL_IO_DELAY_MAXIMUM_PS \
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((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
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OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
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#define MAX_PHASE_SHIFTS_STEPS (8)
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#define WAIT_TME_US_FR_ACQDONE_REG \
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(100) // wait time in us after acquisition done to ensure there is no data
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// in fifo
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#define WAIT_TIME_US_PLL (10 * 1000)
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#define WAIT_TIME_US_STP_ACQ (100)
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#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
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#define WAIT_TIME_PATTERN_READ (10)
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#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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#define LSB_OF_64_BIT_REG_OFST (0)
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#define BIT32_MSK (0xFFFFFFFF)
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#define BIT16_MASK (0xFFFF)
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#define MAXIMUM_ADC_CLK (65)
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#define PLL_VCO_FREQ_MHZ (800)
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl : 4, ip_ver : 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset : 13, ip_flags : 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define IP_HEADER_SIZE (20)
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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/* Enums */
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enum ADCINDEX {
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V_PWR_IO,
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V_PWR_A,
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V_PWR_B,
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V_PWR_C,
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V_PWR_D,
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I_PWR_IO,
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I_PWR_A,
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I_PWR_B,
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I_PWR_C,
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I_PWR_D,
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S_ADC0,
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S_ADC1,
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S_ADC2,
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S_ADC3,
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S_ADC4,
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S_ADC5,
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S_ADC6,
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S_ADC7,
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S_TMP
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};
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enum DACINDEX {
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D0,
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D1,
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D2,
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D3,
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D4,
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D5,
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D6,
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D7,
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D8,
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D9,
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D10,
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D11,
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D12,
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D13,
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D14,
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D15,
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D16,
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D17,
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D_PWR_D,
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D_PWR_CHIP,
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D_PWR_C,
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D_PWR_B,
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D_PWR_A,
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D_PWR_IO
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};
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enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
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#define CLK_NAMES "run", "adc", "sync", "dbit"
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