mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-24 07:20:01 +02:00
2f2fe4dd47
* Setting pattern from memory (#218) * ToString accepts c-style arrays * fixed patwait time bug in validation * Introduced pattern class * compile for servers too * Python binding for Pattern * added scanParameters in Python * slsReceiver: avoid potential memory leak around Implementation::generalData * additional constructors for scanPrameters in python * bugfix: avoid potentital memory leak in receiver if called outside constructor context * added scanParameters in Python * additional constructors for scanPrameters in python * M3defaultpattern (#227) * default pattern for m3 and moench including Python bindings * M3settings (#228) * some changes to compile on RH7 and in the server to load the default chip status register at startup * Updated mythen3DeectorServer_developer executable with correct initialization at startup Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com> Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch> * Pattern.h as a public header files (#229) * fixed buffer overflow but caused by using global instead of local enum * replacing out of range trimbits with edge values * replacing dac values that are out of range after interpolation * updated pybind11 to 2.6.2 * Mythen3 improved synchronization (#231) Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready startDetector first starts the slaves then the master acquire firs calls startDetector for the slaves then acquire on the master getMaster to read back from hardware which one is master * New server for JF to go with the new FW (#232) * Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218 * Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed. * fix for m3 scan with single module * m3 fw version * m3 server * bugfix for bottom when setting quad * new strategy for finding zmq based on cppzmq Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch> Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com> Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr> Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch> Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com> Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
151 lines
6.2 KiB
C
151 lines
6.2 KiB
C
#pragma once
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#include "RegisterDefs.h"
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#include "sls/sls_detector_defs.h"
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#define MIN_REQRD_VRSN_T_RD_API 0x171220
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#define REQRD_FRMWRE_VRSN_BOARD2 0x210218 // 1.0 pcb
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#define REQRD_FRMWRE_VRSN 0x200721 // 2.0 pcb
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl : 4, ip_ver : 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset : 13, ip_flags : 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define IP_HEADER_SIZE (20)
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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/* Enums */
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enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
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enum DACINDEX {
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J_VB_COMP,
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J_VDD_PROT,
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J_VIN_COM,
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J_VREF_PRECH,
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J_VB_PIXBUF,
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J_VB_DS,
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J_VREF_DS,
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J_VREF_COMP
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};
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#define DAC_NAMES \
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"vb_comp", "vdd_prot", "vin_com", "vref_prech", "vb_pixbuf", "vb_ds", \
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"vref_ds", "vref_comp"
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#define DEFAULT_DAC_VALS \
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{ \
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1220, /* J_VB_COMP */ \
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3000, /* J_VDD_PROT */ \
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1053, /* J_VIN_COM */ \
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1450, /* J_VREF_PRECH */ \
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750, /* J_VB_PIXBUF */ \
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1000, /* J_VB_DS */ \
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480, /* J_VREF_DS */ \
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420 /* J_VREF_COMP */ \
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};
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enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
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enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
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#define CLK_NAMES "run", "adc", "dbit"
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/* Hardware Definitions */
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#define NCHAN (256 * 256)
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#define NCHIP (8)
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#define NDAC (8)
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define DATA_BYTES (NCHIP * NCHAN * NUM_BYTES_PER_PIXEL)
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#define CLK_RUN (40) // MHz
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#define CLK_SYNC (20) // MHz
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#define ADC_CLK_INDEX (1)
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#define DBIT_CLK_INDEX (0)
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
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#define DEFAULT_STARTING_FRAME_NUMBER (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (10 * 1000) // ns
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#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
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#define DEFAULT_DELAY (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_TMP_THRSHLD (65 * 1000) // milli degree Celsius
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#define DEFAULT_NUM_STRG_CLLS (0)
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#define DEFAULT_STRG_CLL_STRT (0xf)
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#define DEFAULT_STRG_CLL_DLY (0)
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#define HIGHVOLTAGE_MIN (60)
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#define HIGHVOLTAGE_MAX (200)
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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/* Defines in the Firmware */
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#define MAX_TIMESLOT_VAL (0x1F)
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#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
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#define MAX_STORAGE_CELL_VAL (15) // 0xF
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#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
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#define ACQ_TIME_MIN_CLOCK (2)
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#define MAX_PHASE_SHIFTS (240)
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#define BIT16_MASK (0xFFFF)
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// pipeline
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#define ADC_OFST_FULL_SPEED_VAL (0x10) // 2.0 pcb
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#define ADC_OFST_HALF_SPEED_VAL (0x08) // 2.0 pcb
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#define ADC_OFST_QUARTER_SPEED_VAL (0x04) // 2.0 pcb
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#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x10) // 1.0 pcb (2 resistor network)
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#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x08) // 1.0 pcb (2 resistor network)
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#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
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#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
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// 2.0 pcb
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#define SAMPLE_ADC_FULL_SPEED \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
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SAMPLE_DGTL_SAMPLE_1_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x100
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#define SAMPLE_ADC_HALF_SPEED \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
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SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
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#define SAMPLE_ADC_QUARTER_SPEED \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
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SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
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// 1.0 pcb (2 resistor network)
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#define SAMPLE_ADC_HALF_SPEED_BOARD2 \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
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SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1300
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#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 \
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(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
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SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2610
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#define ADC_PHASE_FULL_SPEED (150) // 2.0 pcb
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#define ADC_PHASE_HALF_SPEED (200) // 2.0 pcb
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#define ADC_PHASE_QUARTER_SPEED (200) // 2.0 pcb
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#define ADC_PHASE_HALF_SPEED_BOARD2 (110) // 1.0 pcb (2 resistor network)
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#define ADC_PHASE_QUARTER_SPEED_BOARD2 (220) // 1.0 pcb (2 resistor network)
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#define DBIT_PHASE_FULL_SPEED (85) // 2.0 pcb
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#define DBIT_PHASE_HALF_SPEED (150) // 2.0 pcb
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#define DBIT_PHASE_QUARTER_SPEED (150) // 2.0 pcb
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#define DBIT_PHASE_HALF_SPEED_BOARD2 (150) // 1.0 pcb (2 resistor network)
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#define DBIT_PHASE_QUARTER_SPEED_BOARD2 (150) // 1.0 pcb (2 resistor network)
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