mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-28 01:00:02 +02:00
6e6fcec698
* MY3.0:read and write Registers, frames, cycles, delay * write pattern seems to work * done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos) * clk check for aquistition time * clk check for aquistition time * Update slsDetectorServer_defs.h * Update slsDetectorFunctionList.c
52 lines
2.1 KiB
C
52 lines
2.1 KiB
C
#pragma once
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#include "sls_detector_defs.h"
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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/* Hardware Definitions */
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#define NCHAN (128)
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#define NCHIP (10)
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#define NDAC (16)
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#define HV_SOFT_MAX_VOLTAGE (200)
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#define HV_HARD_MAX_VOLTAGE (530)
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#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (100*1000*1000) //ns
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#define DEFAULT_PERIOD (2*1000*1000) //ns
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#define DEFAULT_DELAY_AFTER_TRIGGER (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_RUN_CLK (125)
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#define DEFAULT_TICK_CLK (20) // will be fixed later. Not configurable
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#define DEFAULT_SAMPLING_CLK (80)
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/* Enums */
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enum CLKINDEX {RUN_CLK, TICK_CLK, SAMPLING_CLK, NUM_CLOCKS};
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enum DACINDEX {VIBIASSH, VTRIM, VIPRE, VRFSHNPOL, VTH1, VIPREOUT, VRF, VTH2, CAS, CASSH, VPL, VDCSH, VICIN, VICINSH, VICBIAS, VPH, VTH3, VRFSH};
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#define DEFAULT_DAC_VALS {1200, /* vIbiasSh */ \
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2300, /* vTrim */ \
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2150, /* vIpre */ \
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2300, /* VrfShNpol */ \
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900, /* Vth1 */ \
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1000, /* vIpreOut */ \
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900, /* Vrf */ \
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900, /* Vth2 */ \
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1474, /* cas */ \
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983, /* casSh */ \
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900, /* VPL */ \
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655, /* VdcSh */ \
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1400, /* vIcin */ \
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1400, /* vIcinSh */ \
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1200, /* vIcbias */ \
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960, /* VPH */ \
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900, /* Vth3 */ \
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1100 /* VrfSh */ \
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};
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/* Defines in the Firmware */
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#define MAX_PATTERN_LENGTH (0x8192) // maximum number of words (64bit)
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