Dhanya Thattil ff4ce48e5d receiver memory alignment: all data and header is a multiple of 64 bit, just the fifo header size needed to be 8

2019-04-18 11:35:08 +02:00

..

include

receiver memory alignment: all data and header is a multiple of 64 bit, just the fifo header size needed to be 8

2019-04-18 11:35:08 +02:00

src

eiger receiver fix: setting eth2 as well for eiger

2019-04-18 11:16:02 +02:00

tests

merging refactor (replacing)

2019-04-12 10:53:09 +02:00

CMakeLists.txt

merging refactor (replacing)

2019-04-12 10:53:09 +02:00

slsReceiverUsers.doxy

merging refactor (replacing)

2019-04-12 10:53:09 +02:00