mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 15:00:02 +02:00
143 lines
5.2 KiB
C
143 lines
5.2 KiB
C
#pragma once
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#include "sls_detector_defs.h"
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#define REQRD_FRMWRE_VRSN (0x190000)
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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/* Hardware Definitions */
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#define NCHAN (128)
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#define NCHIP (10)
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#define NDAC (16)
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#define NADC (32)
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#define ONCHIP_NDAC (7)
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#define DYNAMIC_RANGE (16)
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#define HV_SOFT_MAX_VOLTAGE (200)
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#define HV_HARD_MAX_VOLTAGE (530)
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#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
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#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
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#define ONCHIP_DAC_DRIVER_FILE_NAME ("/etc/devlinks/chipdac")
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#define TYPE_FILE_NAME ("/etc/devlinks/type")
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#define CONFIG_FILE ("config.txt")
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#define DAC_MAX_MV (2048)
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#define ONCHIP_DAC_MAX_VAL (0x3FF)
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#define ADU_MAX_VAL (0xFFF)
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#define ADU_MAX_BITS (12)
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#define MAX_FRAMES_IN_BURST_MODE (2720)
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#define TYPE_GOTTHARD2_MODULE_VAL (512)
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#define TYPE_TOLERANCE (10)
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#define TYPE_NO_MODULE_STARTING_VAL (800)
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#define INITIAL_STARTUP_WAIT (1 * 1000 * 1000)
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/** Default Parameters */
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#define DEFAULT_BURST_MODE (BURST_INTERNAL)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_NUM_BURSTS (1)
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#define DEFAULT_EXPTIME (0) // 0 ms (220ns in firmware)
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#define DEFAULT_PERIOD (0) // 0 ms
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#define DEFAULT_DELAY_AFTER_TRIGGER (0)
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#define DEFAULT_BURST_PERIOD (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_CURRENT_SOURCE (0)
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#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
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#define DEFAULT_READOUT_C0 (144444448) // rdo_clk, 144 MHz
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#define DEFAULT_READOUT_C1 (144444448) // rdo_x2_clk, 144 MHz
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#define DEFAULT_SYSTEM_C0 (144444448) // run_clk, 144 MHz
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#define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz
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#define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz
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#define DEFAULT_SYSTEM_C3 (144444448) // str_clk, 144 MHz
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/* Firmware Definitions */
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#define IP_HEADER_SIZE (20)
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#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
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#define INT_SYSTEM_C0_FREQUENCY (144000000) //144 MHz
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#define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (722222224) // 722 MHz
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/** Other Definitions */
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#define BIT16_MASK (0xFFFF)
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/* Enums */
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enum DACINDEX {G2_VREF_H_ADC, /* 0 */ \
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G2_DAC_UNUSED, /* 1 */ \
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G2_VB_COMP_FE, /* 2 */ \
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G2_VB_COMP_ADC, /* 3 */ \
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G2_VCOM_CDS, /* 4 */ \
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G2_VREF_RSTORE,/* 5 */ \
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G2_VB_OPA_1ST, /* 6 */ \
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G2_VREF_COMP_FE,/* 7 */ \
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G2_VCOM_ADC1, /* 8 */ \
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G2_VREF_PRECH, /* 9 */ \
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G2_VREF_L_ADC, /* 10 */ \
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G2_VREF_CDS, /* 11 */ \
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G2_VB_CS, /* 12 */ \
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G2_VB_OPA_FD, /* 13 */ \
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G2_DAC_UNUSED2, /* 14 */ \
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G2_VCOM_ADC2 /* 15*/ \
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};
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#define DAC_NAMES "vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", "vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", "vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", "dac_unused2", "vcom_adc2"
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enum ONCHIP_DACINDEX {G2_VCHIP_COMP_FE, /* 0 */ \
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G2_VCHIP_OPA_1ST, /* 1 */ \
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G2_VCHIP_OPA_FD, /* 2 */ \
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G2_VCHIP_COMP_ADC, /* 3 */ \
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G2_VCHIP_UNUSED, /* 4 */ \
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G2_VCHIP_REF_COMP_FE, /* 5 */ \
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G2_VCHIP_CS /* 6 */ \
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};
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#define ONCHIP_DAC_NAMES "vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", "vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
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enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
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#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
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enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
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/** Chip Definitions */
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#define ASIC_ADDR_MAX_BITS (4)
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#define ASIC_CURRENT_INJECT_ADDR (0x9)
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#define ASIC_VETO_REF_ADDR (0xA)
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#define ASIC_CONF_ADC_ADDR (0xB)
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#define ASIC_CONF_GLOBAL_SETT (0xC)
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#define ASIC_GAIN_MAX_BITS (2)
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#define ASIC_GAIN_MSK (0x3)
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#define ASIC_G0_VAL ((0x0 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
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#define ASIC_G1_VAL ((0x1 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
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#define ASIC_G2_VAL ((0x3 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
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#define ASIC_CONTINUOUS_MODE_MSK (0x7)
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#define ASIC_ADC_MAX_BITS (7)
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#define ASIC_ADC_MAX_VAL (0x7F)
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#define ASIC_GLOBAL_SETT_MAX_BITS (6)
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#define ASIC_GLOBAL_BURST_VALUE (0x0)
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#define ASIC_GLOBAL_CONT_VALUE (0x1E)
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl: 4, ip_ver: 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset: 13, ip_flags: 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define UDP_IP_HEADER_LENGTH_BYTES (28) |