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maliakal_dandGitHub 1d4a5d6d29 dev: jungfrau HW 1.0: adc output clock phase to 120 (#952) 
* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* versioning

* formatting
2024-08-22 15:45:41 +02:00
..
sls
dev: jungfrau HW 1.0: adc output clock phase to 120 (#952)
2024-08-22 15:45:41 +02:00