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01c754801fa32f35dce9062a88e122598682cf2a
slsDetectorPackage/slsDetectorServers/ctbDetectorServer/RegisterDefs.h
T
Martin MuellerGitHubmuelle_m1maliakal_d
 0837de2a5a CTB frequency rounding, CTB frequency measurement, CTB frequency units (#1423) 
* round CTB clocks to next closest possible value, added freq measurement

* added time for firmware to measrue actual value after frequency change

* add check for backwards compatibility

* change CTB and XCTB clock values to MHz, TODO: units and validation errors

* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?

* do the same for dbit and adcclk

* added tolerance to exptime, fixed test

* update default values in server defs

* added virtual check in Altera_PLL, update testcases

* change python and pyctbgui to accept and return floating point MHz

* update help and comments

* Dev/ctb clocks fix (#1434)

* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)

* incorrect unit typo

* cmd generation and compiles

* default to MHz, removed space between units for consistency with timers, min and max checks for clks

* in python, but need to change the default to Hz again for clean code and intuition

* allow ints, doubles, implicit conversions

* dont allow raw ints, doubles and implicit conversions

* fixed tests

* added operators for Hz in python

* fix test for min clk for xilinx ctb

* fix test

* fix python tests

* fixed xilinx period and default clks

* test fix

* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb

* removing 3 clock cycle code from xilinx as well

* formatting

* loadpattern before 3 clk cycles code

* actualtime and measurement time to be implemented in 100ns already in fw

* fix tests

* pyzmq dependency forthe tests

* fixed pyctbgui for freq

* insert tolerance check again

* also added tolerance check for patwaittime

* formatting

* minor: rounding test

* removed Rep redundant in ToString for freq

* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary

* minor, and binaries

* minor, default clk vals are 0 but set up at detector setup

* get frequency only for that unit

* tolerance process

* missed in previous commit

* some more changes to exptime and validations

* ctb is probably done

* periodleft and delayleft

* fixed xilinx freq conv as well

* fixed m3 bug, binaries

* xilinx: setup also done in stop server so that the clk is not 0

* missed a test marker

* binaries in

* review fixes, simpler validation of timers in ctb and xilinx ctb

* typo fix

* format

* fix tests

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
2026-05-06 15:52:13 +02:00

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// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
// clang-format off
/* Definitions for FPGA */
#define MEM_MAP_SHIFT 1
#define REG_OFFSET (2)
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_VERSION_BRD_RVSN_OFST (0)
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL \
((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC2016)
/* Status RO register */
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_ANY_FF_FLL_OFST (2)
#define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_SM_FF_FLL_OFST (11)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_STPPD_OFST (15)
#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (16)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_CYCL_RN_BSY_OFST (17)
#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
#define STATUS_FRM_RN_BSY_OFST (18)
#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
#define STATUS_ADC_DESERON_OFST (19)
#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
#define STATUS_PLL_RCNFG_BSY_OFST (20)
#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
#define STATUS_DT_STRMNG_BSY_OFST (21)
#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
#define STATUS_FRM_PCKR_BSY_OFST (22)
#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK \
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Register containing the git hash of the FPGA firmware */
#define FIRMWARE_GIT_HASH_REG (0x03 << MEM_MAP_SHIFT)
/* System Status RO register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
* PLL_PARAM_REG 0x50 */
// #define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
// #define FIFO_DATA_WRD_OFST (16)
// #define FIFO_DATA_WRD_MSK (0x0000FFFF <<
// FIFO_DATA_WRD_OFST)
/* FIFO Status RO register TODO */
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
/* FIFO Empty RO register TODO */
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
/* FIFO Full RO register TODO */
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
/* MCB Serial Number RO register */
#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
#define MOD_SERIAL_NUMBER_OFST (0)
#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
/* API Version RO register */
#define API_VERSION_REG (0x0B << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x97 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x98 << MEM_MAP_SHIFT)
/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
#define DELAY_LEFT_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x8E << MEM_MAP_SHIFT)
/* Triggers Left 64 bit RO register TODO */
#define CYCLES_LEFT_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x90 << MEM_MAP_SHIFT)
/* Frames Left 64 bit RO register TODO */
#define FRAMES_LEFT_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x92 << MEM_MAP_SHIFT)
/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
#define PERIOD_LEFT_LSB_REG (0x93 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x94 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
// #define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
// used in FW #define EXPTIME_LEFT_MSB_REG (0x1B <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Gates Left 64 bit RO register */
// #define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
// used in FW #define GATES_LEFT_MSB_REG (0x1D <<
// MEM_MAP_SHIFT)
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Pattern Out 64 bit RO register */
#define PATTERN_OUT_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x81 << MEM_MAP_SHIFT)
/* Frame number of next acquisition register (64 bit register) */
#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x13 << MEM_MAP_SHIFT)
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x99 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x9A << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x9B << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x9C << MEM_MAP_SHIFT)
/* Power Status RO register */
#define POWER_STATUS_REG (0x18 << MEM_MAP_SHIFT)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
/* FIFO Transceiver In Status RO register */
#define FIFO_TIN_STATUS_REG (0x1A << MEM_MAP_SHIFT)
#define FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST (4)
#define FIFO_TIN_STATUS_FIFO_EMPTY_1_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST (5)
#define FIFO_TIN_STATUS_FIFO_EMPTY_2_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_3_OFST (6)
#define FIFO_TIN_STATUS_FIFO_EMPTY_3_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_3_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST (7)
#define FIFO_TIN_STATUS_FIFO_EMPTY_4_MSK (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST)
#define FIFO_TIN_STATUS_FIFO_EMPTY_ALL_MSK (0x0000000F << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
/* FIFO Transceiver Fill level RO register */
#define FIFO_TIN_FILL_REG (0x25 << MEM_MAP_SHIFT)
#define FIFO_TIN_FILL_FIFO_1_OFST (0)
#define FIFO_TIN_FILL_FIFO_1_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__1_OFST)
#define FIFO_TIN_FILL_FIFO_2_OFST (16)
#define FIFO_TIN_FILL_FIFO_2_MSK (0x00003FFF << FIFO_TIN_FILL_FIFO__2_OFST)
/* FIFO ADC Fill level RO register */
#define FIFO_ADC_FILL_REG (0x26 << MEM_MAP_SHIFT)
#define FIFO_ADC_FILL_FIFO_OFST (0)
#define FIFO_ADC_FILL_FIFO_MSK (0x00003FFF << FIFO_ADC_FILL_FIFO_OFST)
/* Enable continuos readout register */
#define CONTINUOUS_RO_ENABLE_REG (0x27 << MEM_MAP_SHIFT)
#define CONTINUOUS_RO_ADC_ENABLE_OFST (0)
#define CONTINUOUS_RO_TIN_ENABLE_OFST (1)
#define CONTINUOUS_RO_DBIT_ENABLE_OFST (2)
#define CONTINUOUS_RO_ADC_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_ADC_ENABLE_OFST)
#define CONTINUOUS_RO_TIN_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_TIN_ENABLE_OFST)
#define CONTINUOUS_RO_DBIT_ENABLE_MSK (0x00000001 << CONTINUOUS_RO_DBIT_ENABLE_OFST)
#define DBIT_INJECT_COUNTER_ENA_OFST (3) // continuously injects fake-data into the dbit fifo when enabled.
#define DBIT_INJECT_COUNTER_ENA_MSK (0x00000001 << DBIT_INJECT_COUNTER_ENA_OFST)
#define DBIT_INJECT_COUNTER_CLKDIV_OFST (8) // Additional clock divider for fake-data injection
#define DBIT_INJECT_COUNTER_CLKDIV_MSK (0x000000FF << DBIT_INJECT_COUNTER_CLKDIV_OFST)
/* 64-bit FPGA chip ID. Unique for every device. read-only */
#define FPGA_chipID_0_REG (0x28 << MEM_MAP_SHIFT)
#define FPGA_chipID_1_REG (0x29 << MEM_MAP_SHIFT)
/* FIFO Transceiver In 64 bit RO register */
#define FIFO_TIN_LSB_REG (0x1B << MEM_MAP_SHIFT)
#define FIFO_TIN_MSB_REG (0x1C << MEM_MAP_SHIFT)
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x1D << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FILL_OFST (0)
#define FIFO_DIN_STATUS_FIFO_FILL_MSK (0x00003FFF)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x1F << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
#define SPI_REG (0x20 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
/* ADC SPI (Serial Peripheral Interface) RW register */
#define ADC_SPI_REG (0x21 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
/* ADC Offset RW register */
#define ADC_OFFSET_REG (0x22 << MEM_MAP_SHIFT)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
#define ADC_OFFSET_DBT_PPLN_OFST (16)
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
/* ADC Port Invert RW register */
#define ADC_PORT_INVERT_REG (0x23 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
#define ADC_PORT_INVERT_1_INPT_OFST (8)
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
#define ADC_PORT_INVERT_2_INPT_OFST (16)
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
#define ADC_PORT_INVERT_3_INPT_OFST (24)
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
/* Dummy RW register */
#define DUMMY_REG (0x24 << MEM_MAP_SHIFT)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
#define DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_OFST (12)
#define DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_MSK (0x00000003 << DUMMY_TRNSCVR_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST (14)
#define DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST)
/* Configuration RW register */
#define CONFIG_REG (0x2D << MEM_MAP_SHIFT)
#define CONFIG_LED_DSBL_OFST (0)
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
#define CONFIG_ENBLE_ANLG_OTPT_OFST (8)
#define CONFIG_ENBLE_ANLG_OTPT_MSK (0x00000001 << CONFIG_ENBLE_ANLG_OTPT_OFST)
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
#define CONFIG_ENBLE_TRNSCVR_OTPT_OFST (10)
#define CONFIG_ENBLE_TRNSCVR_OTPT_MSK \
(0x00000001 << CONFIG_ENBLE_TRNSCVR_OTPT_OFST)
#define CONFIG_GB10_SND_UDP_OFST (12)
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
/* External Signal RW register */
#define EXT_SIGNAL_REG (0x2E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/* Control RW register */
#define CONTROL_REG (0x2F << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
// #define CONTROL_STRT_FF_TST_OFST (2)
// #define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
// CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
// #define CONTROL_STP_FF_TST_MSK (0x00000001 <<
// CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
// #define CONTROL_STRT_RDT_MSK (0x00000001 <<
// CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5)
// #define CONTROL_STP_RDT_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
// #define CONTROL_STP_EXPSR_OFST (7)
// #define CONTROL_STP_EXPSR_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8)
// #define CONTROL_STRT_TRN_MSK (0x00000001 <<
// CONTROL_STRT_RDT_OFST)
// #define CONTROL_STP_TRN_OFST (9)
// #define CONTROL_STP_TRN_MSK (0x00000001 <<
// CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
// #define CONTROL_PLL_RCNFG_WR_OFST (13)
// #define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
// CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_PARAM_REG (0x30 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_CNTRL_REG (0x31 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Streaming Control RW regiser */
#define STREAMING_CTRL_REG (0x3D << MEM_MAP_SHIFT)
#define STREAMING_CTRL_ENA_OFST (15)
#define STREAMING_CTRL_ENA_MSK (0x00000001 << STREAMING_CTRL_ENA_OFST)
#define STREAMING_CTRL_SELECT_OFST (0)
#define STREAMING_CTRL_SELECT_MSK (0x0000003F << STREAMING_CTRL_SELECT_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x88 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x89 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/** Pattern Loop and Wait Definitions, 5 regs each */
#define PATTERN_LOOPDEF_BASE (0xA0 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_ADDR_WORD_OFST (0)
#define PATTERN_LOOP_ITERATION_WORD_OFST (1)
#define PATTERN_WAIT_ADDR_WORD_OFST (2)
#define PATTERN_WAIT_TIMER_LSB_WORD_OFST (3)
#define PATTERN_WAIT_TIMER_MSB_WORD_OFST (4)
#define PATTERN_LOOPDEF_NWORDS_OFST (5)
#define PATTERN_WAIT_ADDR_OFST (0)
#define PATTERN_WAIT_ADDR_MSK (0x00001FFF << PATTERN_WAIT_ADDR_OFST)
#define PATTERN_LOOP_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STRT_OFST)
#define PATTERN_LOOP_ADDR_STP_OFST (16)
#define PATTERN_LOOP_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_ADDR_STP_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x32 << MEM_MAP_SHIFT)
#define SAMPLES_DIGITAL_OFST (0)
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
#define SAMPLES_ANALOG_OFST (16)
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
/** Power RW register */
#define POWER_REG (0x33 << MEM_MAP_SHIFT)
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
#define POWER_ENBL_VIO_OFST (16)
#define POWER_ENBL_VIO_MSK (0x00000001 << POWER_ENBL_VIO_OFST)
#define POWER_ENBL_VA_OFST (17)
#define POWER_ENBL_VA_MSK (0x00000001 << POWER_ENBL_VA_OFST)
#define POWER_ENBL_VB_OFST (18)
#define POWER_ENBL_VB_MSK (0x00000001 << POWER_ENBL_VB_OFST)
#define POWER_ENBL_VC_OFST (19)
#define POWER_ENBL_VC_MSK (0x00000001 << POWER_ENBL_VC_OFST)
#define POWER_ENBL_VD_OFST (20)
#define POWER_ENBL_VD_MSK (0x00000001 << POWER_ENBL_VD_OFST)
#define POWER_HV_INTERNAL_SLCT_OFST (31)
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
/* Number of samples from transceiver RW register */
#define SAMPLES_TRANSCEIVER_REG (0x34 << MEM_MAP_SHIFT)
#define SAMPLES_TRANSCEIVER_OFST (0)
#define SAMPLES_TRANSCEIVER_MSK (0x0000FFFF << SAMPLES_TRANSCEIVER_OFST)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x8E << MEM_MAP_SHIFT)
/* Triggers 64 bit RW register */
#define CYCLES_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x90 << MEM_MAP_SHIFT)
/* Frames 64 bit RW register */
#define FRAMES_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x92 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
#define PERIOD_LSB_REG (0x93 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x94 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
// #define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
// Not used in FW #define EXPTIME_MSB_REG (0x69 <<
// MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
// #define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not
// used
// in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
// Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
#define PATTERN_IO_CNTRL_LSB_REG (0x8A << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x8B << MEM_MAP_SHIFT)
/* Pattern In 64 bit RW register */
#define PATTERN_IN_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x83 << MEM_MAP_SHIFT)
/* Readout enable RW register */
#define READOUT_10G_ENABLE_REG (0x3C << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_ANLG_OFST (0)
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
#define READOUT_10G_ENABLE_DGTL_OFST (8)
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
#define READOUT_10G_ENABLE_TRNSCVR_OFST (9)
#define READOUT_10G_ENABLE_TRNSCVR_MSK \
(0x0000000F << READOUT_10G_ENABLE_TRNSCVR_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x3E << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x3F << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
// configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x40 << MEM_MAP_SHIFT)
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x84 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x85 << MEM_MAP_SHIFT)
/** Pattern Set 64 bit RW regiser */
#define PATTERN_SET_LSB_REG (0x86 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x87 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value RO register */
#define ADC_SLOW_DATA_REG (0x41 << MEM_MAP_SHIFT)
/* Slow ADC SPI Value Config register */
#define ADC_SLOW_CFG_REG (0x42 << MEM_MAP_SHIFT)
/** Read back CFG Register */
#define ADC_SLOW_CFG_RB_OFST (2)
#define ADC_SLOW_CFG_RB_MSK (0x00000001 << ADC_SLOW_CFG_RB_OFST)
/** Channel sequencer */
#define ADC_SLOW_CFG_SEQ_OFST (3)
#define ADC_SLOW_CFG_SEQ_MSK (0x00000003 << ADC_SLOW_CFG_SEQ_OFST)
#define ADC_SLOW_CFG_SEQ_DSBLE_VAL \
((0x0 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
#define ADC_SLOW_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL \
((0x1 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
#define ADC_SLOW_CFG_SEQ_SCN_WTH_TMP_VAL \
((0x2 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
#define ADC_SLOW_CFG_SEQ_SCN_WTHT_TMP_VAL \
((0x3 << ADC_SLOW_CFG_SEQ_OFST) & ADC_SLOW_CFG_SEQ_MSK)
/** Reference/ buffer selection */
#define ADC_SLOW_CFG_REF_OFST (5)
#define ADC_SLOW_CFG_REF_MSK (0x00000007 << ADC_SLOW_CFG_REF_OFST)
/** Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
*/
#define ADC_SLOW_CFG_REF_INT_2500MV_VAL \
((0x0 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_OFST)
/** Internal reference. REF = 4.096V buffered output. Temperature sensor
* enabled. */
#define ADC_SLOW_CFG_REF_INT_4096MV_VAL \
((0x1 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer disabled. */
#define ADC_SLOW_CFG_REF_EXT_TMP_VAL \
((0x2 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer enabled. */
#define ADC_SLOW_CFG_REF_EXT_TMP_INTBUF_VAL \
((0x3 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer disabled.
*/
#define ADC_SLOW_CFG_REF_EXT_VAL \
((0x6 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer enabled. */
#define ADC_SLOW_CFG_REF_EXT_INTBUF_VAL \
((0x7 << ADC_SLOW_CFG_REF_OFST) & ADC_SLOW_CFG_REF_MSK)
/** bandwidth of low pass filter */
#define ADC_SLOW_CFG_BW_OFST (8)
#define ADC_SLOW_CFG_BW_MSK (0x00000001 << ADC_SLOW_CFG_REF_OFST)
#define ADC_SLOW_CFG_BW_ONE_FOURTH_VAL \
((0x0 << ADC_SLOW_CFG_BW_OFST) & ADC_SLOW_CFG_BW_MSK)
#define ADC_SLOW_CFG_BW_FULL_VAL \
((0x1 << ADC_SLOW_CFG_BW_OFST) & ADC_SLOW_CFG_BW_MSK)
/** input channel selection IN0 - IN7 */
#define ADC_SLOW_CFG_IN_OFST (9)
#define ADC_SLOW_CFG_IN_MSK (0x00000007 << ADC_SLOW_CFG_IN_OFST)
/** input channel configuration */
#define ADC_SLOW_CFG_INCC_OFST (12)
#define ADC_SLOW_CFG_INCC_MSK (0x00000007 << ADC_SLOW_CFG_INCC_OFST)
#define ADC_SLOW_CFG_INCC_BPLR_DFFRNTL_PRS_VAL \
((0x0 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_BPLR_IN_COM_VAL \
((0x2 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_TMP_VAL \
((0x3 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL \
((0x4 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_UNPLR_IN_COM_VAL \
((0x6 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
#define ADC_SLOW_CFG_INCC_UNPLR_IN_GND_VAL \
((0x7 << ADC_SLOW_CFG_INCC_OFST) & ADC_SLOW_CFG_INCC_MSK)
/** configuration update */
#define ADC_SLOW_CFG_CFG_OFST (15)
#define ADC_SLOW_CFG_CFG_MSK (0x00000001 << ADC_SLOW_CFG_CFG_OFST)
#define ADC_SLOW_CFG_CFG_NO_UPDATE_VAL \
((0x0 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
#define ADC_SLOW_CFG_CFG_OVRWRTE_VAL \
((0x1 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
/* Slow ADC SPI Value Control register */
#define ADC_SLOW_CTRL_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_SLOW_CTRL_STRT_OFST (0)
#define ADC_SLOW_CTRL_STRT_MSK (0x00000001 << ADC_SLOW_CTRL_STRT_OFST)
#define ADC_SLOW_CTRL_DONE_OFST (1)
#define ADC_SLOW_CTRL_DONE_MSK (0x00000001 << ADC_SLOW_CTRL_DONE_OFST)
/* Clock Measurement base reg */
#define PLL_FREQ_MEASURE_REG (0x44 << MEM_MAP_SHIFT)
/* SPI */
#define SPI_CTRL_REG (0x48 << MEM_MAP_SHIFT)
#define SPI_CTRL_RX_EMPTY_BIT 2
#define SPI_CTRL_CHIPSELECT_BIT 4
#define SPI_CTRL_NBIT_OFST 16
#define SPI_WRITEDATA_REG (0x49 << MEM_MAP_SHIFT)
#define SPI_READDATA_REG (0x4A << MEM_MAP_SHIFT)
/* Power monitor base register */
#define POWER_MONITOR_BASE_REG (0x50 << MEM_MAP_SHIFT)
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
// clang-format on
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