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slsDetectorPackage/slsDetectorServers/slsDetectorServer/src/ALTERA_PLL.c
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Martin MuellerGitHubmuelle_m1maliakal_d
 0837de2a5a CTB frequency rounding, CTB frequency measurement, CTB frequency units (#1423) 
* round CTB clocks to next closest possible value, added freq measurement

* added time for firmware to measrue actual value after frequency change

* add check for backwards compatibility

* change CTB and XCTB clock values to MHz, TODO: units and validation errors

* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?

* do the same for dbit and adcclk

* added tolerance to exptime, fixed test

* update default values in server defs

* added virtual check in Altera_PLL, update testcases

* change python and pyctbgui to accept and return floating point MHz

* update help and comments

* Dev/ctb clocks fix (#1434)

* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)

* incorrect unit typo

* cmd generation and compiles

* default to MHz, removed space between units for consistency with timers, min and max checks for clks

* in python, but need to change the default to Hz again for clean code and intuition

* allow ints, doubles, implicit conversions

* dont allow raw ints, doubles and implicit conversions

* fixed tests

* added operators for Hz in python

* fix test for min clk for xilinx ctb

* fix test

* fix python tests

* fixed xilinx period and default clks

* test fix

* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb

* removing 3 clock cycle code from xilinx as well

* formatting

* loadpattern before 3 clk cycles code

* actualtime and measurement time to be implemented in 100ns already in fw

* fix tests

* pyzmq dependency forthe tests

* fixed pyctbgui for freq

* insert tolerance check again

* also added tolerance check for patwaittime

* formatting

* minor: rounding test

* removed Rep redundant in ToString for freq

* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary

* minor, and binaries

* minor, default clk vals are 0 but set up at detector setup

* get frequency only for that unit

* tolerance process

* missed in previous commit

* some more changes to exptime and validations

* ctb is probably done

* periodleft and delayleft

* fixed xilinx freq conv as well

* fixed m3 bug, binaries

* xilinx: setup also done in stop server so that the clk is not 0

* missed a test marker

* binaries in

* review fixes, simpler validation of timers in ctb and xilinx ctb

* typo fix

* format

* fix tests

---------

Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
2026-05-06 15:52:13 +02:00

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// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "ALTERA_PLL.h"
#include "blackfin.h"
#include "clogger.h"
#include <unistd.h> // usleep
/* Altera PLL DEFINES */
/** PLL Reconfiguration Registers */
// https://www.altera.com/documentation/mcn1424769382940.html
#define ALTERA_PLL_MODE_REG (0x00)
#define ALTERA_PLL_MODE_WT_RQUST_VAL (0)
#define ALTERA_PLL_MODE_PLLNG_MD_VAL (1)
#define ALTERA_PLL_STATUS_REG (0x01)
#define ALTERA_PLL_START_REG (0x02)
#define ALTERA_PLL_N_COUNTER_REG (0x03)
#define ALTERA_PLL_M_COUNTER_REG (0x04)
#define ALTERA_PLL_C_COUNTER_REG (0x05)
#define ALTERA_PLL_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C_COUNTER_LW_CNT_MSK \
(0x000000FF << ALTERA_PLL_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_OFST (8)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_MSK \
(0x000000FF << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST)
/* total_div = lw_cnt + hgh_cnt */
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST (16)
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_MSK \
(0x00000001 << ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is
* bypassed) */
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST (17)
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK \
(0x00000001 << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle =
* (hgh_cnt - 0.5) / total_div */
#define ALTERA_PLL_C_COUNTER_SLCT_OFST (18)
#define ALTERA_PLL_C_COUNTER_SLCT_MSK \
(0x0000001F << ALTERA_PLL_C_COUNTER_SLCT_OFST)
#define ALTERA_PLL_PHASE_SHIFT_REG (0x06)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST (0)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK \
(0x0000FFFF << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_SHIFT_CNT_SELECT_OFST (16)
#define ALTERA_PLL_SHIFT_CNT_SELECT_MSK \
(0x0000001F << ALTERA_PLL_SHIFT_CNT_SELECT_OFST)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C0_VAL \
((0x0 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C1_VAL \
((0x1 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C2_VAL \
((0x2 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C3_VAL \
((0x3 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C4_VAL \
((0x4 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C5_VAL \
((0x5 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C6_VAL \
((0x6 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C7_VAL \
((0x7 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C8_VAL \
((0x8 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C9_VAL \
((0x9 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C10_VAL \
((0x10 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C11_VAL \
((0x11 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C12_VAL \
((0x12 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C13_VAL \
((0x13 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C14_VAL \
((0x14 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C15_VAL \
((0x15 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C16_VAL \
((0x16 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C17_VAL \
((0x17 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_OFST (21)
#define ALTERA_PLL_SHIFT_UP_DOWN_MSK \
(0x00000001 << ALTERA_PLL_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL \
((0x0 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL \
((0x1 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_K_COUNTER_REG (0x07)
#define ALTERA_PLL_BANDWIDTH_REG (0x08)
#define ALTERA_PLL_CHARGEPUMP_REG (0x09)
#define ALTERA_PLL_VCO_DIV_REG (0x1c)
#define ALTERA_PLL_MIF_REG (0x1f)
#define ALTERA_PLL_WAIT_TIME_US (10 * 1000)
// defines from the fpga
uint32_t ALTERA_PLL_Cntrl_Reg = 0x0;
uint32_t ALTERA_PLL_Param_Reg = 0x0;
uint32_t ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = 0x0;
uint32_t ALTERA_PLL_Cntrl_WrPrmtrMask = 0x0;
#if defined(JUNGFRAUD)
uint32_t ALTERA_PLL_Cntrl_DBIT_PLL_WrPrmtrMask = 0x0;
int ALTERA_PLL_Cntrl_DBIT_ClkIndex = 0;
#elif defined(CHIPTESTBOARDD)
uint32_t ALTERA_PLL_FREQ_MEASURE_BASE = 0x0;
#endif
uint32_t ALTERA_PLL_Cntrl_PLLRstMask = 0x0;
uint32_t ALTERA_PLL_Cntrl_AddrMask = 0x0;
int ALTERA_PLL_Cntrl_AddrOfst = 0;
#if defined(JUNGFRAUD)
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
ALTERA_PLL_Cntrl_WrPrmtrMask = wpmsk;
ALTERA_PLL_Cntrl_PLLRstMask = prmsk;
ALTERA_PLL_Cntrl_AddrMask = amsk;
ALTERA_PLL_Cntrl_AddrOfst = aofst;
ALTERA_PLL_Cntrl_DBIT_PLL_WrPrmtrMask = wd2msk;
ALTERA_PLL_Cntrl_DBIT_ClkIndex = clk2Index;
}
#elif defined(CHIPTESTBOARDD)
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t freqreg) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
ALTERA_PLL_Cntrl_WrPrmtrMask = wpmsk;
ALTERA_PLL_Cntrl_PLLRstMask = prmsk;
ALTERA_PLL_Cntrl_AddrMask = amsk;
ALTERA_PLL_Cntrl_AddrOfst = aofst;
ALTERA_PLL_FREQ_MEASURE_BASE = freqreg;
}
#else
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
ALTERA_PLL_Cntrl_WrPrmtrMask = wpmsk;
ALTERA_PLL_Cntrl_PLLRstMask = prmsk;
ALTERA_PLL_Cntrl_AddrMask = amsk;
ALTERA_PLL_Cntrl_AddrOfst = aofst;
}
#endif
void ALTERA_PLL_ResetPLL() {
LOG(logINFO, ("Resetting only PLL\n"));
LOG(logDEBUG2, ("pllrstmsk:0x%x\n", ALTERA_PLL_Cntrl_PLLRstMask));
bus_w(ALTERA_PLL_Cntrl_Reg,
bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("Set PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg,
bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("UnSet PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
}
void ALTERA_PLL_ResetPLLAndReconfiguration() {
LOG(logINFO, ("Resetting PLL and Reconfiguration\n"));
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) |
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask |
ALTERA_PLL_Cntrl_PLLRstMask);
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) &
~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask &
~ALTERA_PLL_Cntrl_PLLRstMask);
}
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
int useSecondWRMask) {
LOG(logDEBUG1,
("Setting PLL Reconfig Reg, reg:0x%x, val:0x%x, useSecondWRMask:%d)\n",
reg, val, useSecondWRMask));
uint32_t wrmask = ALTERA_PLL_Cntrl_WrPrmtrMask;
#if defined(JUNGFRAUD)
if (useSecondWRMask) {
wrmask = ALTERA_PLL_Cntrl_DBIT_PLL_WrPrmtrMask;
}
#endif
LOG(logDEBUG2,
("pllparamreg:0x%x pllcontrolreg:0x%x addrofst:%d addrmsk:0x%x "
"wrmask:0x%x\n",
ALTERA_PLL_Param_Reg, ALTERA_PLL_Cntrl_Reg, ALTERA_PLL_Cntrl_AddrOfst,
ALTERA_PLL_Cntrl_AddrMask, wrmask));
// set parameter
bus_w(ALTERA_PLL_Param_Reg, val);
LOG(logDEBUG2, ("Set Parameter: ALTERA_PLL_Param_Reg:0x%x\n",
bus_r(ALTERA_PLL_Param_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
// set address
bus_w(ALTERA_PLL_Cntrl_Reg,
(reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask);
LOG(logDEBUG2, ("Set Address: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
// write parameter
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | wrmask);
LOG(logDEBUG2, ("Set WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~wrmask);
LOG(logDEBUG2, ("Unset WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
}
void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
LOG(logINFO, ("\tWriting PLL Phase Shift\n"));
uint32_t value = (((phase << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST) &
ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK) |
((clkIndex << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) &
ALTERA_PLL_SHIFT_CNT_SELECT_MSK) |
(pos ? ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL
: ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL));
LOG(logDEBUG1, ("C%d phase word:0x%08x\n", clkIndex, value));
int useSecondWR = 0;
#if defined(JUNGFRAUD)
if (clkIndex == ALTERA_PLL_Cntrl_DBIT_ClkIndex) {
useSecondWR = 1;
}
#endif
// write phase shift
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value,
useSecondWR);
}
void ALTERA_PLL_SetModePolling() {
LOG(logINFO, ("\tSetting Polling Mode\n"));
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG,
ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
}
int ALTERA_PLL_SetOutputFrequency(int clkIndex, int pllVCOFreqHz, int value) {
LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dHz)\n",
clkIndex, value, pllVCOFreqHz));
// calculate output frequency, round to next closest integer division
uint32_t total_div = (pllVCOFreqHz + value / 2) / value;
// assume 50% duty cycle
uint32_t low_count = total_div / 2;
uint32_t high_count = low_count;
uint32_t odd_division = 0;
// odd division
if (total_div > (2 * low_count)) {
++high_count;
odd_division = 1;
}
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count,
high_count, odd_division));
// command to set output frequency
uint32_t val = (((low_count << ALTERA_PLL_C_COUNTER_LW_CNT_OFST) &
ALTERA_PLL_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST) &
ALTERA_PLL_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST) &
ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK) |
((clkIndex << ALTERA_PLL_C_COUNTER_SLCT_OFST) &
ALTERA_PLL_C_COUNTER_SLCT_MSK));
LOG(logDEBUG1, ("C%d word:0x%08x\n", clkIndex, val));
// write frequency (post-scale output counter C)
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val, 0);
// reset required to keep the phase (must reconfigure adcs again after this
// as adc clock is stopped temporarily when resetting pll)
ALTERA_PLL_ResetPLL();
/*double temp = ((double)pllVCOFreqHz / (double)(low_count + high_count));
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;
}
return (int)temp;
*/
#if defined(CHIPTESTBOARDD) && !defined(VIRTUAL)
// wait for firmware to measure the actual frequency
usleep(2 * 1000 * 1000);
value = ALTERA_PLL_getFrequency(clkIndex);
LOG(logDEBUG1, ("Frequency is %d\n", value));
#endif
return value;
}
#if defined(CHIPTESTBOARDD)
uint32_t ALTERA_PLL_getFrequency(uint32_t clk_index) {
return bus_r(ALTERA_PLL_FREQ_MEASURE_BASE + clk_index * 2);
}
#endif
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