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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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134 lines
3.6 KiB
C
134 lines
3.6 KiB
C
// SPDX-License-Identifier: LGPL-3.0-or-other
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// Copyright (C) 2021 Contributors to the SLS Detector Package
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#pragma once
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#include <inttypes.h>
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#include <sys/types.h>
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/** enable support for ARDY signal on interface to FPGA
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* needed to properly translate avalon_mm_waitrequest in the CTB firmware
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* https://www.analog.com/media/en/dsp-documentation/processor-manuals/bf537_hwr_Rev3.2.pdf
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* page 274
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* */
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#define BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_OFST (0)
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#define BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_MSK \
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(1 << BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_OFST)
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#define BFIN_EBIU_AMBCTL1_B2_ARDY_POL_OFST (1)
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#define BFIN_EBIU_AMBCTL1_B2_ARDY_POL_MSK \
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(1 << BFIN_EBIU_AMBCTL1_B2_ARDY_POL_OFST)
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#define BFIN_AMC_ACCESS_EXTENSION_ENA_VAL \
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(BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_MSK | BFIN_EBIU_AMBCTL1_B2_ARDY_POL_MSK)
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#define BFIN_AMC_ACCESS_EXTENSION_FNAME \
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"/sys/kernel/debug/blackfin/ebiu_amc/EBIU_AMBCTL1"
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/**
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* Write into a 16 bit register
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* @param offset address offset
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* @param data 16 bit data
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*/
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void bus_w16(u_int32_t offset, u_int16_t data);
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/**
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* Read from a 16 bit register
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* @param offset address offset
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* @retuns 16 bit data read
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*/
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u_int16_t bus_r16(u_int32_t offset);
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/**
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* Write into a 32 bit register
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* @param offset address offset
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* @param data 32 bit data
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*/
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void bus_w(u_int32_t offset, u_int32_t data);
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/**
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* Read from a 32 bit register
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* @param offset address offset
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* @retuns 32 bit data read
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*/
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u_int32_t bus_r(u_int32_t offset);
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/**
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* Read from a 64 bit register
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* @param aLSB LSB offset address
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* @param aMSB MSB offset address
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* @returns 64 bit data read
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*/
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int64_t get64BitReg(int aLSB, int aMSB);
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/**
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* Write into a 64 bit register
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* @param value 64 bit data
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* @param aLSB LSB offset address
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* @param aMSB MSB offset address
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* @returns 64 bit data read
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*/
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int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
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/**
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* Read unsigned 64 bit from a 64 bit register
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* @param aLSB LSB offset address
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* @param aMSB MSB offset address
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* @returns unsigned 64 bit data read
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*/
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uint64_t getU64BitReg(int aLSB, int aMSB);
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/**
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* Write unsigned 64 bit into a 64 bit register
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* @param value unsigned 64 bit data
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* @param aLSB LSB offset address
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* @param aMSB MSB offset address
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*/
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void setU64BitReg(uint64_t value, int aLSB, int aMSB);
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/**
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* Read from a 32 bit register (literal register value provided by client)
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* @param offset address offset
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* @retuns 32 bit data read
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*/
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u_int32_t readRegister(u_int32_t offset);
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/**
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* Write into a 32 bit register (literal register value provided by client)
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* @param offset address offset
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* @param data 32 bit data
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*/
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void writeRegister(u_int32_t offset, u_int32_t data);
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/**
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* Read from a 16 bit register (literal register value provided by client)
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* @param offset address offset
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* @retuns 16 bit data read
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*/
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u_int32_t readRegister16(u_int32_t offset);
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/**
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* Write into a 16 bit register (literal register value provided by client)
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* @param offset address offset
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* @param data 16 bit data
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*/
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void writeRegister16(u_int32_t offset, u_int32_t data);
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/**
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* Get base address for memory copy
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*/
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uint32_t *Blackfin_getBaseAddress();
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/**
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* Map FPGA
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*/
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int mapCSP0(void);
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/**
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* Prepare the core cycle counter used by usleep_bf (called from mapCSP0)
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*/
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int initCycleCounter(void);
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/**
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* busy-wait for usecs on the core cycle counter
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* @returns 0, or -1 without sleeping if the wait does not fit the 32-bit
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* cycle count (about 8 s at 525 MHz)
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*/
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int usleep_bf(uint32_t us);
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