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slsDetectorPackage/slsDetectorServers/eigerDetectorServer/xparameters.h
Dhanya Thattil e92578f89d formatting
2025-01-31 12:27:35 +01:00

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// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx
compilation, this file should be replaced with updated values
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
*/
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 12.4 EDK_MS4.81d
* DO NOT EDIT.
*
* Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
*
* Description: Driver parameters
*
*******************************************************************/
#define STDIN_BASEADDRESS 0xC0000000
#define STDOUT_BASEADDRESS 0xC0000000
/******************************************************************/
/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
/* Definitions for peripheral PLB_BRAM_10G */
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR
/* Definitions for peripheral PLB_BRAM_TEMAC */
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
/* Definitions for peripheral PLB_GPIO_SYS */
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
// data streaming register
// clang-format off
#define XPAR_GPIO_P15_STREAMING_REG 0x01e0
#define XPAR_GPIO_FRAME_PKT_ENBL_OFST (0)
#define XPAR_GPIO_FRAME_PKT_ENBL_MSK (0x00000001 << XPAR_GPIO_FRAME_PKT_ENBL_OFST)
#define XPAR_GPIO_RGHT_STRM_DSBL_OFST (1)
#define XPAR_GPIO_RGHT_STRM_DSBL_MSK (0x00000001 << XPAR_GPIO_RGHT_STRM_DSBL_OFST)
#define XPAR_GPIO_LFT_STRM_DSBL_OFST (2)
#define XPAR_GPIO_LFT_STRM_DSBL_MSK (0x00000001 << XPAR_GPIO_LFT_STRM_DSBL_OFST)
// clang-format on
/** Command Generator */
#define XPAR_CMD_GENERATOR 0xC5000000
/** Version Numbers */
#define XPAR_VERSION 0xc6000000
/* Definitions for peripheral PLB_GPIO_TEST */
#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
// udp header (set frame number)
#define UDP_HEADER_FRAME_NUMBER_LSB_OFST (0x0140)
#define UDP_HEADER_FRAME_NUMBER_MSB_OFST (0x0160)
/* Definitions for packet, frame and delay down counters */
#define XPAR_COUNTER_BASEADDR 0xD1020000
#define XPAR_COUNTER_HIGHADDR 0xD102FFFF
// udp header (get frame number)
#define UDP_HEADER_GET_FNUM_1G_LEFT_LSB_OFST (0x0004)
#define UDP_HEADER_GET_FNUM_1G_LEFT_MSB_OFST (0x0024)
#define UDP_HEADER_GET_FNUM_1G_RIGHT_LSB_OFST (0x0044)
#define UDP_HEADER_GET_FNUM_1G_RIGHT_MSB_OFST (0x0064)
#define UDP_HEADER_GET_FNUM_10G_LEFT_LSB_OFST (0x0084)
#define UDP_HEADER_GET_FNUM_10G_LEFT_MSB_OFST (0x00A4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_LSB_OFST (0x00C4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_MSB_OFST (0x00E4)
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
/* Definitions for a new memory */
// #define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
/* Definitions for peripheral PPC_SRAM */
#define XPAR_PPC_SRAM_BASEADDR 0x00000000
#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
/******************************************************************/
/* Definitions for peripheral PFLASH */
#define XPAR_PFLASH_NUM_BANKS_MEM 1
/******************************************************************/
/* Definitions for peripheral PFLASH */
#define XPAR_PFLASH_MEM0_BASEADDR 0xE0000000
#define XPAR_PFLASH_MEM0_HIGHADDR 0xE3FFFFFF
/******************************************************************/
/* Canonical definitions for peripheral PFLASH */
#define XPAR_EMC_0_NUM_BANKS_MEM 1
#define XPAR_EMC_0_MEM0_BASEADDR 0xE0000000
#define XPAR_EMC_0_MEM0_HIGHADDR 0xE3FFFFFF
/******************************************************************/
/* Definitions for driver PLB_SHT1X_IF */
#define XPAR_PLB_SHT1X_IF_NUM_INSTANCES 2
/* Definitions for peripheral PLB_SHT1X_IF_CH1 */
#define XPAR_PLB_SHT1X_IF_CH1_DEVICE_ID 0
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
/******************************************************************/
/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1
/* Definitions for peripheral RS232 */
#define XPAR_RS232_BASEADDR 0xC0000000
#define XPAR_RS232_HIGHADDR 0xC000FFFF
#define XPAR_RS232_DEVICE_ID 0
#define XPAR_RS232_BAUDRATE 115200
#define XPAR_RS232_USE_PARITY 0
#define XPAR_RS232_ODD_PARITY 0
#define XPAR_RS232_DATA_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral RS232 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
#define XPAR_UARTLITE_0_HIGHADDR 0xC000FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN 1
/******************************************************************/
/* Definitions for driver SPI */
#define XPAR_XSPI_NUM_INSTANCES 2
/* Definitions for peripheral SPI_FLASH */
#define XPAR_SPI_FLASH_DEVICE_ID 0
#define XPAR_SPI_FLASH_BASEADDR 0xD2000000
#define XPAR_SPI_FLASH_HIGHADDR 0xD200FFFF
#define XPAR_SPI_FLASH_FIFO_EXIST 1
#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
/* Definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
#define XPAR_XPS_SPI_FEB_CFG_HIGHADDR 0xD201FFFF
#define XPAR_XPS_SPI_FEB_CFG_FIFO_EXIST 1
#define XPAR_XPS_SPI_FEB_CFG_SPI_SLAVE_ONLY 0
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral SPI_FLASH */
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
#define XPAR_SPI_0_BASEADDR 0xD2000000
#define XPAR_SPI_0_HIGHADDR 0xD200FFFF
#define XPAR_SPI_0_FIFO_EXIST 1
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0
#define XPAR_SPI_0_NUM_SS_BITS 1
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
#define XPAR_SPI_1_BASEADDR 0xD2010000
#define XPAR_SPI_1_HIGHADDR 0xD201FFFF
#define XPAR_SPI_1_FIFO_EXIST 1
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0
#define XPAR_SPI_1_NUM_SS_BITS 2
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Definitions for driver LLTEMAC */
#define XPAR_XLLTEMAC_NUM_INSTANCES 1
/* Definitions for peripheral TEMAC_INST Channel 0 */
#define XPAR_TEMAC_INST_CHAN_0_DEVICE_ID 0
#define XPAR_TEMAC_INST_CHAN_0_BASEADDR 0xC3000000
#define XPAR_TEMAC_INST_CHAN_0_HIGHADDR 0xC30FFFFF
#define XPAR_TEMAC_INST_CHAN_0_TXCSUM 0
#define XPAR_TEMAC_INST_CHAN_0_RXCSUM 0
#define XPAR_TEMAC_INST_CHAN_0_PHY_TYPE 4
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TRAN 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TRAN 0
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TAG 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TAG 0
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_STRP 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_STRP 0
#define XPAR_TEMAC_INST_CHAN_0_MCAST_EXTEND 0
/* Canonical definitions for peripheral TEMAC_INST Channel 0 */
#define XPAR_LLTEMAC_0_DEVICE_ID 0
#define XPAR_LLTEMAC_0_BASEADDR 0xC3000000
#define XPAR_LLTEMAC_0_HIGHADDR 0xC30FFFFF
#define XPAR_LLTEMAC_0_TXCSUM 0
#define XPAR_LLTEMAC_0_RXCSUM 0
#define XPAR_LLTEMAC_0_PHY_TYPE 4
#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
#define XPAR_LLTEMAC_0_INTR 1
/* LocalLink TYPE Enumerations */
#define XPAR_LL_FIFO 1
#define XPAR_LL_DMA 2
/* Canonical LocalLink parameters for TEMAC_INST */
/******************************************************************/
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral XPS_INTC_PPC440 */
#define XPAR_XPS_INTC_PPC440_DEVICE_ID 0
#define XPAR_XPS_INTC_PPC440_BASEADDR 0xC1000000
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
#define XPAR_INTC_SINGLE_HIGHADDR 0xC100FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
#define XPAR_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_MASK 0X000001
#define XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR 0
#define XPAR_TEMAC_INST_TEMACINTC0_IRPT_MASK 0X000002
#define XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR 1
#define XPAR_XPS_TIMER_PPC440_INTERRUPT_MASK 0X000004
#define XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR 2
#define XPAR_SPI_FLASH_IP2INTC_IRPT_MASK 0X000008
#define XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR 3
#define XPAR_RS232_INTERRUPT_MASK 0X000010
#define XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR 4
/******************************************************************/
/* Canonical definitions for peripheral XPS_INTC_PPC440 */
#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0xC1000000
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
#define XPAR_INTC_0_LLFIFO_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID \
XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID \
XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
/******************************************************************/
/* Definitions for driver LLFIFO */
#define XPAR_XLLFIFO_NUM_INSTANCES 1
/* Definitions for peripheral XPS_LL_FIFO_TEMAC */
#define XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID 0
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
#define XPAR_LLFIFO_0_DEVICE_ID XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
/******************************************************************/
/* Definitions for driver SYSMON */
#define XPAR_XSYSMON_NUM_INSTANCES 1
/* Definitions for peripheral XPS_SYSMON_ADC_PPC440 */
#define XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID 0
#define XPAR_XPS_SYSMON_ADC_PPC440_BASEADDR 0xD0010000
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
/******************************************************************/
/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
#define XPAR_SYSMON_0_INCLUDE_INTR 1
/******************************************************************/
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1
/* Definitions for peripheral XPS_TIMER_PPC440 */
#define XPAR_XPS_TIMER_PPC440_DEVICE_ID 0
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
/******************************************************************/
/* Definitions for bus frequencies */
#define XPAR_CPU_PPC440_MPLB_FREQ_HZ 100000000
/******************************************************************/
/* Canonical definitions for bus frequencies */
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
/******************************************************************/
#define XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_PPC440_VIRTEX5_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_CPU_PPC440_IDCR_BASEADDR 0x00000000
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_PPC440_VIRTEX5_ID 0
#define XPAR_PPC440_VIRTEX5_PIR 0b1111
#define XPAR_PPC440_VIRTEX5_ENDIAN_RESET 0
#define XPAR_PPC440_VIRTEX5_USER_RESET 0b0000
#define XPAR_PPC440_VIRTEX5_INTERCONNECT_IMASK 0xffffffff
#define XPAR_PPC440_VIRTEX5_ICU_RD_FETCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_ICU_RD_SPEC_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_ICU_RD_TOUCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_LD_CACHE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_NONCACHE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_TOUCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_URGENT_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_FLUSH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_STORE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_URGENT_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA0_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA1_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA2_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA3_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_IDCR_BASEADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_IDCR_HIGHADDR 0x000000FF
#define XPAR_PPC440_VIRTEX5_APU_CONTROL 0b00010000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_0 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_1 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_2 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_3 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_4 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_5 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_6 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_7 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_8 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_9 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_10 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_11 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_12 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_13 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_14 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_15 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_BASE 0x00000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_HIGH 0X01FFFFFF
#define XPAR_PPC440_VIRTEX5_PPC440MC_ROW_CONFLICT_MASK 0x00000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_BANK_CONFLICT_MASK 0x00000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_CONTROL 0X8140008F
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_ICU 4
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUW 3
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUR 2
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB1 0
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB0 1
#define XPAR_PPC440_VIRTEX5_PPC440MC_ARB_MODE 0
#define XPAR_PPC440_VIRTEX5_PPC440MC_MAX_BURST 8
#define XPAR_PPC440_VIRTEX5_MPLB_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_MPLB_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_MPLB_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_MPLB_COUNTER 0x00000500
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_ICU 4
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUW 3
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUR 2
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB1 0
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB0 1
#define XPAR_PPC440_VIRTEX5_MPLB_ARB_MODE 0
#define XPAR_PPC440_VIRTEX5_MPLB_SYNC_TATTRIBUTE 0
#define XPAR_PPC440_VIRTEX5_MPLB_MAX_BURST 8
#define XPAR_PPC440_VIRTEX5_MPLB_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_MPLB_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_POST_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_P2P 0
#define XPAR_PPC440_VIRTEX5_MPLB_WDOG_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB0_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_SPLB0_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB0_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB0_SUPPORT_BURSTS 1
#define XPAR_PPC440_VIRTEX5_SPLB0_USE_MPLB_ADDR 0
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MPLB_ADDR_RNG 0
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MASTERS 1
#define XPAR_PPC440_VIRTEX5_SPLB0_MID_WIDTH 1
#define XPAR_PPC440_VIRTEX5_SPLB0_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_SPLB0_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB0_PROPAGATE_MIRQ 0
#define XPAR_PPC440_VIRTEX5_SPLB0_P2P -1
#define XPAR_PPC440_VIRTEX5_SPLB1_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_SPLB1_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB1_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB1_SUPPORT_BURSTS 1
#define XPAR_PPC440_VIRTEX5_SPLB1_USE_MPLB_ADDR 0
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MPLB_ADDR_RNG 0
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MASTERS 1
#define XPAR_PPC440_VIRTEX5_SPLB1_MID_WIDTH 1
#define XPAR_PPC440_VIRTEX5_SPLB1_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_SPLB1_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB1_PROPAGATE_MIRQ 0
#define XPAR_PPC440_VIRTEX5_SPLB1_P2P -1
#define XPAR_PPC440_VIRTEX5_NUM_DMA 0
#define XPAR_PPC440_VIRTEX5_DMA0_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA0_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA0_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA0_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA0_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA1_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA1_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA1_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA1_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA1_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA2_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA2_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA2_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA2_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA2_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA3_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA3_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA3_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA3_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA3_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DCR_AUTOLOCK_ENABLE 1
#define XPAR_PPC440_VIRTEX5_PPCDM_ASYNCMODE 0
#define XPAR_PPC440_VIRTEX5_PPCDS_ASYNCMODE 0
#define XPAR_PPC440_VIRTEX5_GENERATE_PLB_TIMESPECS 1
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
/******************************************************************/
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