Dhanya Thattil 8ada7b6e37

802: jungfrau HW 1.0: adc output clock phase to 120 (#951) ...

* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* formatting

2024-08-22 14:27:16 +02:00

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ctbDetectorServerv8.0.0

updated versioning

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eigerDetectorServerv8.0.0

updated versioning

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gotthard2DetectorServerv8.0.0

updated versioning

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gotthardDetectorServerv8.0.0

updated versioning

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jungfrauDetectorServerv8.0.2

802: jungfrau HW 1.0: adc output clock phase to 120 (#951)

2024-08-22 14:27:16 +02:00

moenchDetectorServerv8.0.2

moench server name and version renaming

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mythen3DetectorServerv8.0.2

8.0.2.rc: m3 clkdiv0 20 (#923)

2024-07-25 17:17:20 +02:00