//#define TESTADC #define TESTADC1 //#define TIMEDBG #include "server_defs.h" #include "firmware_funcs.h" #include "mcb_funcs.h" #include "registers_m.h" #include "gitInfoJungfrau.h" //#define VERBOSE //#define VERYVERBOSE #include #include #include #include #include #include /* exit() */ #include /* memset(), memcpy() */ #include /* uname() */ #include #include /* socket(), bind(), listen(), accept() */ #include #include #include #include #include /* fork(), write(), close() */ #include #include #include #include #include #include #include #include #include #include #include #include #include extern enum detectorType myDetectorType; typedef struct ip_header_struct { u_int16_t ip_len; u_int8_t ip_tos; u_int8_t ip_ihl:4 ,ip_ver:4; u_int16_t ip_offset:13,ip_flag:3; u_int16_t ip_ident; u_int16_t ip_chksum; u_int8_t ip_protocol; u_int8_t ip_ttl; u_int32_t ip_sourceip; u_int32_t ip_destip; } ip_header; u_int32_t CSP0BASE; int highvoltage = 0; FILE *debugfp, *datafp; int fr; int wait_time; int *fifocntrl; const int nModY=1; int nModBoard; int nModX=NMAXMOD; int dynamicRange=16; int nSamples=1; size_t dataBytes=NMAXMOD*NCHIP*NCHAN*2; int storeInRAM=0; int ROI_flag=0; int adcConfigured=-1; int ram_size=0; int64_t totalTime=1; u_int32_t progressMask=0; int phase_shift=0;//DEFAULT_PHASE_SHIFT; int ipPacketSize=DEFAULT_IP_PACKETSIZE; int udpPacketSize=DEFAULT_UDP_PACKETSIZE; int clockdivider_exptime = 40; int clockdivider_fc = 20; /* #ifndef NEW_PLL_RECONFIG u_int32_t clkDivider[2]={32,16}; #else u_int32_t clkDivider[2]={40,20}; #endif */ int32_t clkPhase[2]={0,0}; u_int32_t adcDisableMask=0; int ififostart, ififostop, ififostep, ififo; int masterMode=NO_MASTER, syncMode=NO_SYNCHRONIZATION, timingMode=AUTO_TIMING; enum externalSignalFlag signals[4]={EXT_SIG_OFF, EXT_SIG_OFF, EXT_SIG_OFF, EXT_SIG_OFF}; char mtdvalue[10]; int mapCSP0(void) { printf("Mapping memory\n"); #ifndef VIRTUAL int fd; fd = open("/dev/mem", O_RDWR | O_SYNC, 0); if (fd == -1) { printf("\nCan't find /dev/mem!\n"); return FAIL; } //printf("/dev/mem opened\n"); CSP0BASE = (u_int32_t)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, CSP0); if (CSP0BASE == (u_int32_t)MAP_FAILED) { printf("\nCan't map memmory area!!\n"); return FAIL; } //printf("CSP0 mapped\n"); #endif #ifdef VIRTUAL CSP0BASE = malloc(MEM_SIZE); printf("memory allocated\n"); #endif //printf("CSPObase is 0x%08x \n",CSP0BASE); printf("CSPOBASE mapped from %08x to %08x\n",CSP0BASE,CSP0BASE+MEM_SIZE); printf("statusreg=%08x\n",bus_r(STATUS_REG)); return OK; } void defineGPIOpins(){ //define the gpio pins system("echo 7 > /sys/class/gpio/export"); system("echo 9 > /sys/class/gpio/export"); //define their direction system("echo in > /sys/class/gpio/gpio7/direction"); system("echo out > /sys/class/gpio/gpio9/direction"); } void resetFPGA(){ cprintf(BLUE,"\n*** Reseting FPGA ***\n"); FPGAdontTouchFlash(); FPGATouchFlash(); usleep(250*1000); } void FPGAdontTouchFlash(){ //tell FPGA to not touch flash system("echo 0 > /sys/class/gpio/gpio9/value"); //usleep(100*1000); } void FPGATouchFlash(){ //tell FPGA to touch flash to program itself system("echo 1 > /sys/class/gpio/gpio9/value"); } int powerChip (int on){ if(on != -1){ if(on){ printf("\nPowering on the chip\n"); bus_w(POWER_ON_REG,0x1); } else{ printf("\nPowering off the chip\n"); bus_w(POWER_ON_REG,0x0); } } return bus_r(POWER_ON_REG); } void initializeDetector(){ printf("Initializing Detector\n"); //initial test if ( (testFpga() == FAIL) || (testBus() == FAIL) || (checkType() == FAIL)) { /*Check with Carlos if type check required */ cprintf(BG_RED, "Dangerous to continue. Goodbye!\n"); exit(-1); } printVersions(); printf("Resetting PLL\n"); resetPLL(); bus_w16(CONTROL_REG, SYNC_RESET); bus_w16(CONTROL_REG, 0); bus_w16(CONTROL_REG, GB10_RESET_BIT); bus_w16(CONTROL_REG, 0); //allocating module structure for the detector in the server #ifdef MCB_FUNCS initDetector(); #endif /*some registers set, which is in common with jungfrau, please check */ prepareADC(); /*some registers set, which is in common with jungfrau, please check */ /*initDac(0); initDac(8); Carlos later need to initialize dac 0 and dac8 doesnt exist */ //initializes the two dacs //set dacs printf("Setting Default Dac values\n"); enum dacNames{VB_COMP,VDD_PROT,VIN_COM,VREF_PRECH,VB_PIXBUF,VB_DS,VREF_DS,VREF_COMP}; int retval = -1; int dacvalues[8][2]={ {VB_COMP, 1220}, {VDD_PROT, 3000}, {VIN_COM, 1053}, {VREF_PRECH,1450}, {VB_PIXBUF, 750}, {VB_DS, 1000}, {VREF_DS, 480}, {VREF_COMP, 420}, }; for(i=0;i<8;++i){ retval=setDac(dacvalues[i][0], dacvalues[i][1]); if(retval!=dacvalues[i][1]) printf("Error: Setting dac %d failed, wrote %d, read %d\n",dacvalues[i][0],dacvalues[i][1],retval); } //done from config file //printf("\nPowering on the chip\n"); //bus_w(POWER_ON_REG,0x1); /* Only once */ bus_w(CONFGAIN_REG,0x0); printf("Resetting ADC\n"); writeADC(ADCREG1,0x3); writeADC(ADCREG1,0x0); writeADC(ADCREG2,0x40); writeADC(ADCREG3,0xf); writeADC(ADCREG4,0x3f); printf("Configuring Vrefs\n"); writeADC(ADCREG_VREFS,0x2); printf("Setting ADC Inversion\n");// (by trial and error) bus_w(ADC_INVERSION_REG,0x453b2a9c); adcPipeline(HALFSPEED_ADC_PIPELINE); dbitPipeline(HALFSPEED_DBIT_PIPELINE); adcPhase(HALFSPEED_ADC_PHASE); //set adc_clock_phase in unit of 1/(52) clock period (by trial and error) printf("Reset mem machine fifos\n"); bus_w(MEM_MACHINE_FIFOS_REG,0x4000); bus_w(MEM_MACHINE_FIFOS_REG,0x0); printf("Reset run control\n"); bus_w(MEM_MACHINE_FIFOS_REG,0x0400); bus_w(MEM_MACHINE_FIFOS_REG,0x0); initSpeedConfGain(HALFSPEED_CONF); setSettings(DYNAMICGAIN,-1); //Initialization of acquistion parameters setFrames(1*1000*1000); setTrains(-1); setExposureTime(10*1000); setPeriod(2*1000*1000); setDelay(0); setGates(0); initHighVoltage(0); /* ask Carlos Set it to a value so server is always updated in a get*/ setTiming(GET_EXTERNAL_COMMUNICATION_MODE); setMaster(GET_MASTER); setSynchronization(GET_SYNCHRONIZATION_MODE); } int checkType() { volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST); if (type != JUNGFRAU){ cprintf(BG_RED,"This is not a Jungfrau Server (read %d, expected %d)\n",type, JUNGFRAU); return FAIL; } return OK; } void printVersions() { cprintf(BLUE,"\n\n" "********************************************************\n" "*********************Jungfrau Server********************\n" "********************************************************\n\n" "Firmware Version:\t 0x%llx\n" "Software Version:\t 0x%llx\n" //"F/w-S/w API Version:\t\t %lld\n" //"Required Firmware Version:\t %d\n" "********************************************************\n", (long long unsigned int)getId(DETECTOR_FIRMWARE_VERSION), (long long unsigned int)getId(DETECTOR_SOFTWARE_VERSION) //,(long long unsigned int)getId(SOFTWARE_FIRMWARE_API_VERSION) //REQUIRED_FIRMWARE_VERSION); ); } u_int16_t bus_r16(u_int32_t offset){ volatile u_int16_t *ptr1; ptr1=(u_int16_t*)(CSP0BASE+offset*2); return *ptr1; } u_int16_t bus_w16(u_int32_t offset, u_int16_t data) { volatile u_int16_t *ptr1; ptr1=(u_int16_t*)(CSP0BASE+offset*2); *ptr1=data; return OK; } /** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG */ u_int16_t ram_w16(u_int32_t ramType, int adc, int adcCh, int Ch, u_int16_t data) { unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); // printf("Writing to addr:%x\n",adr); return bus_w16(adr,data); } /** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG */ u_int16_t ram_r16(u_int32_t ramType, int adc, int adcCh, int Ch){ unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); // printf("Reading from addr:%x\n",adr); return bus_r16(adr); } u_int32_t bus_w(u_int32_t offset, u_int32_t data) { volatile u_int32_t *ptr1; ptr1=(u_int32_t*)(CSP0BASE+offset*2); *ptr1=data; return OK; } u_int32_t bus_r(u_int32_t offset) { volatile u_int32_t *ptr1; ptr1=(u_int32_t*)(CSP0BASE+offset*2); return *ptr1; } int setPhaseShiftOnce(){ u_int32_t addr, reg; int i; addr=MULTI_PURPOSE_REG; reg=bus_r(addr); #ifdef VERBOSE printf("Multipurpose reg:%x\n",reg); #endif //Checking if it is power on(negative number) // if(((reg&0xFFFF0000)>>16)>0){ //bus_w(addr,0x0); //clear the reg if(reg==0){ printf("\nImplementing phase shift of %d\n",phase_shift); for (i=1;i2*l) { h=l+1; odd=1; } printf("Counter %d: Low is %d, High is %d\n",i, l,h); val= (i<<18)| (odd<<17) | l | (h<<8); printf("Counter %d, val: %08x\n", i, val); setPllReconfigReg(PLL_C_COUNTER_REG, val,0); // usleep(20); //change sync at the same time as if (i>0) { val= (2<<18)| (odd<<17) | l | (h<<8); printf("Counter %d, val: %08x\n", i, val); setPllReconfigReg(PLL_C_COUNTER_REG, val,0); } } else { // if (mode==1) { // } else { printf("phase in %d\n",clkPhase[1]); if (clkPhase[1]>0) { inv=0; phase=clkPhase[1]; } else { inv=1; phase=-1*clkPhase[1]; } printf("phase out %d %08x\n",phase,phase); if (inv) { val=phase | (1<<16);// | (inv<<21); printf("**************** phase word %08x\n",val); // printf("Phase, val: %08x\n", val); setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0 } else { val=phase ;// | (inv<<21); printf("**************** phase word %08x\n",val); // printf("Phase, val: %08x\n", val); setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0 #ifndef NEW_PLL_RECONFIG printf("Start reconfig\n"); setPllReconfigReg(PLL_START_REG, 1,0); // bus_w(PLL_CNTRL_REG, 0); printf("Status register\n"); getPllReconfigReg(PLL_STATUS_REG,0); // sleep(1); printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,1,0); // usleep(10000); #endif printf("**************** phase word %08x\n",val); val=phase | (2<<16);// | (inv<<21); // printf("Phase, val: %08x\n", val); setPllReconfigReg(PLL_PHASE_SHIFT_REG,val,0); //shifts counter 0 } } #ifndef NEW_PLL_RECONFIG printf("Start reconfig\n"); setPllReconfigReg(PLL_START_REG, 1,0); // bus_w(PLL_CNTRL_REG, 0); printf("Status register\n"); getPllReconfigReg(PLL_STATUS_REG,0); // sleep(1); #endif // printf("PLL mode\n"); setPllReconfigReg(PLL_MODE_REG,0,0); usleep(10000); if (i<2) { printf("reset pll\n"); bus_w(PLL_CNTRL_REG,((1<65535 || st<-65535) return clkPhase[0]; #ifdef NEW_PLL_RECONFIG printf("reset pll\n"); bus_w(PLL_CNTRL_REG,((1<=0){ printf("Setting ADC Pipeline to 0x%x\n",d); bus_w(ADC_PIPELINE_REG, d); } return bus_r(ADC_PIPELINE_REG); } u_int32_t dbitPipeline(int d){ if (d>=0){ printf("Setting DBIT Pipeline to 0x%x\n",d); bus_w(DBIT_PIPELINE_REG, d); } return bus_r(DBIT_PIPELINE_REG); } u_int32_t setSetLength(int d) { return 0; } u_int32_t getSetLength() { return 0; } u_int32_t setOversampling(int d) { if (d>=0 && d<=255) bus_w(OVERSAMPLING_REG, d); return bus_r(OVERSAMPLING_REG); } u_int32_t setWaitStates(int d1) { return 0; } u_int32_t getWaitStates() { return 0; } u_int32_t setTotClockDivider(int d) { return 0; } u_int32_t getTotClockDivider() { return 0; } u_int32_t setTotDutyCycle(int d) { return 0; } u_int32_t getTotDutyCycle() { return 0; } u_int32_t setExtSignal(int d, enum externalSignalFlag mode) { u_int32_t c; c=bus_r(EXT_SIGNAL_REG); if (d>=0 && d<4) { signals[d]=mode; #ifdef VERBOSE printf("settings signal variable number %d to value %04x\n", d, signals[d]); #endif // if output signal, set it! switch (mode) { case GATE_IN_ACTIVE_HIGH: case GATE_IN_ACTIVE_LOW: if (timingMode==GATE_FIX_NUMBER || timingMode==GATE_WITH_START_TRIGGER) setFPGASignal(d,mode); else setFPGASignal(d,SIGNAL_OFF); break; case TRIGGER_IN_RISING_EDGE: case TRIGGER_IN_FALLING_EDGE: if (timingMode==TRIGGER_EXPOSURE || timingMode==GATE_WITH_START_TRIGGER) setFPGASignal(d,mode); else setFPGASignal(d,SIGNAL_OFF); break; case RO_TRIGGER_IN_RISING_EDGE: case RO_TRIGGER_IN_FALLING_EDGE: if (timingMode==TRIGGER_READOUT) setFPGASignal(d,mode); else setFPGASignal(d,SIGNAL_OFF); break; case MASTER_SLAVE_SYNCHRONIZATION: setSynchronization(syncMode); break; default: setFPGASignal(d,mode); break; } setTiming(GET_EXTERNAL_COMMUNICATION_MODE); } return getExtSignal(d); } u_int32_t setFPGASignal(int d, enum externalSignalFlag mode) { int modes[]={EXT_SIG_OFF, EXT_GATE_IN_ACTIVEHIGH, EXT_GATE_IN_ACTIVELOW,EXT_TRIG_IN_RISING,EXT_TRIG_IN_FALLING,EXT_RO_TRIG_IN_RISING, EXT_RO_TRIG_IN_FALLING,EXT_GATE_OUT_ACTIVEHIGH, EXT_GATE_OUT_ACTIVELOW, EXT_TRIG_OUT_RISING, EXT_TRIG_OUT_FALLING, EXT_RO_TRIG_OUT_RISING, EXT_RO_TRIG_OUT_FALLING}; u_int32_t c; int off=d*SIGNAL_OFFSET; c=bus_r(EXT_SIGNAL_REG); if (mode<=RO_TRIGGER_OUT_FALLING_EDGE && mode>=0) { #ifdef VERBOSE printf("writing signal register number %d mode %04x\n",d, modes[mode]); #endif bus_w(EXT_SIGNAL_REG,((modes[mode])<=0 && d<4) { #ifdef VERBOSE printf("gettings signal variable number %d value %04x\n", d, signals[d]); #endif return signals[d]; } else return -1; } int getFPGASignal(int d) { int modes[]={SIGNAL_OFF, GATE_IN_ACTIVE_HIGH, GATE_IN_ACTIVE_LOW,TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE,RO_TRIGGER_IN_RISING_EDGE, RO_TRIGGER_IN_FALLING_EDGE, GATE_OUT_ACTIVE_HIGH, GATE_OUT_ACTIVE_LOW, TRIGGER_OUT_RISING_EDGE, TRIGGER_OUT_FALLING_EDGE, RO_TRIGGER_OUT_RISING_EDGE,RO_TRIGGER_OUT_FALLING_EDGE}; int off=d*SIGNAL_OFFSET; int mode=((bus_r(EXT_SIGNAL_REG)&(SIGNAL_MASK<>off); if (mode<=RO_TRIGGER_OUT_FALLING_EDGE) { if (modes[mode]!=SIGNAL_OFF && signals[d]!=MASTER_SLAVE_SYNCHRONIZATION) signals[d]=modes[mode]; #ifdef VERYVERBOSE printf("gettings signal register number %d value %04x\n", d, modes[mode]); #endif return modes[mode]; } else return -1; } /* enum externalCommunicationMode{ GET_EXTERNAL_COMMUNICATION_MODE, AUTO, TRIGGER_EXPOSURE_SERIES, TRIGGER_EXPOSURE_BURST, TRIGGER_READOUT, TRIGGER_COINCIDENCE_WITH_INTERNAL_ENABLE, GATE_FIX_NUMBER, GATE_FIX_DURATION, GATE_WITH_START_TRIGGER, GATE_COINCIDENCE_WITH_INTERNAL_ENABLE }; */ int setTiming(int ti) { int ret=GET_EXTERNAL_COMMUNICATION_MODE; int g=-1, t=-1, rot=-1; int i; switch (ti) { case AUTO_TIMING: printf("\nSetting timing to auto\n"); timingMode=ti; // disable all gates/triggers in except if used for master/slave synchronization for (i=0; i<4; i++) { if (getFPGASignal(i)>0 && getFPGASignal(i)=0 && t>=0 && rot<0) { ret=GATE_WITH_START_TRIGGER; } else if (g<0 && t>=0 && rot<0) { ret=TRIGGER_EXPOSURE; } else if (g>=0 && t<0 && rot<0) { ret=GATE_FIX_NUMBER; } else if (g<0 && t<0 && rot>0) { ret=TRIGGER_READOUT; } else if (g<0 && t<0 && rot<0) { ret=AUTO_TIMING; } // timingMode=ret; return ret; } int setConfigurationRegister(int d) { #ifdef VERBOSE printf("Setting configuration register to %x",d); #endif if (d>=0) { bus_w(CONFIG_REG,d); } #ifdef VERBOSE printf("configuration register is %x", bus_r(CONFIG_REG)); #endif return bus_r(CONFIG_REG); } int setToT(int d) { //int ret=0; int reg; #ifdef VERBOSE printf("Setting ToT to %d\n",d); #endif reg=bus_r(CONFIG_REG); #ifdef VERBOSE printf("Before: ToT is %x\n", reg); #endif if (d>0) { bus_w(CONFIG_REG,reg|TOT_ENABLE_BIT); } else if (d==0) { bus_w(CONFIG_REG,reg&(~TOT_ENABLE_BIT)); } reg=bus_r(CONFIG_REG); #ifdef VERBOSE printf("ToT is %x\n", reg); #endif if (reg&TOT_ENABLE_BIT) return 1; else return 0; } int setContinousReadOut(int d) { //int ret=0; int reg; #ifdef VERBOSE printf("Setting Continous readout to %d\n",d); #endif reg=bus_r(CONFIG_REG); #ifdef VERBOSE printf("Before: Continous readout is %x\n", reg); #endif if (d>0) { bus_w(CONFIG_REG,reg|CONT_RO_ENABLE_BIT); } else if (d==0) { bus_w(CONFIG_REG,reg&(~CONT_RO_ENABLE_BIT)); } reg=bus_r(CONFIG_REG); #ifdef VERBOSE printf("Continous readout is %x\n", reg); #endif if (reg&CONT_RO_ENABLE_BIT) return 1; else return 0; } u_int64_t getDetectorNumber() { char output[255],mac[255]=""; u_int64_t res=0; FILE* sysFile = popen("ifconfig eth0 | grep HWaddr | cut -d \" \" -f 11", "r"); fgets(output, sizeof(output), sysFile); pclose(sysFile); //getting rid of ":" char * pch; pch = strtok (output,":"); while (pch != NULL){ strcat(mac,pch); pch = strtok (NULL, ":"); } sscanf(mac,"%llx",&res); return res; } u_int64_t getFirmwareVersion() { return ((bus_r(FPGA_VERSION_REG) & BOARD_REVISION_MSK) >> BOARD_REVISION_OFST); } int64_t getId(enum idMode arg) { int64_t retval = -1; switch(arg){ case DETECTOR_SERIAL_NUMBER: retval = getDetectorNumber(); break; case DETECTOR_FIRMWARE_VERSION: retval=getFirmwareSVNVersion(); retval=(retval <<32) | getFirmwareVersion(); break; case DETECTOR_SOFTWARE_VERSION: retval= SVNREV; retval= (retval <<32) | SVNDATE; break; default: printf("Required unknown id %d \n", arg); break; } return retval; } int testFifos(void) { printf("Fifo test not implemented!\n"); /*bus_w16(CONTROL_REG, START_FIFOTEST_BIT); check with Carlos bus_w16(CONTROL_REG, 0x0);*/ return OK; } u_int32_t testFpga(void) { printf("\nTesting FPGA...\n"); //fixed pattern int ret = OK; volatile u_int32_t val = bus_r(FIX_PATT_REG); if (val == FIX_PATT_VAL) { printf("Fixed pattern: successful match 0x%08x\n",val); } else { cprintf(RED,"Fixed pattern does not match! Read 0x%08x, expected 0x%08x\n", val, FIX_PATT_VAL); ret = FAIL; } printf("\n"); return ret; } u_int32_t testRAM(void) { int result=OK; printf("RAM Test not implemented!\n"); return result; } int testBus() { printf("\nTesting Bus...\n"); int ret = OK; u_int32_t addr = SET_DELAY_LSB_REG; int times = 1000 * 1000; int i = 0; for (i = 0; i < times; ++i) { bus_w(addr, i * 100); if (i * 100 != bus_r(SET_DELAY_LSB_REG)) { cprintf(RED,"ERROR: Mismatch! Wrote 0x%x, read 0x%x\n", i * 100, bus_r(SET_DELAY_LSB_REG)); ret = FAIL; } } if (ret == OK) printf("Successfully tested bus %d times\n", times); printf("\n"); return ret; } int getNModBoard() { return 1; } int setNMod(int n) { return 1; } int getNMod() { return 1; } // program dacq settings int64_t set64BitReg(int64_t value, int aLSB, int aMSB){ int64_t v64; u_int32_t vLSB,vMSB; if (value!=-1) { vLSB=value&(0xffffffff); bus_w(aLSB,vLSB); v64=value>> 32; vMSB=v64&(0xffffffff); bus_w(aMSB,vMSB); } return get64BitReg(aLSB, aMSB); } int64_t get64BitReg(int aLSB, int aMSB){ int64_t v64; u_int32_t vLSB,vMSB; vLSB=bus_r(aLSB); vMSB=bus_r(aMSB); v64=vMSB; v64=(v64<<32) | vLSB; printf("reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, v64); return v64; } int64_t setFrames(int64_t value){ if(value!=-1) printf("\nSetting number of frames to %lld\n",(long long int)value); int64_t retval = set64BitReg(value, SET_FRAMES_LSB_REG, SET_FRAMES_MSB_REG); printf("Getting number of frames: %lld\n",(long long int)retval); return retval; } int64_t getFrames(){ return get64BitReg(GET_FRAMES_LSB_REG, GET_FRAMES_MSB_REG); } int64_t setExposureTime(int64_t value){ if (value!=-1){ printf("\nSetting exptime to %lldns\n",(long long int)value); value*=(1E-3*clockdivider_exptime); } int64_t retval = set64BitReg(value,SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG)/(1E-3*clockdivider_exptime);//(1E-9*CLK_FREQ); printf("Getting exptime: %lldns\n",(long long int)retval); return retval; } int64_t getExposureTime(){ return get64BitReg(GET_EXPTIME_LSB_REG, GET_EXPTIME_MSB_REG)/(1E-3*clockdivider_exptime);//(1E-9*CLK_FREQ); } int64_t setGates(int64_t value){ if(value!=-1) printf("\nSetting number of gates to %lld\n",(long long int)value); int64_t retval = set64BitReg(value, SET_GATES_LSB_REG, SET_GATES_MSB_REG); printf("Getting number of gates: %lld\n",(long long int)retval); return retval; } int64_t getGates(){ return get64BitReg(GET_GATES_LSB_REG, GET_GATES_MSB_REG); } int64_t setPeriod(int64_t value){ if (value!=-1){ printf("\nSetting period to %lldns\n",(long long int)value); value*=(1E-3*clockdivider_fc); } int64_t retval = set64BitReg(value,SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/(1E-3*clockdivider_fc);//(1E-9*CLK_FREQ); printf("Getting period: %lldns\n",(long long int)retval); return retval; } int64_t getPeriod(){ return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG)/(1E-3*clockdivider_fc);//(1E-9*CLK_FREQ); } int64_t setDelay(int64_t value){ if (value!=-1){ printf("\nSetting delay to %lldns\n",(long long int)value); value*=(1E-3*clockdivider_fc); } int64_t retval = set64BitReg(value,SET_DELAY_LSB_REG, SET_DELAY_MSB_REG)/(1E-3*clockdivider_fc);//(1E-9*CLK_FREQ); printf("Getting delay: %lldns\n",(long long int)retval); return retval; } int64_t getDelay(){ return get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG)/(1E-3*clockdivider_fc);//(1E-9*CLK_FREQ); } int64_t setTrains(int64_t value){ if(value!=-1) printf("\nSetting number of cycles to %lld\n",(long long int)value); int64_t retval = set64BitReg(value, SET_CYCLES_LSB_REG, SET_CYCLES_MSB_REG); printf("Getting number of cycles: %lld\n",(long long int)retval); return retval; } int64_t getTrains(){ return get64BitReg(GET_CYCLES_LSB_REG, GET_CYCLES_MSB_REG); } int64_t setProbes(int64_t value){ return 0; } int64_t setProgress() { return 0; } int64_t getProgress() { //should be done in firmware!!!! return 0; } int64_t getActualTime(){ return get64BitReg(TIME_FROM_START_LSB_REG, TIME_FROM_START_MSB_REG)/(1E-9*CLK_FREQ); } int64_t getMeasurementTime(){ int64_t v=get64BitReg(MEASUREMENT_START_TIME_LSB_REG, MEASUREMENT_START_TIME_MSB_REG); return v/(1E-9*CLK_FREQ); } int64_t getFramesFromStart(){ /** ask Carlos.. sending back v, but not used in firmware? */ int64_t v=get64BitReg(FRAMES_FROM_START_LSB_REG, FRAMES_FROM_START_MSB_REG); int64_t v1=get64BitReg(FRAMES_FROM_START_PG_LSB_REG, FRAMES_FROM_START_PG_MSB_REG); printf("Frames from start data streaming %lld\n",v); printf("Frames from start run control %lld\n",v1); return v; } ROI *setROI(int nroi,ROI* arg,int *retvalsize, int *ret) { cprintf(RED,"ROI Not implemented yet\n"); return NULL; } int loadImage(int index, short int ImageVals[]){ printf("loadImage Not implemented yet\n"); return OK; } int64_t getProbes(){ return 0; } int setDACRegister(int idac, int val, int imod) { u_int32_t addr, reg, mask; int off; #ifdef VERBOSE if(val==-1) printf("Getting dac register%d module %d\n",idac,imod); else printf("Setting dac register %d module %d to %d\n",idac,imod,val); #endif switch(idac){ case 0: case 1: case 2: addr=MOD_DACS1_REG; break; case 3: case 4: case 5: addr=MOD_DACS2_REG; break; case 6: case 7: addr=MOD_DACS3_REG; break; default: printf("weird idac value %d\n",idac); return -1; break; } //saving only the msb val=val>>2; off=(idac%3)*10; mask=~((0x3ff)<=0 && val>off)&0x3ff; //since we saved only the msb val=val<<2; //val=(bus_r(addr)>>off)&0x3ff; #ifdef VERBOSE printf("Dac %d module %d register is %d\n\n",idac,imod,val); #endif return val; } int getTemperature(int tempSensor, int imod){ int val; imod=0;//ignoring more than 1 mod for now int i,j,repeats=6; u_int32_t tempVal=0; #ifdef VERBOSE char cTempSensor[2][100]={"ADCs/ASICs","VRs/FPGAs"}; printf("Getting Temperature of module:%d for the %s for tempsensor:%d\n",imod,cTempSensor[tempSensor],tempSensor); #endif bus_w(TEMP_IN_REG,(T1_CLK_BIT)|(T1_CS_BIT)|(T2_CLK_BIT)|(T2_CS_BIT));//standby bus_w(TEMP_IN_REG,((T1_CLK_BIT)&~(T1_CS_BIT))|(T2_CLK_BIT));//high clk low cs for(i=0;i<20;i++) { //repeats is number of register writes for delay for(j=0;j>1);//fpga } } bus_w(TEMP_IN_REG,(T1_CLK_BIT)|(T1_CS_BIT)|(T2_CLK_BIT)|(T2_CS_BIT));//standby val=((int)tempVal)/4.0; #ifdef VERBOSE printf("Temperature of module:%d for the %s is %.2fC\n",imod,cTempSensor[tempSensor],val); #endif return val; } int initHighVoltage(int val, int imod){ u_int32_t addr = SPI_REG; float alpha=0.55; u_int16_t valw, dacvalue; u_int32_t codata; int numbits = 8; int valuemask = 0xff; // setting hv if (val >= 0) { // limit values if (val < 60) { dacvalue = 0; val = 60; } else if (val >= 200) { dacvalue = 0x1; val = 200; } else { dacvalue = 1. + (200.-val) / alpha; val=200.-(dacvalue-1)*alpha; } printf ("\n Setting High voltage to %d (dacval %d)\n",val, dacvalue); codata = dacvalue & valuemask; // start point 0xffff valw = 0xffff; //To make it compatible with old board //valw = DAC_SERIAL_DIGITAL_OUT_MSK & DAC_SERIAL_CLK_OUT_MSK & DAC_SERIAL_CS_OUT_MSK & //HV_SERIAL_DIGITAL_OUT_MSK & HV_SERIAL_CLK_OUT_MSK & HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); // chip sel bar down valw &= ~HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); { int i = 0; for (i = 0; i < numbits; i++) { // clk down valw &= ~HV_SERIAL_CLK_OUT_MSK; bus_w (addr, valw); // write data (i) (each bit from codata starting from msb) valw = ((valw & ~HV_SERIAL_DIGITAL_OUT_MSK) + (((codata >> (7-i)) & 0x1) << HV_SERIAL_DIGITAL_OUT_OFST)); bus_w (addr, valw); // clk up valw |= HV_SERIAL_CLK_OUT_MSK ; bus_w (addr, valw); } } // chip sel bar up valw |= HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); //clk down valw &= ~HV_SERIAL_CLK_OUT_MSK; bus_w (addr, valw); // stop point = start point of course 0xffff valw = 0xffff; //To make it compatible with old board //valw = DAC_SERIAL_DIGITAL_OUT_MSK & DAC_SERIAL_CLK_OUT_MSK & DAC_SERIAL_CS_OUT_MSK & //HV_SERIAL_DIGITAL_OUT_MSK & HV_SERIAL_CLK_OUT_MSK & HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); printf(" High voltage set to %d (dacval %d)\n", val, dacvalue); highvoltage = val; } return highvoltage; } int initConfGain(int isettings,int val,int imod){ int retval; u_int32_t addr=CONFGAIN_REG; if(isettings!=-1){ //#ifdef VERBOSE printf("Setting Gain with val:0x%x\n",val); //#endif bus_w(addr,(val|(bus_r(addr)&~GAIN_MASK))); } retval=(bus_r(addr)&GAIN_MASK); //#ifdef VERBOSE printf("Value read from Gain reg is 0x%x\n",retval); printf("Gain Reg Value is 0x%x\n",bus_r(addr)); //#endif return retval; } int initSpeedConfGain(int val){ int retval; u_int32_t addr=CONFGAIN_REG; if(val!=-1){ //#ifdef VERBOSE printf("\nSetting Speed of Gain reg with val:0x%x\n",val); //#endif bus_w(addr,((val<>SPEED_GAIN_OFFSET); //#ifdef VERBOSE printf("Value read from Speed of Gain reg is 0x%x\n",retval); printf("Gain Reg Value is 0x%x\n",bus_r(addr)); //#endif return retval; } int setADC(int adc){ int reg,nchips,mask,nchans; if(adc==-1) ROI_flag=0; else ROI_flag=1; // setDAQRegister();//token timing cleanFifo();//adc sync //with moench module all adc //set packet size ipPacketSize= DEFAULT_IP_PACKETSIZE; udpPacketSize=DEFAULT_UDP_PACKETSIZE; //set channel mask nchips = NCHIP; nchans = NCHANS; mask = ACTIVE_ADC_MASK; //set channel mask reg = (nchans*nchips)< 1 ) { sum += *addr++; count -= 2; } if( count > 0 ) sum += *addr; // Add left-over byte, if any while (sum>>16) sum = (sum & 0xffff) + (sum >> 16);// Fold 32-bit sum to 16 bits checksum = (~sum)&0xffff; printf("IP checksum is 0x%lx\n",checksum); return checksum; } #ifdef NEW_GBE_INTERFACE int writeGbeReg(int ivar, uint32_t val, int addr, int interface) { /* #define GBE_CTRL_WSTROBE 0 */ /* #define GBE_CTRL_VAR_OFFSET 16 */ /* #define GBE_CTRL_VAR_MASK 0XF */ /* #define GBE_CTRL_RAMADDR_OFFSET 24 */ /* #define GBE_CTRL_RAMADDR_MASK 0X3F */ /* #define GBE_CTRL_INTERFACE 23 */ uint32_t ctrl=((ivar&GBE_CTRL_VAR_MASK)<>32)&0xFFFFFFFF; vals[IPCHECKSUM_ADDR]=checksum; vals[GBE_DELAY_ADDR]=0; vals[GBE_RESERVED1_ADDR]=sourceport; vals[GBE_RESERVED2_ADDR]=interface; vals[DETECTOR_MAC_L_ADDR]=(sourcemac)&0xFFFFFFFF; vals[DETECTOR_MAC_H_ADDR]=(sourcemac>>32)&0xFFFFFFFF; vals[DETECTOR_IP_ADDR]=sourceip; for (ivar=0; ivar>32)&0xFFFFFFFF);//rx_udpmacH_AReg_c bus_w(RX_UDPMACL_AREG,(destmac)&0xFFFFFFFF);//rx_udpmacL_AReg_c bus_w(DETECTORMACH_AREG,(sourcemac>>32)&0xFFFFFFFF);//detectormacH_AReg_c bus_w(DETECTORMACL_AREG,(sourcemac)&0xFFFFFFFF);//detectormacL_AReg_c bus_w(UDPPORTS_AREG,((sourceport&0xFFFF)<<16)+(destport&0xFFFF));//udpports_AReg_c bus_w(IPCHKSUM_AREG,(checksum&0xFFFF));//ipchksum_AReg_c #endif /*bus_w(CONTROL_REG,0); Carlos modification*/ /*printf("System status register is %08x\n",bus_r(SYSTEM_STATUS_REG)); Carlos modification */ printf("Reset mem machine fifos\n"); bus_w(MEM_MACHINE_FIFOS_REG,0x4000); bus_w(MEM_MACHINE_FIFOS_REG,0x0); printf("Reset run control\n"); bus_w(MEM_MACHINE_FIFOS_REG,0x0400); bus_w(MEM_MACHINE_FIFOS_REG,0x0); usleep(500 * 1000); return 0; //any value doesnt matter - dhanya } int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int sourceip,int ival,uint32_t destport) { //int configureMAC(int ipad,long long int macad,long long int detectormacad, int detipad, int ival, int udpport){ /*volatile u_int32_t conf= bus_r(CONFIG_REG);*/ uint32_t sourceport = 0x7e9a; // 0xE185; int interface=0; int ngb; #ifdef NEW_GBE_INTERFACE ngb=2; printf("--------- New XGB interface\n"); #else ngb=1; printf("********* Old XGB interface\n"); #endif for (interface=0; interface > RUN_BUSY_OFST); #ifdef VERBOSE printf("status %04x\n",s); #endif return s; } u_int32_t runState(void) { int s=bus_r(STATUS_REG); #ifdef VERBOSE printf("status %04x\n",s); #endif return s; } // State Machine int startStateMachine(){ //int i; //#ifdef VERBOSE printf("*******Starting State Machine*******\n"); //#endif // cleanFifo(); // fifoReset(); //start state machine bus_w16(CONTROL_REG, FIFO_RESET_BIT); bus_w16(CONTROL_REG, 0x0); bus_w16(CONTROL_REG, START_ACQ_BIT | START_EXPOSURE_BIT); bus_w16(CONTROL_REG, 0x0); printf("statusreg=%08x\n",bus_r(STATUS_REG)); return OK; } int stopStateMachine(){ //#ifdef VERBOSE cprintf(BG_RED,"*******Stopping State Machine*******\n"); //#endif // for(i=0;i<100;i++){ //stop state machine bus_w16(CONTROL_REG, STOP_ACQ_BIT); usleep(100); bus_w16(CONTROL_REG, 0x0); printf("statusreg=%08x\n",bus_r(STATUS_REG)); return OK; } int startReadOut(){ #ifdef VERBOSE printf("Starting State Machine Readout\n"); #endif #ifdef DEBUG printf("State machine status is %08x\n",bus_r(STATUS_REG)); #endif bus_w16(CONTROL_REG, START_ACQ_BIT |START_READOUT_BIT); // start readout usleep(100); bus_w16(CONTROL_REG, 0x0); return OK; } enum runStatus getStatus() { #ifdef VERBOSE printf("Getting status\n"); #endif enum runStatus s; u_int32_t retval = runState(); printf("\n\nSTATUS=%08x\n",retval); //running if(((retval & RUN_BUSY_MSK) >> RUN_BUSY_OFST)) { if ((retval & WAITING_FOR_TRIGGER_MSK) >> WAITING_FOR_TRIGGER_OFST) { printf("-----------------------------------WAITING-----------------------------------\n"); s=WAITING; } else{ printf("-----------------------------------RUNNING-----------------------------------\n"); s=RUNNING; } } //not running else { if ((retval & STOPPED_MSK) >> STOPPED_OFST) { printf("-----------------------------------STOPPED--------------------------\n"); s=STOPPED; } else if ((retval & RUNMACHINE_BUSY_MSK) >> RUNMACHINE_BUSY_OFST) { printf("-----------------------------------READ MACHINE BUSY--------------------------\n"); s=TRANSMITTING; } else if (!retval) { printf("-----------------------------------IDLE--------------------------------------\n"); s=IDLE; } else { printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval); s=ERROR; } /* Check with Carlos , I included IDLE and unknown status above //and readbusy=0,idle else if((!(retval&0xffff))||(retval==SOME_FIFO_FULL_BIT)){ printf("-----------------------------------IDLE--------------------------------------\n"); s=IDLE; } else { printf("-----------------------------------Unknown status %08x--------------------------------------\n", retval); s=ERROR; ret=FAIL; }*/ } return s; } // fifo routines u_int32_t fifoReset(void) { return -1; } u_int32_t setNBits(u_int32_t n) { return -1; } u_int32_t getNBits(){ return -1; } u_int32_t fifoReadCounter(int fifonum){ return -1; } u_int32_t fifoReadStatus(){ return bus_r(STATUS_REG)&(SOME_FIFO_FULL_BIT | ALL_FIFO_EMPTY_BIT); } u_int32_t fifo_full(void){ return bus_r(STATUS_REG)&SOME_FIFO_FULL_BIT; } void waitForAcquisitionEnd(){ while(runBusy()){ usleep(500); } } u_int32_t* decode_data(int *datain) { u_int32_t *dataout; // const char one=1; const int bytesize=8; char *ptr=(char*)datain; //int nbits=dynamicRange; int ipos=0, ichan=0;; //int nch, boff=0; int ibyte;//, ibit; char iptr; #ifdef VERBOSE printf("Decoding data for DR %d\n",dynamicRange); #endif dataout=malloc(NCHAN*NCHIP*nModX*4); ichan=0; switch (dynamicRange) { case 1: for (ibyte=0; ibyte>(ipos))&0x1; ichan++; } } break; case 4: for (ibyte=0; ibyte>(ipos*4))&0xf; ichan++; } } break; case 8: for (ichan=0; ichan0) storeInRAM=1; else storeInRAM=0; return OK; } int getChannels() { int nch=32; int i; for (i=0; i>(23-i))&0x1)<-2) { dataret=FAIL; printf("no data and run stopped: %d frames left\n",(int)(getFrames()+2)); } else { dataret=FINISHED; printf("acquisition successfully finished\n"); } } //double nf = (double)numberFrames; for(i =0; i < 1280; i++){ adc = i / 256; adcCh = (i - adc * 256) / 32; Ch = i - adc * 256 - adcCh * 32; adc--; double v2 = avg[i]; avg[i] = avg[i]/ ((double)numberFrames/(double)frames); unsigned short v = (unsigned short)avg[i]; printf("setting avg for channel %i(%i,%i,%i): %i (double= %f (%f))\t", i,adc,adcCh,Ch, v,avg[i],v2); v=i*100; ram_w16(DARK_IMAGE_REG,adc,adcCh,Ch,v-4096); if(ram_r16(DARK_IMAGE_REG,adc,adcCh,Ch) != v-4096){ printf("value is wrong (%i,%i,%i): %i \n",adc,adcCh,Ch, ram_r16(DARK_IMAGE_REG,adc,adcCh,Ch)); } } printf("frames: %i\n",numberFrames); printf("corrected avg by: %f\n",(double)numberFrames/(double)frames); printf("restoring previous condition\n"); setFrames(framesBefore); setPeriod(periodBefore); printf("---------------------------\n"); return 0; } uint64_t readPatternWord(int addr) { uint64_t word=0; int cntrl=0; if (addr>=MAX_PATTERN_LENGTH) return -1; printf("read %x\n",addr); cntrl= (addr&APATTERN_MASK) << PATTERN_CTRL_ADDR_OFFSET; bus_w(PATTERN_CNTRL_REG, cntrl); usleep(1000); bus_w(PATTERN_CNTRL_REG, cntrl | (1<< PATTERN_CTRL_READ_BIT) ); usleep(1000); printf("reading\n"); word=get64BitReg(PATTERN_OUT_LSB_REG,PATTERN_OUT_MSB_REG); printf("read %llx\n", word); usleep(1000); bus_w(PATTERN_CNTRL_REG, cntrl); printf("done\n"); return word; } uint64_t writePatternWord(int addr, uint64_t word) { int cntrl=0; if (addr>=MAX_PATTERN_LENGTH) return -1; printf("write %x %llx\n",addr, word); if (word!=-1){ set64BitReg(word,PATTERN_IN_REG_LSB,PATTERN_IN_REG_MSB); cntrl= (addr&APATTERN_MASK) << PATTERN_CTRL_ADDR_OFFSET; bus_w(PATTERN_CNTRL_REG, cntrl); usleep(1000); bus_w(PATTERN_CNTRL_REG, cntrl | (1<< PATTERN_CTRL_WRITE_BIT) ); usleep(1000); bus_w(PATTERN_CNTRL_REG, cntrl); return word; } else return readPatternWord(addr); } uint64_t writePatternIOControl(uint64_t word) { return FAIL; } uint64_t writePatternClkControl(uint64_t word) { return FAIL; } int setPatternLoop(int level, int *start, int *stop, int *n) { int ret=OK; int lval=0; int nreg; int areg; switch (level ) { case 0: nreg=PATTERN_N_LOOP0_REG; areg=PATTERN_LOOP0_AREG; break; case 1: nreg=PATTERN_N_LOOP1_REG; areg=PATTERN_LOOP1_AREG; break; case 2: nreg=PATTERN_N_LOOP2_REG; areg=PATTERN_LOOP2_AREG; break; case -1: nreg=-1; areg=PATTERN_LIMITS_AREG; break; default: return FAIL; } printf("level %d start %x stop %x nl %d\n",level, *start, *stop, *n); if (nreg>=0) { if ((*n)>=0) bus_w(nreg, *n); printf ("n %d\n",*n); *n=bus_r(nreg); printf ("n %d\n",*n); } printf("level %d start %x stop %x nl %d\n",level, *start, *stop, *n); lval=bus_r(areg); /* printf("l=%x\n",bus_r16(areg)); */ /* printf("m=%x\n",bus_r16_m(areg)); */ printf("lval %x\n",lval); if (*start==-1) *start=(lval>> ASTART_OFFSET) & APATTERN_MASK; printf("start %x\n",*start); if (*stop==-1) *stop=(lval>> ASTOP_OFFSET) & APATTERN_MASK; printf("stop %x\n",*stop); lval= ((*start & APATTERN_MASK) << ASTART_OFFSET) | ((*stop & APATTERN_MASK) << ASTOP_OFFSET); printf("lval %x\n",lval); bus_w(areg,lval); printf("lval %x\n",lval); return ret; } int setPatternWaitAddress(int level, int addr) { int reg; switch (level) { case 0: reg=PATTERN_WAIT0_AREG; break; case 1: reg=PATTERN_WAIT1_AREG; break; case 2: reg=PATTERN_WAIT2_AREG; break; default: return -1; }; // printf("BEFORE *********PATTERN IOCTRL IS %llx (%x)\n",writePatternIOControl(-1), PATTERN_IOCTRL_REG_MSB); // printf ("%d addr %x (%x)\n",level,addr,reg); if (addr>=0) bus_w(reg, addr); // printf ("%d addr %x %x (%x) \n",level,addr, bus_r(reg), reg); // printf("AFTER *********PATTERN IOCTRL IS %llx (%x)\n",writePatternIOControl(-1), PATTERN_IOCTRL_REG_MSB); return bus_r(reg); } uint64_t setPatternWaitTime(int level, uint64_t t) { int reglsb; int regmsb; switch (level) { case 0: reglsb=PATTERN_WAIT0_TIME_REG_LSB; regmsb=PATTERN_WAIT0_TIME_REG_MSB; break; case 1: reglsb=PATTERN_WAIT1_TIME_REG_LSB; regmsb=PATTERN_WAIT1_TIME_REG_MSB; break; case 2: reglsb=PATTERN_WAIT2_TIME_REG_LSB; regmsb=PATTERN_WAIT2_TIME_REG_MSB; break; default: return -1; } if (t>=0) set64BitReg(t,reglsb,regmsb); return get64BitReg(reglsb,regmsb); } /** Carlos later, used only for 0 and 8 */ void initDac(int dacnum) { printf("\nInitializing dac for %d\n",dacnum); u_int32_t addr = SPI_REG; u_int16_t valw; u_int32_t codata; int csdx = dacnum / 8 + 2; // To make it compatible with old board (16 dacs), otherwise only DAC_SERIAL_CS_OUT_OFST printf("Chip select bit:%d\n" "Dac Channel Nr:%d\n", csdx, 0xf); int numbits = 25; codata = ( ((0x6 << 4) + /* 110 for initdac, 011 for specific dac ?? */ (0xf << 16)) + /* dac channel number (can be 0 - 8), f means all in initdac ??*/ ((0x0 << 4) & 0xfff0) /* value from bit 12 to 4?? */ ); // start point valw = 0xffff; //To make it compatible with old board //valw = DAC_SERIAL_DIGITAL_OUT_MSK & DAC_SERIAL_CLK_OUT_MSK & DAC_SERIAL_CS_OUT_MSK & //HV_SERIAL_DIGITAL_OUT_MSK & HV_SERIAL_CLK_OUT_MSK & HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); // chip sel bar down valw &= ~(0x1 << csdx); bus_w (addr, valw); { int i = 0; for (i = 0; i < numbits; i++) { // clk down valw &= ~DAC_SERIAL_CLK_OUT_MSK; bus_w (addr, valw); // write data (i) (each bit from codata starting from msb) valw = ((valw & ~DAC_SERIAL_DIGITAL_OUT_MSK) + (((codata >> (numbits - 1 - i)) & 0x1) << DAC_SERIAL_DIGITAL_OUT_OFST)); bus_w (addr, valw); // clk up valw |= DAC_SERIAL_CLK_OUT_MSK ; bus_w (addr, valw); } } // chip sel bar up valw |= (0x1 << csdx); bus_w (addr, valw); //clk down valw &= ~DAC_SERIAL_CLK_OUT_MSK; bus_w (addr, valw); // stop point = start point of course valw = 0xffff; //To make it compatible with old board //valw = DAC_SERIAL_DIGITAL_OUT_MSK & DAC_SERIAL_CLK_OUT_MSK & DAC_SERIAL_CS_OUT_MSK & //HV_SERIAL_DIGITAL_OUT_MSK & HV_SERIAL_CLK_OUT_MSK & HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); } int setDacRegister(int dacnum,int dacvalue) { int val; if (dacvalue==-100) dacvalue=0xffff; if (dacnum%2) { val=((dacvalue & 0xffff)<<16) | getDacRegister(dacnum-1); } else { val=(getDacRegister(dacnum+1)<<16) | (dacvalue & 0xffff); } printf("Dac register %x wrote %08x\n",(DAC_REG_OFF+dacnum/2)<<11,val); bus_w((DAC_REG_OFF+dacnum/2)<<11, val); return getDacRegister(dacnum); } int getDacRegister(int dacnum) { int retval; retval=bus_r((DAC_REG_OFF+dacnum/2)<<11); printf("Dac register %x read %08x\n",(DAC_REG_OFF+dacnum/2)<<11,retval); if (dacnum%2) return (retval>>16)&0xffff; else return retval&0xffff; } int setDac(int dacnum, int dacvalue){ printf("\nSetting of DAC %d with value %d\n",dacnum, dacvalue); u_int32_t addr = SPI_REG; u_int16_t valw; u_int32_t codata; int csdx = dacnum / 8 + 2; // Chip select can be DAC_SERIAL_CS_OUT_OFST(2) or 3 (compatibility with old board 16 dacs) int dacch = dacnum % 8; // 0-8, dac channel number (also for dacnum 9-15 in old board) int numbits = 25; printf("Chip select bit:%d\n" "Dac Channel Nr:%d\n", csdx, dacch); // setting dac if (dacvalue >= 0) { //modified to power down single channels codata=((((0x2)<<4)+((dacch)&0xf))<<16)+((dacvalue<<4)&0xfff0); codata = ( ((0x3 << 4) + /** 110 for initdac, 011 for specific dac?? */ ((dacch)&0xf)) /** dac ch number (can be 0 - 8). f means all in initdac ?? */ << 16) + /** Carlos later, why change in bracket position */ ((dacvalue<<4)&0xfff0); /* value from bit 12 to 4?? */ codata=(((0x6<<4)+(0xf<<16))+((0x0<<4)&0xfff0)); codata=(((0x3<<4)+((dacch)&0xf))<<16)+((dacvalue<<4)&0xfff0); // start point valw = 0xffff; //To make it compatible with old board //valw = DAC_SERIAL_DIGITAL_OUT_MSK & DAC_SERIAL_CLK_OUT_MSK & DAC_SERIAL_CS_OUT_MSK & //HV_SERIAL_DIGITAL_OUT_MSK & HV_SERIAL_CLK_OUT_MSK & HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); // chip sel bar down valw &= ~(0x1 << csdx); bus_w (addr, valw); { int i = 0; for (i = 0; i < numbits; i++) { // clk down valw &= ~DAC_SERIAL_CLK_OUT_MSK; bus_w (addr, valw); // write data (i) (each bit from codata starting from msb) valw = ((valw & ~DAC_SERIAL_DIGITAL_OUT_MSK) + (((codata >> (numbits - 1 - i)) & 0x1) << DAC_SERIAL_DIGITAL_OUT_OFST)); bus_w (addr, valw); // clk up valw |= DAC_SERIAL_CLK_OUT_MSK ; bus_w (addr, valw); } } // chip sel bar up valw |= (0x1 << csdx); bus_w (addr, valw); //clk down valw &= ~DAC_SERIAL_CLK_OUT_MSK; bus_w (addr, valw); // stop point = start point of course valw = 0xffff; //To make it compatible with old board //valw = DAC_SERIAL_DIGITAL_OUT_MSK & DAC_SERIAL_CLK_OUT_MSK & DAC_SERIAL_CS_OUT_MSK & //HV_SERIAL_DIGITAL_OUT_MSK & HV_SERIAL_CLK_OUT_MSK & HV_SERIAL_CS_OUT_MSK; bus_w (addr, valw); printf("Writing %d in DAC %d \n",dacvalue,dacnum); setDacRegister(dacnum,dacvalue); } else if (dacvalue==-100) { printf("switching off dac %d\n", dacnum); csdx=dacnum/8+2; dacch=dacnum%8; ddx=0; cdx=1; codata=((((0x4)<<4)+((dacch)&0xf))<<16)+((dacvalue<<4)&0xfff0); valw=0xffff; bus_w(offw,(valw)); // start point valw=((valw&(~(0x1<>(24-i))&0x1)<>(24-i))&0x1)); valw=((valw&(~(0x1<