// SPDX-License-Identifier: LGPL-3.0-or-other // Copyright (C) 2021 Contributors to the SLS Detector Package #pragma once // clang-format off #define REG_OFFSET (4) #define PATTERN_STEP0_MSB_REG (0x10004) #define PATTERN_STEP0_LSB_REG (0x10000) #ifndef __CHEBY__XCTB__H__ #define __CHEBY__XCTB__H__ #define XCTB_SIZE 49924 /* 0xc304 */ /* REG CTRL_Reg */ #define CTRL_REG 0x8000UL #define POWER_VIO 0x1UL #define POWER_VIO_MSK 0x1UL #define POWER_VIO_OFST 0 #define POWER_VCC_A 0x2UL #define POWER_VCC_A_MSK 0x2UL #define POWER_VCC_A_OFST 1 #define POWER_VCC_B 0x4UL #define POWER_VCC_B_MSK 0x4UL #define POWER_VCC_B_OFST 2 #define POWER_VCC_C 0x8UL #define POWER_VCC_C_MSK 0x8UL #define POWER_VCC_C_OFST 3 #define POWER_VCC_D 0x10UL #define POWER_VCC_D_MSK 0x10UL #define POWER_VCC_D_OFST 4 /* REG Status_Reg */ #define STATUS_REG 0x8004UL #define PATTERN_RUNNING 0x1UL #define PATTERN_RUNNING_MSK 0x1UL #define PATTERN_RUNNING_OFST 0 #define RX_BUSY 0x2UL #define RX_BUSY_MSK 0x2UL #define RX_BUSY_OFST 1 #define PROCESSING_BUSY 0x4UL #define PROCESSING_BUSY_MSK 0x4UL #define PROCESSING_BUSY_OFST 2 #define UDP_GEN_BUSY 0x8UL #define UDP_GEN_BUSY_MSK 0x8UL #define UDP_GEN_BUSY_OFST 3 #define NETWORK_BUSY 0x10UL #define NETWORK_BUSY_MSK 0x10UL #define NETWORK_BUSY_OFST 4 #define WAIT_FOR_TRIGGER 0x20UL #define WAIT_FOR_TRIGGER_MSK 0x20UL #define WAIT_FOR_TRIGGER_OFST 5 #define RX_NOT_GOOD 0x40UL #define RX_NOT_GOOD_MSK 0x40UL #define RX_NOT_GOOD_OFST 6 /* REG Status_Reg2 */ #define STATUS_REG2 0x8008UL #define STATUS_REG2_PRESET 0x0UL /* REG FPGAVersionReg */ #define FPGAVERSIONREG 0x800cUL #define FPGACOMPDATE_MSK 0xffffffUL #define FPGACOMPDATE_OFST 0 #define FPGADETTYPE_MSK 0xff000000UL #define FPGADETTYPE_OFST 24 #define FPGADETTYPE_PRESET 0x8UL /* REG FPGA_GIT_HEAD */ #define FPGA_GIT_HEAD 0x8010UL #define FPGA_GIT_HEAD_PRESET 0x0UL /* REG FixedPatternReg */ #define FIXEDPATTERNREG 0x8014UL #define FIXEDPATTERNREG_PRESET 0xacdc2016UL /* REG ApiVersionReg */ #define APIVERSIONREG 0x8018UL #define APICOMPDATE_MSK 0xffffffUL #define APICOMPDATE_OFST 0 #define APIDETTYPE_MSK 0xff000000UL #define APIDETTYPE_OFST 24 #define APIDETTYPE_PRESET 0x8UL /* REG datagen_ctrl */ #define DATAGEN_CTRL 0xc300UL #define DATAGEN_MH1_ENABLE 0x1UL #define DATAGEN_MH1_ENABLE_MSK 0x1UL #define DATAGEN_MH1_ENABLE_OFST 0 #define DATAGEN_MH1_RESETN 0x2UL #define DATAGEN_MH1_RESETN_MSK 0x2UL #define DATAGEN_MH1_RESETN_OFST 1 /* REG FIFO_To_Gb_Control_Reg */ #define FIFO_TO_GB_CONTROL_REG 0xa000UL #define ENABLED_CHANNELS_ADC_MSK 0xffUL #define ENABLED_CHANNELS_ADC_OFST 0 #define ENABLED_CHANNELS_D 0x100UL #define ENABLED_CHANNELS_D_MSK 0x100UL #define ENABLED_CHANNELS_D_OFST 8 #define ENABLED_CHANNELS_X_MSK 0x1e00UL #define ENABLED_CHANNELS_X_OFST 9 #define RO_MODE_ADC 0x2000UL #define RO_MODE_ADC_MSK 0x2000UL #define RO_MODE_ADC_OFST 13 #define RO_MODE_D 0x4000UL #define RO_MODE_D_MSK 0x4000UL #define RO_MODE_D_OFST 14 #define RO_MODE_X 0x8000UL #define RO_MODE_X_MSK 0x8000UL #define RO_MODE_X_OFST 15 #define COUNT_FRAMES_FROM_UPDATE 0x10000UL #define COUNT_FRAMES_FROM_UPDATE_MSK 0x10000UL #define COUNT_FRAMES_FROM_UPDATE_OFST 16 #define START_STREAMING_P 0x20000UL #define START_STREAMING_P_MSK 0x20000UL #define START_STREAMING_P_OFST 17 #define STREAM_BUFFER_CLEAR 0x40000UL #define STREAM_BUFFER_CLEAR_MSK 0x40000UL #define STREAM_BUFFER_CLEAR_OFST 18 /* REG no_Samples_D_Reg */ #define NO_SAMPLES_D_REG 0xa004UL #define NO_SAMPLES_D_MSK 0x3fffUL #define NO_SAMPLES_D_OFST 0 /* REG no_Samples_A_Reg */ #define NO_SAMPLES_A_REG 0xa008UL #define NO_SAMPLES_A_MSK 0x3fffUL #define NO_SAMPLES_A_OFST 0 /* REG no_Samples_X_Reg */ #define NO_SAMPLES_X_REG 0xa00cUL #define NO_SAMPLES_X_MSK 0x7FFFFFFFUL #define NO_SAMPLES_X_OFST 0 /* REG count_Frames_From_Reg_1 */ #define COUNT_FRAMES_FROM_REG_1 0xa010UL #define COUNT_FRAMES_FROM_REG_1_PRESET 0x0UL /* REG count_Frames_From_Reg_2 */ #define COUNT_FRAMES_FROM_REG_2 0xa014UL #define COUNT_FRAMES_FROM_REG_2_PRESET 0x0UL /* REG local_Frame_Number_Reg_1 */ #define LOCAL_FRAME_NUMBER_REG_1 0xa018UL #define LOCAL_FRAME_NUMBER_REG_1_PRESET 0x0UL /* REG local_Frame_Number_Reg_2 */ #define LOCAL_FRAME_NUMBER_REG_2 0xa01cUL #define LOCAL_FRAME_NUMBER_REG_2_PRESET 0x0UL /* REG TransceiverRXCTRL0Reg1 */ #define TRANSCEIVERRXCTRL0REG1 0xc100UL #define TRANSCEIVERRXCTRL0REG1_PRESET 0x0UL /* REG TransceiverRXCTRL0Reg2 */ #define TRANSCEIVERRXCTRL0REG2 0xc104UL #define TRANSCEIVERRXCTRL0REG2_PRESET 0x0UL /* REG TransceiverRXCTRL1Reg1 */ #define TRANSCEIVERRXCTRL1REG1 0xc108UL #define TRANSCEIVERRXCTRL1REG1_PRESET 0x0UL /* REG TransceiverRXCTRL1Reg2 */ #define TRANSCEIVERRXCTRL1REG2 0xc10cUL #define TRANSCEIVERRXCTRL1REG2_PRESET 0x0UL /* REG TransceiverRXCTRL2Reg */ #define TRANSCEIVERRXCTRL2REG 0xc110UL #define TRANSCEIVERRXCTRL2REG_PRESET 0x0UL /* REG TransceiverRXCTRL3Reg */ #define TRANSCEIVERRXCTRL3REG 0xc114UL #define TRANSCEIVERRXCTRL3REG_PRESET 0x0UL /* REG TransceiverSTATUS */ #define TRANSCEIVERSTATUS 0xc118UL #define LINKDOWNLATCHEDOUT 0x1UL #define LINKDOWNLATCHEDOUT_MSK 0x1UL #define LINKDOWNLATCHEDOUT_OFST 0 #define TXUSERCLKACTIVE 0x2UL #define TXUSERCLKACTIVE_MSK 0x2UL #define TXUSERCLKACTIVE_OFST 1 #define RXUSERCLKACTIVE 0x4UL #define RXUSERCLKACTIVE_MSK 0x4UL #define RXUSERCLKACTIVE_OFST 2 #define RXCOMMADET_MSK 0x78UL #define RXCOMMADET_OFST 3 #define RXBYTEREALIGN_MSK 0x780UL #define RXBYTEREALIGN_OFST 7 #define RXBYTEISALIGNED_MSK 0x7800UL #define RXBYTEISALIGNED_OFST 11 #define GTWIZRXCDRSTABLE 0x8000UL #define GTWIZRXCDRSTABLE_MSK 0x8000UL #define GTWIZRXCDRSTABLE_OFST 15 #define RESETTXDONE 0x10000UL #define RESETTXDONE_MSK 0x10000UL #define RESETTXDONE_OFST 16 #define RESETRXDONE 0x20000UL #define RESETRXDONE_MSK 0x20000UL #define RESETRXDONE_OFST 17 #define RXPMARESETDONE_MSK 0x3c0000UL #define RXPMARESETDONE_OFST 18 #define TXPMARESETDONE_MSK 0x3c00000UL #define TXPMARESETDONE_OFST 22 #define GTTPOWERGOOD_MSK 0x3c000000UL #define GTTPOWERGOOD_OFST 26 /* REG TransceiverSTATUS2 */ #define TRANSCEIVERSTATUS2 0xc11cUL #define RXLOCKED_MSK 0xfUL #define RXLOCKED_OFST 0 /* REG TransceiverCONTROL */ #define TRANSCEIVERCONTROL 0xc120UL #define GTWIZRESETALL 0x1UL #define GTWIZRESETALL_MSK 0x1UL #define GTWIZRESETALL_OFST 0 #define RESETTXPLLANDDATAPATH 0x2UL #define RESETTXPLLANDDATAPATH_MSK 0x2UL #define RESETTXPLLANDDATAPATH_OFST 1 #define RESETTXDATAPATHIN 0x4UL #define RESETTXDATAPATHIN_MSK 0x4UL #define RESETTXDATAPATHIN_OFST 2 #define RESETRXPLLANDDATAPATH 0x8UL #define RESETRXPLLANDDATAPATH_MSK 0x8UL #define RESETRXPLLANDDATAPATH_OFST 3 #define RESETRXDATAPATHIN 0x10UL #define RESETRXDATAPATHIN_MSK 0x10UL #define RESETRXDATAPATHIN_OFST 4 #define RXPOLARITY_MSK 0x1e0UL #define RXPOLARITY_OFST 5 #define RXERRORCNTRESET_MSK 0x1e00UL #define RXERRORCNTRESET_OFST 9 #define RXMSBLSBINVERT_MSK 0x1e000UL #define RXMSBLSBINVERT_OFST 13 #define RXWORDALIGNINVERT_MSK 0x1e0000UL #define RXWORDALIGNINVERT_OFST 17 #define ENABLEDVALIDLOCK 0x200000UL #define ENABLEDVALIDLOCK_MSK 0x200000UL #define ENABLEDVALIDLOCK_OFST 21 #define ENABLEMANUALWORDALIGN 0x400000UL #define ENABLEMANUALWORDALIGN_MSK 0x400000UL #define ENABLEMANUALWORDALIGN_OFST 22 /* REG TransceiverErrCnt_Reg0 */ #define TRANSCEIVERERRCNT_REG0 0xc124UL #define TRANSCEIVERERRCNT_REG0_PRESET 0x0UL /* REG TransceiverErrCnt_Reg1 */ #define TRANSCEIVERERRCNT_REG1 0xc128UL #define TRANSCEIVERERRCNT_REG1_PRESET 0x0UL /* REG TransceiverErrCnt_Reg2 */ #define TRANSCEIVERERRCNT_REG2 0xc12cUL #define TRANSCEIVERERRCNT_REG2_PRESET 0x0UL /* REG TransceiverErrCnt_Reg3 */ #define TRANSCEIVERERRCNT_REG3 0xc130UL #define TRANSCEIVERERRCNT_REG3_PRESET 0x0UL /* REG TransceiverAlignCnt_Reg0 */ #define TRANSCEIVERALIGNCNT_REG0 0xc134UL #define RXALIGNCNTCH0_MSK 0xffffUL #define RXALIGNCNTCH0_OFST 0 /* REG TransceiverAlignCnt_Reg1 */ #define TRANSCEIVERALIGNCNT_REG1 0xc138UL #define RXALIGNCNTCH1_MSK 0xffffUL #define RXALIGNCNTCH1_OFST 0 /* REG TransceiverAlignCnt_Reg2 */ #define TRANSCEIVERALIGNCNT_REG2 0xc13cUL #define RXALIGNCNTCH2_MSK 0xffffUL #define RXALIGNCNTCH2_OFST 0 /* REG TransceiverAlignCnt_Reg3 */ #define TRANSCEIVERALIGNCNT_REG3 0xc140UL #define RXALIGNCNTCH3_MSK 0xffffUL #define RXALIGNCNTCH3_OFST 0 /* REG TransceiverLastWord_Reg0 */ #define TRANSCEIVERLASTWORD_REG0 0xc144UL #define RXDATACH0_MSK 0xffffUL #define RXDATACH0_OFST 0 /* REG TransceiverLastWord_Reg1 */ #define TRANSCEIVERLASTWORD_REG1 0xc148UL #define RXDATACH1_MSK 0xffffUL #define RXDATACH1_OFST 0 /* REG TransceiverLastWord_Reg2 */ #define TRANSCEIVERLASTWORD_REG2 0xc14cUL #define RXDATACH2_MSK 0xffffUL #define RXDATACH2_OFST 0 /* REG TransceiverLastWord_Reg3 */ #define TRANSCEIVERLASTWORD_REG3 0xc150UL #define RXDATACH3_MSK 0xffffUL #define RXDATACH3_OFST 0 /* REG PktPacketLengthReg */ #define PKTPACKETLENGTHREG 0xa020UL #define PACKETLENGTH1G_MSK 0xffffUL #define PACKETLENGTH1G_OFST 0 #define PACKETLENGTH10G_MSK 0xffff0000UL #define PACKETLENGTH10G_OFST 16 /* REG PktNoPacketsReg */ #define PKTNOPACKETSREG 0xa024UL #define NOPACKETS1G_MSK 0x3fUL #define NOPACKETS1G_OFST 0 #define NOPACKETS10G_MSK 0x3f0000UL #define NOPACKETS10G_OFST 16 /* REG PktCtrlReg */ #define PKTCTRLREG 0xa028UL #define NOSERVERS_MSK 0x3fUL #define NOSERVERS_OFST 0 #define SERVERSTART_MSK 0x1f00UL #define SERVERSTART_OFST 8 #define ETHINTERF 0x10000UL #define ETHINTERF_MSK 0x10000UL #define ETHINTERF_OFST 16 /* REG PktCoordReg1 */ #define PKTCOORDREG1 0xa02cUL #define COORDX_MSK 0xffffUL #define COORDX_OFST 0 #define COORDY_MSK 0xffff0000UL #define COORDY_OFST 16 /* REG PktCoordReg2 */ #define PKTCOORDREG2 0xa030UL #define COORDZ_MSK 0xffffUL #define COORDZ_OFST 0 /* REG pattern_out_lsb_reg */ #define PATTERN_OUT_LSB_REG 0xb000UL #define PATTERN_OUT_LSB_REG_PRESET 0x0UL /* REG pattern_out_msb_reg */ #define PATTERN_OUT_MSB_REG 0xb004UL #define PATTERN_OUT_MSB_REG_PRESET 0x0UL /* REG pattern_in_lsb_reg */ #define PATTERN_IN_LSB_REG 0xb008UL #define PATTERN_IN_LSB_REG_PRESET 0x0UL /* REG pattern_in_msb_reg */ #define PATTERN_IN_MSB_REG 0xb00cUL #define PATTERN_IN_MSB_REG_PRESET 0x0UL /* REG pattern_mask_lsb_reg */ #define PATTERN_MASK_LSB_REG 0xb010UL #define PATTERN_MASK_LSB_REG_PRESET 0x0UL /* REG pattern_mask_msb_reg */ #define PATTERN_MASK_MSB_REG 0xb014UL #define PATTERN_MASK_MSB_REG_PRESET 0x0UL /* REG pattern_set_lsb_reg */ #define PATTERN_SET_LSB_REG 0xb018UL #define PATTERN_SET_LSB_REG_PRESET 0x0UL /* REG pattern_set_msb_reg */ #define PATTERN_SET_MSB_REG 0xb01cUL #define PATTERN_SET_MSB_REG_PRESET 0x0UL /* REG pattern_cntrl_reg */ #define PATTERN_CNTRL_REG 0xb020UL #define PATTERN_CNTRL_WR 0x1UL #define PATTERN_CNTRL_WR_MSK 0x1UL #define PATTERN_CNTRL_WR_OFST 0 #define PATTERN_CNTRL_RD 0x2UL #define PATTERN_CNTRL_RD_MSK 0x2UL #define PATTERN_CNTRL_RD_OFST 1 #define PATTERN_CNTRL_ADDR_MSK 0x1fff0000UL #define PATTERN_CNTRL_ADDR_OFST 16 /* REG pattern_limit_reg */ #define PATTERN_LIMIT_REG 0xb024UL #define PATTERN_LIMIT_STRT_MSK 0x1fffUL #define PATTERN_LIMIT_STRT_OFST 0 #define PATTERN_LIMIT_STP_MSK 0x1fff0000UL #define PATTERN_LIMIT_STP_OFST 16 /* REG pattern_io_cntrl_lsb_reg */ #define PATTERN_IO_CNTRL_LSB_REG 0xb028UL #define PATTERN_IO_CNTRL_LSB_REG_PRESET 0x0UL /* REG pattern_io_cntrl_msb_reg */ #define PATTERN_IO_CNTRL_MSB_REG 0xb02cUL #define PATTERN_IO_CNTRL_MSB_REG_PRESET 0x0UL /* REG Flow_Control_Reg */ #define FLOW_CONTROL_REG 0xb030UL #define START_F 0x1UL #define START_F_MSK 0x1UL #define START_F_OFST 0 #define STOP_F 0x2UL #define STOP_F_MSK 0x2UL #define STOP_F_OFST 1 #define RST_F 0x4UL #define RST_F_MSK 0x4UL #define RST_F_OFST 2 #define SW_TRIGGER_F 0x8UL #define SW_TRIGGER_F_MSK 0x8UL #define SW_TRIGGER_F_OFST 3 #define TRIGGER_ENABLE 0x10UL #define TRIGGER_ENABLE_MSK 0x10UL #define TRIGGER_ENABLE_OFST 4 #define RSM_BUSY 0x20UL #define RSM_BUSY_MSK 0x20UL #define RSM_BUSY_OFST 5 #define RSM_TRG_WAIT 0x40UL #define RSM_TRG_WAIT_MSK 0x40UL #define RSM_TRG_WAIT_OFST 6 #define CSM_BUSY 0x80UL #define CSM_BUSY_MSK 0x80UL #define CSM_BUSY_OFST 7 /* REG delay_In_Reg_1 */ #define DELAY_IN_REG_1 0xb034UL #define DELAY_IN_REG_1_PRESET 0x0UL /* REG delay_In_Reg_2 */ #define DELAY_IN_REG_2 0xb038UL #define DELAY_IN_REG_2_PRESET 0x0UL /* REG cycles_In_Reg_1 */ #define CYCLES_IN_REG_1 0xb03cUL #define CYCLES_IN_REG_1_PRESET 0x0UL /* REG cycles_In_Reg_2 */ #define CYCLES_IN_REG_2 0xb040UL #define CYCLES_IN_REG_2_PRESET 0x0UL /* REG frames_In_Reg_1 */ #define FRAMES_IN_REG_1 0xb044UL #define FRAMES_IN_REG_1_PRESET 0x0UL /* REG frames_In_Reg_2 */ #define FRAMES_IN_REG_2 0xb048UL #define FRAMES_IN_REG_2_PRESET 0x0UL /* REG period_In_Reg_1 */ #define PERIOD_IN_REG_1 0xb04cUL #define PERIOD_IN_REG_1_PRESET 0x0UL /* REG period_In_Reg_2 */ #define PERIOD_IN_REG_2 0xb050UL #define PERIOD_IN_REG_2_PRESET 0x0UL /* REG pattern_test_reg */ #define PATTERN_TEST_REG 0xb054UL #define PATTERN_TEST_REG_PRESET 0x0UL /* REG pattern_firmware_reg */ #define PATTERN_FIRMWARE_REG 0xb058UL #define PATTERN_WIDTH_MSK 0xffUL #define PATTERN_WIDTH_OFST 0 #define PATTERN_ADDR_WIDTH_MSK 0xff00UL #define PATTERN_ADDR_WIDTH_OFST 8 #define PATTERN_NLOOPS_NWAITS_MSK 0xff0000UL #define PATTERN_NLOOPS_NWAITS_OFST 16 #define DIRECT_PATTERN_RAM 0x1000000UL #define DIRECT_PATTERN_RAM_MSK 0x1000000UL #define DIRECT_PATTERN_RAM_OFST 24 /* REG time_From_Start_Out_Reg_1 */ #define TIME_FROM_START_OUT_REG_1 0xb05cUL #define TIME_FROM_START_OUT_REG_1_PRESET 0x0UL /* REG time_From_Start_Out_Reg_2 */ #define TIME_FROM_START_OUT_REG_2 0xb060UL #define TIME_FROM_START_OUT_REG_2_PRESET 0x0UL /* REG frames_From_Start_Out_Reg_1 */ #define FRAMES_FROM_START_OUT_REG_1 0xb064UL #define FRAMES_FROM_START_OUT_REG_1_PRESET 0x0UL /* REG frames_From_Start_Out_Reg_2 */ #define FRAMES_FROM_START_OUT_REG_2 0xb068UL #define FRAMES_FROM_START_OUT_REG_2_PRESET 0x0UL /* REG frame_Time_Out_Reg_1 */ #define FRAME_TIME_OUT_REG_1 0xb06cUL #define FRAME_TIME_OUT_REG_1_PRESET 0x0UL /* REG frame_Time_Out_Reg_2 */ #define FRAME_TIME_OUT_REG_2 0xb070UL #define FRAME_TIME_OUT_REG_2_PRESET 0x0UL /* REG pattern_loopdef_base */ #define PATTERN_LOOPDEF_BASE 0xb080UL #define PATTERN_LOOP_ADDR_WORD 0x1UL #define PATTERN_LOOP_ADDR_WORD_MSK 0x1UL #define PATTERN_LOOP_ADDR_WORD_OFST 0 #define PATTERN_LOOP_ITERATION_WORD 0x2UL #define PATTERN_LOOP_ITERATION_WORD_MSK 0x2UL #define PATTERN_LOOP_ITERATION_WORD_OFST 1 #define PATTERN_WAIT_ADDR_WORD 0x4UL #define PATTERN_WAIT_ADDR_WORD_MSK 0x4UL #define PATTERN_WAIT_ADDR_WORD_OFST 2 #define PATTERN_WAIT_TIMER_LSB_WORD 0x8UL #define PATTERN_WAIT_TIMER_LSB_WORD_MSK 0x8UL #define PATTERN_WAIT_TIMER_LSB_WORD_OFST 3 #define PATTERN_WAIT_TIMER_MSB_WORD 0x10UL #define PATTERN_WAIT_TIMER_MSB_WORD_MSK 0x10UL #define PATTERN_WAIT_TIMER_MSB_WORD_OFST 4 #define PATTERN_LOOPDEF_NWORDS 0x20UL #define PATTERN_LOOPDEF_NWORDS_MSK 0x20UL #define PATTERN_LOOPDEF_NWORDS_OFST 5 /* REG pattern_loopdef_base_helper1 */ #define PATTERN_LOOPDEF_BASE_HELPER1 0xb084UL #define PATTERN_WAIT_ADDR_MSK 0x1fffUL #define PATTERN_WAIT_ADDR_OFST 0 /* REG pattern_loopdef_base_helper2 */ #define PATTERN_LOOPDEF_BASE_HELPER2 0xb088UL #define PATTERN_LOOP_ADDR_STRT_MSK 0x1fffUL #define PATTERN_LOOP_ADDR_STRT_OFST 0 #define PATTERN_LOOP_ADDR_STP_MSK 0x1fff0000UL #define PATTERN_LOOP_ADDR_STP_OFST 16 /* REG pattern_bypass */ #define PATTERN_BYPASS 0xc200UL #define PATTERN_BYPASS_PRESET 0x0UL /* REG pattern_bypass_enable */ #define PATTERN_BYPASS_ENABLE 0xc204UL #define PATTERN_BYPASS_ENABLE_PRESET 0x0UL /* REG pattern_MOSI_bitselect */ #define PATTERN_MOSI_BITSELECT 0xc208UL #define PATTERN_MOSI_BITSELECT_PRESET 0x0UL /* REG pattern_SCLK_bitselect */ #define PATTERN_SCLK_BITSELECT 0xc20cUL #define PATTERN_SCLK_BITSELECT_PRESET 0x0UL /* REG pattern_SPI_writedata */ #define PATTERN_SPI_WRITEDATA 0xc210UL #define PATTERN_SPI_WRITEDATA_PRESET 0x0UL /* REG pattern_mux_ctrl */ #define PATTERN_MUX_CTRL 0xc214UL #define SPI_FULL 0x2UL #define SPI_FULL_MSK 0x2UL #define SPI_FULL_OFST 1 #define MISO_FIFO_CLEAR 0x4UL #define MISO_FIFO_CLEAR_MSK 0x4UL #define MISO_FIFO_CLEAR_OFST 2 #define MISO_FIFO_FULL 0x8UL #define MISO_FIFO_FULL_MSK 0x8UL #define MISO_FIFO_FULL_OFST 3 #define MISO_FIFO_EMPTY 0x10UL #define MISO_FIFO_EMPTY_MSK 0x10UL #define MISO_FIFO_EMPTY_OFST 4 #define ENABLE_CPU_SPI 0x20UL #define ENABLE_CPU_SPI_MSK 0x20UL #define ENABLE_CPU_SPI_OFST 5 #define SPI_REVERSE_BITORDER 0x40UL #define SPI_REVERSE_BITORDER_MSK 0x40UL #define SPI_REVERSE_BITORDER_OFST 6 /* REG MISO_data */ #define MISO_DATA 0xc218UL #define MISO_DATA_PRESET 0x0UL /* REG pattern_CSN_bitselect */ #define PATTERN_CSN_BITSELECT 0xc21cUL #define PATTERN_CSN_BITSELECT_PRESET 0x0UL /* REG SPI_nBits */ #define SPI_NBITS 0xc220UL #define SPI_NBITS_MSK 0x1fUL #define SPI_NBITS_OFST 0 /* REG DbitFIFOCTRLReg */ #define DBITFIFOCTRLREG 0xc000UL #define DBITRD 0x1UL #define DBITRD_MSK 0x1UL #define DBITRD_OFST 0 #define DBITRST 0x2UL #define DBITRST_MSK 0x2UL #define DBITRST_OFST 1 #define DBITFULL 0x4UL #define DBITFULL_MSK 0x4UL #define DBITFULL_OFST 2 #define DBITEMPTY 0x8UL #define DBITEMPTY_MSK 0x8UL #define DBITEMPTY_OFST 3 #define DBITUNDERFLOW 0x10UL #define DBITUNDERFLOW_MSK 0x10UL #define DBITUNDERFLOW_OFST 4 #define DBITOVERFLOW 0x20UL #define DBITOVERFLOW_MSK 0x20UL #define DBITOVERFLOW_OFST 5 /* REG DbitFIFODataReg1 */ #define DBITFIFODATAREG1 0xc004UL #define DBITFIFODATAREG1_PRESET 0x0UL /* REG DbitFIFODataReg2 */ #define DBITFIFODATAREG2 0xc008UL #define DBITFIFODATAREG2_PRESET 0x0UL /* REG MatterhornSPIReg1 */ #define MATTERHORNSPIREG1 0xc00cUL #define MATTERHORNSPIREG1_PRESET 0x0UL /* REG MatterhornSPIReg2 */ #define MATTERHORNSPIREG2 0xc010UL #define MATTERHORNSPIREG2_PRESET 0x0UL /* REG MatterhornSPICTRL */ #define MATTERHORNSPICTRL 0xc014UL #define CONFIGSTART_P 0x1UL #define CONFIGSTART_P_MSK 0x1UL #define CONFIGSTART_P_OFST 0 #define PERIPHERYRST_P 0x2UL #define PERIPHERYRST_P_MSK 0x2UL #define PERIPHERYRST_P_OFST 1 #define STARTREAD_P 0x4UL #define STARTREAD_P_MSK 0x4UL #define STARTREAD_P_OFST 2 #define BUSY 0x8UL #define BUSY_MSK 0x8UL #define BUSY_OFST 3 #define READOUTFROMASIC 0x10UL #define READOUTFROMASIC_MSK 0x10UL #define READOUTFROMASIC_OFST 4 /* REG MISO_select */ #define MISO_SELECT 0xc018UL #define MISO_SELECT_PRESET 0x0UL /* REG A_FIFO_Overflow_Status_Reg */ #define A_FIFO_OVERFLOW_STATUS_REG 0x9000UL #define A_FIFO_OVERFLOW_STATUS_REG_PRESET 0x0UL /* REG A_FIFO_Empty_Status_Reg */ #define A_FIFO_EMPTY_STATUS_REG 0x9004UL #define A_FIFO_EMPTY_STATUS_REG_PRESET 0x0UL /* REG A_FIFO_Full_Status_Reg */ #define A_FIFO_FULL_STATUS_REG 0x9008UL #define A_FIFO_FULL_STATUS_REG_PRESET 0x0UL /* REG D_FIFO_Overflow_Status_Reg */ #define D_FIFO_OVERFLOW_STATUS_REG 0x900cUL #define D_FIFO_OVERFLOW_STATUS 0x1UL #define D_FIFO_OVERFLOW_STATUS_MSK 0x1UL #define D_FIFO_OVERFLOW_STATUS_OFST 0 /* REG D_FIFO_Empty_Status_Reg */ #define D_FIFO_EMPTY_STATUS_REG 0x9010UL #define D_FIFO_EMPTY_STATUS 0x1UL #define D_FIFO_EMPTY_STATUS_MSK 0x1UL #define D_FIFO_EMPTY_STATUS_OFST 0 /* REG D_FIFO_Full_Status_Reg */ #define D_FIFO_FULL_STATUS_REG 0x9014UL #define D_FIFO_FULL_STATUS 0x1UL #define D_FIFO_FULL_STATUS_MSK 0x1UL #define D_FIFO_FULL_STATUS_OFST 0 /* REG X_FIFO_Overflow_Status_Reg */ #define X_FIFO_OVERFLOW_STATUS_REG 0x9018UL #define X_FIFO_OVERFLOW_STATUS_MSK 0xfUL #define X_FIFO_OVERFLOW_STATUS_OFST 0 /* REG X_FIFO_Empty_Status_Reg */ #define X_FIFO_EMPTY_STATUS_REG 0x901cUL #define X_FIFO_EMPTY_STATUS_MSK 0xfUL #define X_FIFO_EMPTY_STATUS_OFST 0 /* REG X_FIFO_Full_Status_Reg */ #define X_FIFO_FULL_STATUS_REG 0x9020UL #define X_FIFO_FULL_STATUS_MSK 0xfUL #define X_FIFO_FULL_STATUS_OFST 0 /* REG A_FIFO_Clean_Reg */ #define A_FIFO_CLEAN_REG 0x9024UL #define A_FIFO_CLEAN_REG_PRESET 0x0UL /* REG D_FIFO_Clean_Reg */ #define D_FIFO_CLEAN_REG 0x9028UL #define D_FIFO_CLEAN 0x1UL #define D_FIFO_CLEAN_MSK 0x1UL #define D_FIFO_CLEAN_OFST 0 /* REG X_FIFO_Clean_Reg */ #define X_FIFO_CLEAN_REG 0x902cUL #define X_FIFO_CLEAN_MSK 0xfUL #define X_FIFO_CLEAN_OFST 0 #endif /* __CHEBY__XCTB__H__ */ // ---------------------------------------------------- // TODO: fix these in the firmware reg generator: // ----------------------------------------------------: #define DELAY_OUT_REG_1 (0xB054) #define DELAY_OUT_REG_2 (0xB058) #define CYCLES_OUT_REG_1 (0xB05C) #define CYCLES_OUT_REG_2 (0xB060) #define FRAMES_OUT_REG_1 (0xB064) #define FRAMES_OUT_REG_2 (0xB068) #define PERIOD_OUT_REG_1 (0xB06C) #define PERIOD_OUT_REG_2 (0xB070) // clang-format on