#ifndef SLS_DETECTOR_DEFS_H #define SLS_DETECTOR_DEFS_H #ifdef __CINT__ #define MYROOT #define __cplusplus #endif //#include #include "sls_receiver_defs.h" /** maximum rois */ #define MAX_ROIS 100 /** maximum trim en */ #define MAX_TRIMEN 100 /** maximum unit size of program sent to detector */ #define MAX_FPGAPROGRAMSIZE (2 * 1024 *1024) typedef char mystring[MAX_STR_LENGTH]; typedef int dacs_t; #define DEFAULT_DET_MAC "00:aa:bb:cc:dd:ee" #define DEFAULT_DET_IP "129.129.202.46" /** \file sls_detector_defs.h This file contains all the basic definitions common to the slsDetector class and to the server programs running on the detector * @author Anna Bergamaschi * @version 0.1alpha (any string) * @see slsDetector */ /** get flag form most functions */ #define GET_FLAG -1 #ifdef __cplusplus /** @short class containing all the structures, constants and enum definitions */ class slsDetectorDefs: public virtual slsReceiverDefs{ public: slsDetectorDefs(){}; #endif /** @short structure for a detector module should not be used by unexperienced users \see :: moduleRegisterBit ::chipRegisterBit :channelRegisterBit @li reg is the module register (e.g. dynamic range? see moduleRegisterBit) @li dacs is the pointer to the array of dac values (in V) @li adcs is the pointer to the array of adc values (in V) @li chipregs is the pointer to the array of chip registers @li chanregs is the pointer to the array of channel registers @li gain is the module gain @li offset is the module offset */ typedef struct { int serialnumber; /**< is the module serial number */ int nchan; /**< is the number of channels on the module*/ int nchip; /**< is the number of chips on the module */ int ndac; /**< is the number of dacs on the module */ int nadc; /**< is the number of adcs on the module */ int reg; /**< is the module register (e.g. dynamic range?) \see moduleRegisterBit */ dacs_t *dacs; /**< is the pointer to the array of the dac values (in V) */ dacs_t *adcs; /**< is the pointer to the array of the adc values (in V) FLAT_FIELD_CORRECTION*/ int *chipregs; /**< is the pointer to the array of the chip registers \see ::chipRegisterBit */ int *chanregs; /**< is the pointer to the array of the channel registers \see ::channelRegisterBit */ double gain; /**< is the module gain (V/keV) */ double offset; /**< is the module offset (V) */ } sls_detector_module; /** network parameters */ enum networkParameter { DETECTOR_MAC, /**< detector MAC */ DETECTOR_IP, /**< detector IP */ RECEIVER_HOSTNAME, /**< receiver IP/hostname */ RECEIVER_UDP_IP, /**< receiever UDP IP */ RECEIVER_UDP_PORT, /**< receiever UDP Port */ RECEIVER_UDP_MAC, /**< receiever UDP MAC */ RECEIVER_UDP_PORT2, /**< receiever UDP Port of second half module for eiger */ DETECTOR_TXN_DELAY_LEFT, /**< transmission delay on the (left) port for next frame */ DETECTOR_TXN_DELAY_RIGHT, /**< transmission delay on the right port for next frame */ DETECTOR_TXN_DELAY_FRAME, /**< transmission delay of a whole frame for all the ports */ FLOW_CONTROL_10G, /**< flow control for 10GbE */ FLOW_CONTROL_WR_PTR, /**< memory write pointer for flow control */ FLOW_CONTROL_RD_PTR, /**< memory read pointer for flow control */ RECEIVER_STREAMING_PORT, /**< receiever streaming TCP(ZMQ) port */ CLIENT_STREAMING_PORT, /**< client streaming TCP(ZMQ) port */ RECEIVER_STREAMING_SRC_IP,/**< receiever streaming TCP(ZMQ) ip */ CLIENT_STREAMING_SRC_IP, /**< client streaming TCP(ZMQ) ip */ ADDITIONAL_JSON_HEADER, /**< additional json header (ZMQ) */ RECEIVER_UDP_SCKT_BUF_SIZE, /**< UDP socket buffer size */ RECEIVER_REAL_UDP_SCKT_BUF_SIZE /**< real UDP socket buffer size */ }; /** type of action performed (for text client) */ enum {GET_ACTION, PUT_ACTION, READOUT_ACTION, HELP_ACTION}; /** online flags enum \sa setOnline*/ enum {GET_ONLINE_FLAG=-1, /**< returns wether the detector is in online or offline state */ OFFLINE_FLAG=0, /**< detector in offline state (i.e. no communication to the detector - using only local structure - no data acquisition possible!) */ ONLINE_FLAG =1/**< detector in online state (i.e. communication to the detector updating the local structure) */ }; /** flags to get (or set) the size of the detector */ enum numberOf { MAXMODX, /***/ M_vIbias, /**< mythen 3 >*/ M_vIinSh, /**< mythen 3 >*/ M_VdcSh, /**< mythen 3 >*/ M_Vth2, /**< mythen 3 >*/ M_VPL, /**< mythen 3 >*/ M_Vth3, /**< mythen 3 >*/ M_casSh, /**< mythen 3 >*/ M_cas, /**< mythen 3 >*/ M_vIbiasSh, /**< mythen 3 >*/ M_vIcin, /**< mythen 3 >*/ M_vIpreOut, /**< mythen 3 >*/ V_POWER_A = 100, /**new chiptest board */ V_POWER_B = 101, /**new chiptest board */ V_POWER_C = 102, /**new chiptest board */ V_POWER_D = 103, /**new chiptest board */ V_POWER_IO =104, /**new chiptest board */ V_POWER_CHIP=105 ,/**new chiptest board */ I_POWER_A=106 , /**new chiptest board */ I_POWER_B=107 , /**new chiptest board */ I_POWER_C=108 , /**new chiptest board */ I_POWER_D=109 , /**new chiptest board */ I_POWER_IO=110 , /**new chiptest board */ V_LIMIT=111 /**new chiptest board */ }; /** detector settings indexes */ enum detectorSettings{ GET_SETTINGS=-1, /**< return current detector settings */ STANDARD, /**< standard settings */ FAST, /**< fast settings */ HIGHGAIN, /**< highgain settings */ DYNAMICGAIN, /**< dynamic gain settings */ LOWGAIN, /**< low gain settings */ MEDIUMGAIN, /**< medium gain settings */ VERYHIGHGAIN, /**< very high gain settings */ LOWNOISE, /**< low noise settings */ DYNAMICHG0, /**< dynamic high gain 0 */ FIXGAIN1, /**< fix gain 1 */ FIXGAIN2, /**< fix gain 2 */ FORCESWITCHG1, /**< force switch gain 1 */ FORCESWITCHG2, /**< force switch gain 2 */ VERYLOWGAIN, /**< very low gain settings */ UNDEFINED=200, /**< undefined or custom settings */ UNINITIALIZED /**< uninitialiazed (status at startup) */ }; #define TRIMBITMASK 0x3f /** important speed parameters */ enum speedVariable { CLOCK_DIVIDER, /**< readout clock divider */ PHASE_SHIFT, /**< adds phase shift */ OVERSAMPLING, /**< oversampling for analog detectors */ ADC_CLOCK, /**< adc clock divider */ ADC_PHASE, /**< adc clock phase */ ADC_PIPELINE, /**< adc pipeline */ DBIT_CLOCK, /**< adc clock divider */ DBIT_PHASE, /**< adc clock phase */ DBIT_PIPELINE /**< adc pipeline */ }; /** readout flags */ enum readOutFlags { GET_READOUT_FLAGS=-1, /**< return readout flags */ NORMAL_READOUT=0, /**< no flag */ STORE_IN_RAM=0x1, /**< data are stored in ram and sent only after end of acquisition for faster frame rate */ READ_HITS=0x2, /**< return only the number of the channel which counted ate least one */ ZERO_COMPRESSION=0x4,/**< returned data are 0-compressed */ PUMP_PROBE_MODE=0x8,/**