#ifndef SERVER_DEFS_H #define SERVER_DEFS_H #include "sls_detector_defs.h" #include #define GOODBYE (-200) /* Hardware Definitions */ #define NMAXMODY (1) #define NMAXMODX (1) #define NMAXMOD (NMAXMODX * NMAXMODY) #define NMODY (1) #define NMODX (1) #define NMOD (NMODX * NMODY) #define NCHAN (256 * 256) #define NCHIP (8) #define NADC (0) #define NDAC (8) #define NCHANS (NCHAN * NCHIP * NMAXMOD) #define NDACS (NDAC * NMAXMOD) #define DYNAMIC_RANGE (16) #define DATA_BYTES (NMAXMOD * NCHIP * NCHAN * 2) #define IP_PACKETSIZE (0x0522) /**carlos?? calcChecksum*/ #define UDP_PACKETSIZE (0x050E) /**carlos?? calcChecksum*/ #define CLK_EXPTIME (40) /** 0x28 better name? */ #define CLK_FC (20) /** 0x14 better name? */ #define CLK_FREQ 156.25E+6 /**carlos used in firmware_funcs.. but needed ?*/ /** Default Acqusition Parameters */ #define DEFAULT_NUM_FRAMES (1*1000*1000) #define DEFAULT_NUM_CYCLES (0) #define DEFAULT_EXPTIME (10*1000) #define DEFAULT_PERIOD (2*1000*1000) #define DEFAULT_DELAY (0) #define DEFAULT_NUM_GATES (0) #define DEFAULT_HIGH_VOLTAGE (0) /* Other Default Values */ //enum DACNAMES { VB_COMP, VDD_PROT, VIN_COM, VREF_PRECH, VB_PIXBUF, VB_DS, VREF_DS, VREF_COMP }; #define DEFAULT_DAC_VALS { 1220, 3000, 1053, 1450, 750, 1000, 480, 420 }; enum adcVals {TEMP_FPGA, TEMP_ADC}; #define DEFAULT_SETTINGS (DYNAMICGAIN) #define DEFAULT_TX_UDP_PORT (0x7e9a) /* Defines in the Firmware */ #define FIX_PATT_VAL (0xACDC2014) #define ADC_PORT_INVERT_VAL (0x453b2a9c) #define ADC_OFST_HALF_SPEED_VAL (0x20) #define ADC_OFST_QUARTER_SPEED_VAL (0x10) #define SAMPLE_ADC_HALF_SPEED (0x7f7c) #define SAMPLE_ADC_QUARTER_SPEED (0x8981) #define DAQ_HALF_SPEED (0x0) #define DAQ_QUARTER_SPEED (0xf) #define ADC_PHASE_HALF_SPEED (0x41) #define ADC_PHASE_QUARTER_SPEED (0x19) /* Maybe not required for jungfrau */ #define NTRIMBITS (6) #define NCOUNTBITS (24) #define NCHIPS_PER_ADC (2) #define TRIM_DR (((int)pow(2,NTRIMBITS))-1) #define COUNT_DR (((int)pow(2,NCOUNTBITS))-1) #define ALLMOD (0xffff) #define ALLFIFO (0xffff) /* LTC2620 DAC DEFINES */ #define LTC2620_DAC_CMD_OFST (20) #define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST) #define LTC2620_DAC_ADDR_OFST (16) #define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST) #define LTC2620_DAC_DATA_OFST (4) #define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST) #define LTC2620_DAC_CMD_WRITE (0x00000000 << LTC2620_DAC_CMD_OFST) #define LTC2620_DAC_CMD_SET (0x00000003 << LTC2620_DAC_CMD_OFST) #define LTC2620_DAC_CMD_POWER_DOWN (0x00000004 << LTC2620_DAC_CMD_OFST) #define LTC2620_DAC_NUMBITS (24) /* MAX1932 HV DEFINES */ #define MAX1932_HV_NUMBITS (8) #define MAX1932_HV_DATA_OFST (0) #define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST) /* AD9257 ADC DEFINES */ #define AD9257_ADC_NUMBITS (24) #define AD9257_DEV_IND_2_REG (0x04) #define AD9257_CHAN_H_OFST (0) #define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST) #define AD9257_CHAN_G_OFST (1) #define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST) #define AD9257_CHAN_F_OFST (2) #define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST) #define AD9257_CHAN_E_OFST (3) #define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST) #define AD9257_DEV_IND_1_REG (0x05) #define AD9257_CHAN_D_OFST (0) #define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST) #define AD9257_CHAN_C_OFST (1) #define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST) #define AD9257_CHAN_B_OFST (2) #define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST) #define AD9257_CHAN_A_OFST (3) #define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST) #define AD9257_CLK_CH_DCO_OFST (4) #define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST) #define AD9257_CLK_CH_IFCO_OFST (5) #define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST) #define AD9257_POWER_MODE_REG (0x08) #define AD9257_POWER_INTERNAL_OFST (0) #define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST) #define AD9257_INT_RESET_VAL (0x3) #define AD9257_INT_CHIP_RUN_VAL (0x0) #define AD9257_POWER_EXTERNAL_OFST (5) #define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST) #define AD9257_EXT_FULL_POWER_VAL (0x0) #define AD9257_EXT_STANDBY_VAL (0x1) #define AD9257_OUT_MODE_REG (0x14) #define AD9257_OUT_FORMAT_OFST (0) #define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST) #define AD9257_OUT_BINARY_OFST_VAL (0) #define AD9257_OUT_TWOS_COMPL_VAL (1) #define AD9257_OUT_LVDS_OPT_OFST (6) #define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST) #define AD9257_OUT_LVDS_ANSI_VAL (0) #define AD9257_OUT_LVDS_IEEE_VAL (1) #define AD9257_OUT_PHASE_REG (0x16) #define AD9257_OUT_CLK_OFST (0) #define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST) #define AD9257_OUT_CLK_60_VAL (0x1) #define AD9257_IN_CLK_OFST (4) #define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST) #define AD9257_IN_CLK_0_VAL (0x0) #define AD9257_VREF_REG (0x18) #define AD9257_VREF_OFST (0) #define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST) #define AD9257_VREF_1_33_VAL (0x2) #define AD9257_TEST_MODE_REG (0x0D) #define AD9257_OUT_TEST_OFST (0) #define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST) #define AD9257_NONE_VAL (0x0) #define AD9257_MIXED_BIT_FREQ_VAL (0xC) #define AD9257_TEST_RESET_SHORT_GEN (4) #define AD9257_TEST_RESET_LONG_GEN (5) #define AD9257_USER_IN_MODE_OFST (6) #define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST) #endif