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Trim

.clang-format

@@ -4,3 +4,4 @@ IndentWidth: 4
 UseTab: Never
 ColumnLimit: 80
 AlignConsecutiveAssignments: false 
+AlignConsecutiveMacros: true

CMakeLists.txt

@@ -46,6 +46,21 @@ option(SLS_BUILD_DOCS "docs" OFF)
 option(SLS_BUILD_EXAMPLES "examples" OFF)
 option(SLS_TUNE_LOCAL "tune to local machine" OFF)
 
+# set(ClangFormat_BIN_NAME clang-format)
+set(ClangFormat_EXCLUDE_PATTERNS  "build/" 
+                                    "libs/" 
+                                    "slsDetectorCalibration/" 
+                                    "ctbGui/" 
+                                    "manual/"
+                                    "python/"
+                                    "sample/"
+                                    ${CMAKE_BINARY_DIR})
+find_package(ClangFormat)
+
+#Enable LTO if available
+check_ipo_supported(RESULT SLS_LTO_AVAILABLE)
+
+
 # Use ld.gold if it is available and isn't disabled explicitly
 option(SLS_USE_LD_GOLD "Use GNU gold linker" ON)
 if (SLS_USE_LD_GOLD)

cmake/FindClangFormat.cmake

@@ -0,0 +1,39 @@
+# Find Clang format
+if(NOT ClangFormat_BIN_NAME)
+	set(ClangFormat_BIN_NAME clang-format)
+endif()
+
+# if custom path check there first
+if(ClangFormat_ROOT_DIR)
+    find_program(ClangFormat_BIN 
+        NAMES
+        ${ClangFormat_BIN_NAME}
+        PATHS
+        "${ClangFormat_ROOT_DIR}"
+        NO_DEFAULT_PATH)
+endif()
+
+find_program(ClangFormat_BIN NAMES ${ClangFormat_BIN_NAME})
+
+include(FindPackageHandleStandardArgs)
+FIND_PACKAGE_HANDLE_STANDARD_ARGS(
+    ClangFormat
+    DEFAULT_MSG 
+    ClangFormat_BIN)
+
+mark_as_advanced(
+    ClangFormat_BIN)
+
+if(ClangFormat_FOUND)
+    exec_program(${ClangFormat_BIN} ${CMAKE_CURRENT_SOURCE_DIR} ARGS --version OUTPUT_VARIABLE CLANG_VERSION_TEXT)
+    string(REGEX MATCH "([0-9]+)\\.[0-9]+\\.[0-9]+" CLANG_VERSION ${CLANG_VERSION_TEXT})
+    if((${CLANG_VERSION} GREATER "9") OR (${CLANG_VERSION} EQUAL "9"))
+        # A CMake script to find all source files and setup clang-format targets for them
+        message(STATUS "found clang-format \"${CLANG_VERSION}\" adding formatting targets")
+        include(clang-format)
+    else()
+        message(STATUS "clang-format version \"${CLANG_VERSION}\" found but need at least 9. Not setting up format targets")
+    endif()
+else()
+    message(STATUS "clang-format not found. Not setting up format targets")
+endif()

cmake/clang-format.cmake

@@ -0,0 +1,47 @@
+# A CMake script to find all source files and setup clang-format targets for them
+
+# Find all source files
+set(ClangFormat_CXX_FILE_EXTENSIONS ${ClangFormat_CXX_FILE_EXTENSIONS} *.cpp *.h *.cxx *.hxx *.hpp *.cc *.ipp *.c)
+file(GLOB_RECURSE ALL_SOURCE_FILES ${ClangFormat_CXX_FILE_EXTENSIONS})
+
+# Don't include some common build folders
+set(ClangFormat_EXCLUDE_PATTERNS ${ClangFormat_EXCLUDE_PATTERNS} "/CMakeFiles/" "cmake")
+
+# get all project files file
+foreach (SOURCE_FILE ${ALL_SOURCE_FILES}) 
+    foreach (EXCLUDE_PATTERN ${ClangFormat_EXCLUDE_PATTERNS})
+        string(FIND ${SOURCE_FILE} ${EXCLUDE_PATTERN} EXCLUDE_FOUND) 
+        if (NOT ${EXCLUDE_FOUND} EQUAL -1) 
+            list(REMOVE_ITEM ALL_SOURCE_FILES ${SOURCE_FILE})
+        endif () 
+    endforeach ()
+endforeach ()
+
+#target for formatting soruce files
+add_custom_target(format
+    COMMENT "Running clang-format to change files"
+    COMMAND ${ClangFormat_BIN}
+    -style=file
+    -i
+    ${ALL_SOURCE_FILES}
+)
+
+
+#target to check format on source files 
+add_custom_target(format-check
+    COMMENT "Checking clang-format changes"
+    # Use ! to negate the result for correct output
+    COMMAND !
+    ${ClangFormat_BIN}
+    -style=file
+    -output-replacements-xml
+    ${ALL_SOURCE_FILES}
+    | grep -q "replacement offset" 
+)
+
+# debug to check which file will be formatted
+add_custom_target(
+    listformatfiles
+    COMMAND
+    echo ${ALL_SOURCE_FILES}
+)

ctbGui/patternGenerator/generate.sh

@@ -21,6 +21,7 @@ if [ -f "$infile" ]
 then
 gcc -DINFILE="\"$infile\"" -DOUTFILE="\"$outfile\""  -DOUTFILEBIN="\"$outfilebin\"" -o $exe generator.c ; 
 echo compiling
+echo gcc -DINFILE="\"$infile\"" -DOUTFILE="\"$outfile\""  -DOUTFILEBIN="\"$outfilebin\"" -o $exe generator.c ; 
 $exe ; 
 echo cleaning
 rm $exe

docs/src/gendoc.cpp

@@ -9,7 +9,6 @@
 #include <string>
 #include <vector>
 
-
 #include "CmdProxy.h"
 #include "Detector.h"
 #include "sls_detector_defs.h"
@@ -52,5 +51,4 @@ int main() {
         auto help = replace_all(tmp, "\n\t", "\n\t\t");
         fs << '\t' << cmd << usage << help << "\n";
     }
-
 }

integrationTests/test-eigerIntegration.cpp

@@ -1,5 +1,5 @@
-#include "catch.hpp"
 #include "DetectorImpl.h"
+#include "catch.hpp"
 #include "string_utils.h"
 #include "tests/globals.h"
 #include <iostream>

integrationTests/test-integrationDectector.cpp

@@ -2,9 +2,9 @@
 #include "catch.hpp"
 
 #include "ClientSocket.h"
-#include "logger.h"
 #include "DetectorImpl.h"
 #include "Module.h"
+#include "logger.h"
 #include "sls_detector_defs.h"
 
 #include "Timer.h"
@@ -79,7 +79,6 @@ TEST_CASE("Set control port then create a new object with this control port",
     d.freeSharedMemory();
 }
 
-
 TEST_CASE("single EIGER detector no receiver basic set and get",
           "[.integration][eiger]") {
     // TODO! this test should take command line arguments for config
@@ -130,8 +129,6 @@ TEST_CASE("single EIGER detector no receiver basic set and get",
     d.freeSharedMemory();
 }
 
-
-
 TEST_CASE("Locking mechanism and last ip", "[.integration][.single]") {
     Module d(test::type);
     d.setHostname(test::hostname);
@@ -160,7 +157,6 @@ TEST_CASE("Set settings", "[.integration][.single]"){
     CHECK(d.setSettings(defs::STANDARD) == defs::STANDARD);
 }
 
-
 TEST_CASE("Timer functions", "[.integration][cli]") {
     // FRAME_NUMBER, /**< number of real time frames: total number of
     // acquisitions is number or frames*number of triggers */ ACQUISITION_TIME,
@@ -204,8 +200,7 @@ TEST_CASE("Timer functions", "[.integration][cli]") {
     if (test::type != dt::EIGER) {
         auto delay = 10000;
         d.setDelayAfterTrigger(delay);
-        CHECK(d.getDelayAfterTrigger() ==
-              delay);
+        CHECK(d.getDelayAfterTrigger() == delay);
     }
 
     auto triggers = 2;
@@ -221,7 +216,6 @@ TEST_CASE("Timer functions", "[.integration][cli]") {
     d.startAndReadAll();
 
     d.freeSharedMemory();
-
 }
 
 // TEST_CASE("Aquire", "[.integration][eiger]"){
@@ -382,8 +376,8 @@ TEST_CASE("Chiptestboard Loading Patterns", "[.ctbintegration]") {
     }
 }
 
-
-TEST_CASE("Chiptestboard Dbit offset, list, sampling, advinvert", "[.ctbintegration][dbit]") {
+TEST_CASE("Chiptestboard Dbit offset, list, sampling, advinvert",
+          "[.ctbintegration][dbit]") {
     SingleDetectorConfig c;
 
     // pick up multi detector from shm id 0
@@ -450,17 +444,20 @@ TEST_CASE("Chiptestboard Dbit offset, list, sampling, advinvert", "[.ctbintegrat
     m.setExternalSampling(1);
     CHECK(m.getExternalSampling() == 1);
     CHECK(m.readRegister(0x7b) == 0x1003E);
-    
 }
 
-TEST_CASE("Eiger or Jungfrau startingfnum", "[.eigerintegration][.jungfrauintegration][startingfnum]") {
+TEST_CASE("Eiger or Jungfrau startingfnum",
+          "[.eigerintegration][.jungfrauintegration][startingfnum]") {
     SingleDetectorConfig c;
 
     // pick up multi detector from shm id 0
     DetectorImpl m(0);
 
     // ensure ctb detector type, hostname and online
-    REQUIRE(((m.getDetectorTypeAsEnum() == slsDetectorDefs::detectorType::EIGER) || (m.getDetectorTypeAsEnum() == slsDetectorDefs::detectorType::JUNGFRAU)));
+    REQUIRE(
+        ((m.getDetectorTypeAsEnum() == slsDetectorDefs::detectorType::EIGER) ||
+         (m.getDetectorTypeAsEnum() ==
+          slsDetectorDefs::detectorType::JUNGFRAU)));
     REQUIRE(m.getHostname() == c.hostname);
 
     CHECK(m.setNumberOfFrames(1) == 1);
@@ -498,7 +495,8 @@ TEST_CASE("Eiger readnlines", "[.eigerintegration][readnlines]") {
     DetectorImpl m(0);
 
     // ensure detector type, hostname
-    REQUIRE((m.getDetectorTypeAsEnum() == slsDetectorDefs::detectorType::EIGER));
+    REQUIRE(
+        (m.getDetectorTypeAsEnum() == slsDetectorDefs::detectorType::EIGER));
     REQUIRE(m.getHostname() == c.hostname);
 
     m.setDynamicRange(16);

integrationTests/test-integrationMulti.cpp

@@ -1,5 +1,5 @@
-#include "catch.hpp"
 #include "DetectorImpl.h"
+#include "catch.hpp"
 #include "string_utils.h"
 #include "tests/globals.h"
 #include <iostream>
@@ -24,8 +24,6 @@ TEST_CASE("Initialize a multi detector", "[.integration][.multi]") {
     d.freeSharedMemory();
 }
 
-
-
 TEST_CASE("Set and read timers", "[.integration][.multi]") {
 
     DetectorImpl d(0, true, true);
@@ -57,7 +55,6 @@ TEST_CASE("Set and read timers", "[.integration][.multi]") {
     // PROGRESS, /**< fraction of measurement elapsed - only get! */
     // MEASUREMENTS_NUMBER,
 
-
     // FRAMES_FROM_START,
     // FRAMES_FROM_START_PG,
     // SAMPLES,
@@ -78,7 +75,6 @@ TEST_CASE("Set and read timers", "[.integration][.multi]") {
         CHECK(d.setSubFrameExposureDeadTime(-1) == Approx(subframe_deadtime));
     }
 
-    
     if (test::type == dt::EIGER) {
         // 32bit is needed for subframe exposure
         d.setDynamicRange(32);

python/slsdet/detector.py

@@ -160,6 +160,13 @@ class Detector(CppDetectorApi):
     def frames(self, n_frames):
         self.setNumberOfFrames(n_frames)
 
+    @property
+    def triggers(self):
+        return element_if_equal(self.getNumberOfTriggers())
+
+    @triggers.setter
+    def triggers(self, n_triggers):
+        self.setNumberOfTriggers(n_triggers)
 
     @property
     def exptime(self):

slsDetectorCalibration/dataStructures/moench04CtbZmq10GbData.h

@@ -156,7 +156,7 @@ class moench04CtbZmq10GbData : public slsDetectorData<uint16_t> {
     if (dSamples>isample) {
       ptr=data+32*(isample+1)+8*isample;
       sample=*((uint64_t*)ptr);
-    cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
+      // cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
     if (sample & (1<<ibit[isc]))
       return 1;
     else

slsDetectorCalibration/dataStructures/moench04CtbZmqData.h

@@ -120,7 +120,7 @@ class moench04CtbZmqData : public slsDetectorData<uint16_t> {
     if (dSamples>isample) {
       ptr=data+aoff+8*isample;
       sample=*((uint64_t*)ptr);
-    cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
+      // cout << isc << " " << ibit[isc] << " " << isample << hex << sample << dec << endl;
     if (sample & (1<<ibit[isc]))
       return 1;
     else

slsDetectorCalibration/moenchExecutables/Makefile.zmq

@@ -5,12 +5,15 @@ LDFLAG= -L/usr/lib64/ -lpthread -lm  -lstdc++  -lzmq -pthread -lrt -ltiff   -O3
 
 #DESTDIR?=../bin
 
-all:  moenchZmqProcess 
+all:  moenchZmqProcess moenchZmq04Process
  #moenchZmqProcessCtbGui
 
 moenchZmqProcess:  moenchZmqProcess.cpp   clean
 		      g++ -o moenchZmqProcess  moenchZmqProcess.cpp  $(LDFLAG) $(INCDIR) $(LIBHDF5) $(LIBRARYCBF)  -DNEWZMQ -DINTERP 
 
+moenchZmq04Process:  moenchZmqProcess.cpp   clean
+		      g++ -o moench04ZmqProcess  moenchZmqProcess.cpp  $(LDFLAG) $(INCDIR) $(LIBHDF5) $(LIBRARYCBF)  -DNEWZMQ -DINTERP -DMOENCH04 
+
 #moenchZmqProcessCtbGui:  moenchZmqProcess.cpp   clean
 #		      g++ -o moenchZmqProcessCtbGui  moenchZmqProcess.cpp  $(LDFLAG) $(INCDIR) $(LIBHDF5) $(LIBRARYCBF)  -DNEWZMQ -DINTERP -DCTBGUI
 

slsDetectorCalibration/moenchExecutables/moenchZmqProcess.cpp

@@ -8,7 +8,13 @@
 #include "sls_detector_defs.h"
 #include "ZmqSocket.h"
 #ifndef RECT
+#ifndef MOENCH04
 #include "moench03T1ZmqDataNew.h"
+#endif
+#ifdef MOENCH04
+#include "moench04CtbZmq10GbData.h"
+#endif
+
 #endif
 #ifdef RECT
 #include "moench03T1ZmqDataNewRect.h"
@@ -73,6 +79,10 @@ int main(int argc, char *argv[]) {
   char* socketip2 = 0;
   uint32_t portnum2 = 0;
 
+  zmqHeader zHeader, outHeader;
+  zHeader.jsonversion = SLS_DETECTOR_JSON_HEADER_VERSION;
+  outHeader.jsonversion = SLS_DETECTOR_JSON_HEADER_VERSION;
+
   uint32_t nSigma=5;
 
   int ok;
@@ -124,7 +134,12 @@ int main(int argc, char *argv[]) {
   }
 
   //slsDetectorData *det=new moench03T1ZmqDataNew(); 
+#ifndef MOENCH04
   moench03T1ZmqDataNew *det=new moench03T1ZmqDataNew(); 
+#endif
+#ifdef MOENCH04
+  moench04CtbZmq10GbData *det=new moench04CtbZmq10GbData(); 
+#endif
   cout << endl << " det" <<endl;
   int npx, npy;
   det->getDetectorSize(npx, npy);
@@ -140,13 +155,15 @@ int main(int argc, char *argv[]) {
   char dummybuff[size];
   
 
-  int ncol_cm=CM_ROWS;
-  double xt_ghost=C_GHOST;
   moench03CommonMode *cm=NULL;
   moench03GhostSummation *gs=NULL;
 #ifdef CORR
-  cm=new moench03CommonMode(ncol_cm);
-  gs=new moench03GhostSummation(det, xt_ghost);
+  
+  //int ncol_cm=CM_ROWS;
+  //double xt_ghost=C_GHOST;
+
+  cm=new moench03CommonMode(CM_ROWS);
+  gs=new moench03GhostSummation(det, C_GHOST);
 #endif
   double *gainmap=NULL;
   float *gm;
@@ -308,9 +325,10 @@ int main(int argc, char *argv[]) {
 	uint64_t bunchId = 0;
 	uint64_t timestamp = 0;
 	int16_t modId = 0;
+	uint32_t expLength=0;
 	uint16_t xCoord = 0;
 	uint16_t yCoord = 0;
-	uint16_t zCoord = 0;
+	//uint16_t zCoord = 0;
 	uint32_t debug = 0;
 	//uint32_t dr = 16;
 	//int16_t *dout;//=new int16_t [nnx*nny];
@@ -341,6 +359,7 @@ int main(int argc, char *argv[]) {
 	filter->getImageSize(nnx, nny,nnsx, nnsy);
 
 	
+	std::map<std::string, std::string> addJsonHeader;
 
 
 
@@ -350,16 +369,13 @@ int main(int argc, char *argv[]) {
 
 	  //  cout << "+++++++++++++++++++++++++++++++LOOP" << endl;
 		// get header, (if dummy, fail is on parse error or end of acquisition)
-#ifndef NEWZMQ	
-	  if (!zmqsocket->ReceiveHeader(0, acqIndex, frameIndex, subframeIndex, filename, fileindex)){
-#endif
 
-#ifdef NEWZMQ	
-	    rapidjson::Document doc;
-	    if (!zmqsocket->ReceiveHeader(0, doc, SLS_DETECTOR_JSON_HEADER_VERSION)) {
+
+
+	  //  rapidjson::Document doc;
+	    if (!zmqsocket->ReceiveHeader(0, zHeader, SLS_DETECTOR_JSON_HEADER_VERSION)) {
 	      /* zmqsocket->CloseHeaderMessage();*/
 
-#endif
 	    //	  if (!zmqsocket->ReceiveHeader(0, acqIndex, frameIndex, subframeIndex, filename, fileindex)) {
 	       cprintf(RED, "Got Dummy\n");
 	      //   t1=high_resolution_clock::now();
@@ -378,7 +394,11 @@ int main(int argc, char *argv[]) {
 	    if (newFrame>0) {
 	      cprintf(RED,"DIDn't receive any data!\n");
 	    if (send) { 
-	      zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
+	      
+	      //zHeader.data = false;
+	      outHeader.data=false;
+	      //  zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
+	      zmqsocket2->SendHeader(0,outHeader);
 	      cprintf(RED, "Sent Dummy\n");
 	    }
 	    } else {
@@ -510,14 +530,39 @@ int main(int argc, char *argv[]) {
 
 	    if(send_something) {
 	   
- 	    zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);   
+	      //  zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);   
 	      
+	      outHeader.data=true;
+	      outHeader.dynamicRange=dr;
+	      outHeader.fileIndex=fileindex;
+	      outHeader.ndetx=1;
+	      outHeader.ndety=1;
+	      outHeader.npixelsx=nnx;
+	      outHeader.npixelsy=nny;
+	      outHeader.imageSize=nnx*nny*dr/8;
+	      outHeader.acqIndex=acqIndex;
+	      outHeader.frameIndex=frameIndex;
+	      outHeader.fname=fname;
+	      outHeader.frameNumber=acqIndex;
+	      outHeader.expLength=expLength;
+	      outHeader.packetNumber=packetNumber;
+	      outHeader.bunchId=bunchId;
+	      outHeader.timestamp=timestamp;
+	      outHeader.modId=modId;
+	      outHeader.row=xCoord;
+	      outHeader.column=yCoord;
+	      outHeader.debug=debug;
+	      outHeader.roundRNumber=roundRNumber;
+	      outHeader.detType=detType;
+	      outHeader.version=version;
 	      
+	      zmqsocket2->SendHeader(0,outHeader);
 	      zmqsocket2->SendData((char*)dout,nnx*nny*dr/8);
 	      cprintf(GREEN, "Sent Data\n");
 	    }
-	    
-	    zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
+	    outHeader.data=false;
+	    zmqsocket2->SendHeader(0,outHeader);
+	    // zmqsocket2->SendHeaderData(0, true, SLS_DETECTOR_JSON_HEADER_VERSION);
 	    cprintf(RED, "Sent Dummy\n");
 	    if (dout)
 	      delete [] dout;
@@ -544,33 +589,84 @@ int main(int argc, char *argv[]) {
 
 	    }
 
-#ifdef NEWZMQ
+	    //#ifdef NEWZMQ
 	    if (newFrame) {
 	      begin = std::chrono::steady_clock::now();
-    //time(&begin);
-	      // t0 = high_resolution_clock::now();
-	      //cout <<"new frame" << endl;
    
-	      //  acqIndex, frameIndex, subframeIndex, filename, fileindex
-	      size       = doc["size"].GetUint();
-	      // multisize  = size;// * zmqsocket->size();
-	      // dynamicRange  = doc["bitmode"].GetUint();
-	      //  nPixelsX = doc["shape"][0].GetUint();
-	      // nPixelsY = doc["shape"][1].GetUint();
-	      filename        = doc["fname"].GetString();
-	      //acqIndex = doc["acqIndex"].GetUint64();
-	      //frameIndex       = doc["fIndex"].GetUint64();
-	      fileindex        = doc["fileIndex"].GetUint64();
-	      //subFrameIndex    = doc["expLength"].GetUint();
-	      //packetNumber=doc["packetNumber"].GetUint();
-	      //bunchId=doc["bunchId"].GetUint();
-	      //timestamp=doc["timestamp"].GetUint();
-	      //modId=doc["modId"].GetUint();
-	      //debug=doc["debug"].GetUint();
-	      //roundRNumber=doc["roundRNumber"].GetUint();
-	      //detType=doc["detType"].GetUint();
-	      //version=doc["version"].GetUint();
+	      size       = zHeader.imageSize;//doc["size"].GetUint();
 	      
+	      // dynamicRange  = zheader.dynamicRange; //doc["bitmode"].GetUint();
+	      // nPixelsX = zHeader.npixelsx; //doc["shape"][0].GetUint();
+	      // nPixelsY = zHeader.npixelsy;// doc["shape"][1].GetUint();
+	      filename        = zHeader.fname;//doc["fname"].GetString();
+	      acqIndex = zHeader.acqIndex; //doc["acqIndex"].GetUint64();
+		// frameIndex       = zHeader.frameIndex;//doc["fIndex"].GetUint64();
+	      fileindex        = zHeader.fileIndex;//doc["fileIndex"].GetUint64();
+	      expLength   = zHeader.expLength;//doc["expLength"].GetUint();
+	      packetNumber=zHeader.packetNumber;//doc["packetNumber"].GetUint();
+	      bunchId=zHeader.bunchId;//doc["bunchId"].GetUint();
+	      timestamp=zHeader.timestamp;//doc["timestamp"].GetUint();
+	      modId=zHeader.modId;//doc["modId"].GetUint();
+	      debug=zHeader.debug;//doc["debug"].GetUint();
+	      //  roundRNumber=r.roundRNumber;//doc["roundRNumber"].GetUint();
+	      detType=zHeader.detType;//doc["detType"].GetUint();
+	      version=zHeader.version;//doc["version"].GetUint();
+	      /*document["bitmode"].GetUint(); zHeader.dynamicRange
+
+document["fileIndex"].GetUint64(); zHeader.fileIndex
+
+document["detshape"][0].GetUint();
+zHeader.ndetx
+
+document["detshape"][1].GetUint();
+zHeader.ndety
+
+document["shape"][0].GetUint();
+zHeader.npixelsx
+
+document["shape"][1].GetUint();
+zHeader.npixelsy
+
+document["size"].GetUint(); zHeader.imageSize
+
+document["acqIndex"].GetUint64(); zHeader.acqIndex
+
+document["frameIndex"].GetUint64(); zHeader.frameIndex
+
+document["fname"].GetString(); zHeader.fname
+
+document["frameNumber"].GetUint64(); zHeader.frameNumber
+
+document["expLength"].GetUint(); zHeader.expLength
+
+document["packetNumber"].GetUint(); zHeader.packetNumber
+
+document["bunchId"].GetUint64(); zHeader.bunchId
+
+document["timestamp"].GetUint64(); zHeader.timestamp
+
+document["modId"].GetUint(); zHeader.modId
+
+document["row"].GetUint(); zHeader.row
+
+document["column"].GetUint(); zHeader.column
+
+document["reserved"].GetUint(); zHeader.reserved
+
+document["debug"].GetUint(); zHeader.debug
+
+document["roundRNumber"].GetUint(); zHeader.roundRNumber
+
+document["detType"].GetUint(); zHeader.detType
+
+document["version"].GetUint(); zHeader.version
+
+document["flippedDataX"].GetUint(); zHeader.flippedDataX
+
+document["quad"].GetUint(); zHeader.quad
+
+document["completeImage"].GetUint(); zHeader.completeImage
+	      */
 	      //dataSize=size;
 
 	      //strcpy(fname,filename.c_str());
@@ -604,6 +700,8 @@ int main(int argc, char *argv[]) {
 	      // 	      xCoord, yCoord,zCoord,
 	      // 	      flippedDataX, packetNumber, bunchId, timestamp, modId, debug, roundRNumber, detType, version);
 	      
+	      addJsonHeader=zHeader.addJsonHeader;
+
 	      /* Analog detector commands */
 	      //isPedestal=0;
 	      //isFlat=0;
@@ -611,9 +709,10 @@ int main(int argc, char *argv[]) {
 	      fMode=eFrame;
 	      frameMode_s="frame";
 	      cprintf(MAGENTA, "Frame mode: ");
-	      if (doc.HasMember("frameMode")) {
-		if (doc["frameMode"].IsString()) {
-		  frameMode_s=doc["frameMode"].GetString();
+	      //	      if (doc.HasMember("frameMode")) {
+	      if (addJsonHeader.find("frameMode")!= addJsonHeader.end()) { 
+		//	if (doc["frameMode"].IsString()) {
+		frameMode_s=addJsonHeader.at("frameMode");//doc["frameMode"].GetString();
 		  if (frameMode_s == "pedestal"){
 		    fMode=ePedestal;
 		    //isPedestal=1;
@@ -639,7 +738,7 @@ int main(int argc, char *argv[]) {
 		     cprintf(MAGENTA, "Resetting flatfield\n");
 		     fMode=eFlat;
 		   }
-#endif
+		  //#endif
 		  else {
 		    fMode=eFrame;
 		    //isPedestal=0;
@@ -647,19 +746,23 @@ int main(int argc, char *argv[]) {
 		    fMode=eFrame;
 		    frameMode_s="frame";
 		  }
-		}
+		  //}
 	      }
 	      cprintf(MAGENTA, "%s\n" , frameMode_s.c_str());
 	      mt->setFrameMode(fMode);
 
 	      // threshold=0;
 	      cprintf(MAGENTA, "Threshold: "); 
-	      if (doc.HasMember("threshold")) {	
-		if (doc["threshold"].IsInt()) {
-		  threshold=doc["threshold"].GetInt();
+	      if (addJsonHeader.find("threshold")!= addJsonHeader.end()) {
+		istringstream(addJsonHeader.at("threshold")) >>threshold;
+		//		threshold=atoi(addJsonHeader.at("threshold").c_str());//doc["frameMode"].GetString();
+	      }
+	      //if (doc.HasMember("threshold")) {	
+	      //if (doc["threshold"].IsInt()) {
+	      //  threshold=doc["threshold"].GetInt();
 	      mt->setThreshold(threshold);
-		}
-	      }	
+	      //	}
+	      // }	
 	      cprintf(MAGENTA, "%d\n", threshold);
 
 	      xmin=0;
@@ -667,40 +770,47 @@ int main(int argc, char *argv[]) {
 	      ymin=0;
 	      ymax=npy;
 	      cprintf(MAGENTA, "ROI: ");
-	      if (doc.HasMember("roi")) {
-		if (doc["roi"].IsArray()) {
-		  if (doc["roi"].Size() > 0 )
-		    if (doc["roi"][0].IsInt())
-		      xmin=doc["roi"][0].GetInt();
 	      
-		  if (doc["roi"].Size() > 1 )
-		    if (doc["roi"][1].IsInt())
-		      xmax=doc["roi"][1].GetInt();
+	      if (addJsonHeader.find("roi")!= addJsonHeader.end()) {
+		istringstream(addJsonHeader.at("roi")) >> xmin >> xmax >> ymin >> ymax ;
+		//  if (doc.HasMember("roi")) {
+		//if (doc["roi"].IsArray()) {
+		// if (doc["roi"].Size() > 0 )
+		//  if (doc["roi"][0].IsInt())
+		   //    xmin=doc["roi"][0].GetInt();
 		  
-		  if (doc["roi"].Size() > 2 )
-		    if (doc["roi"][2].IsInt())
-		      ymin=doc["roi"][2].GetInt();
+		//   if (doc["roi"].Size() > 1 )
+		//     if (doc["roi"][1].IsInt())
+		//       xmax=doc["roi"][1].GetInt();
 
-		  if (doc["roi"].Size() > 3 )
-		    if (doc["roi"][3].IsInt())
-		      ymax=doc["roi"][3].GetInt();
-		}
+		//   if (doc["roi"].Size() > 2 )
+		//     if (doc["roi"][2].IsInt())
+		//       ymin=doc["roi"][2].GetInt();
+		  
+		//   if (doc["roi"].Size() > 3 )
+		//     if (doc["roi"][3].IsInt())
+		//       ymax=doc["roi"][3].GetInt();
+		// }
 	      }
 
 	      cprintf(MAGENTA, "%d %d %d %d\n", xmin, xmax, ymin, ymax);
 	      mt->setROI(xmin, xmax, ymin, ymax);	
-	
-	      if (doc.HasMember("dynamicRange")) {
-		dr=doc["dynamicRange"].GetUint();
+	      if (addJsonHeader.find("dynamicRange")!= addJsonHeader.end()) {
+		istringstream(addJsonHeader.at("dynamicRange")) >> dr ;
 		dr=32;
 	      }
+	      // if (doc.HasMember("dynamicRange")) {
+	      // 	dr=doc["dynamicRange"].GetUint();
+	      // 	dr=32;
+	      // }
 
 	      dMode=eAnalog;
 	      detectorMode_s="analog";
 	      cprintf(MAGENTA, "Detector mode: ");	  
-	      if (doc.HasMember("detectorMode")) {
-		if (doc["detectorMode"].IsString()) {
-		    detectorMode_s=doc["detectorMode"].GetString();
+		if (addJsonHeader.find("detectorMode")!= addJsonHeader.end()) {;
+		  //if (doc.HasMember("detectorMode")) {
+		  //if (doc["detectorMode"].IsString()) {
+		  detectorMode_s=addJsonHeader.at("detectorMode");//=doc["detectorMode"].GetString();
 #ifdef INTERP
 		    if (detectorMode_s == "interpolating"){
 		      dMode=eInterpolating;
@@ -718,7 +828,7 @@ int main(int argc, char *argv[]) {
 		      mt->setInterpolation(NULL);
 #endif
 		    }
-		  }
+		    // }
 		  
 	      }
 
@@ -767,19 +877,19 @@ int main(int argc, char *argv[]) {
 	      // }
 	      
 	      // threshold=0;
-	      cprintf(MAGENTA, "Subframes: ");
-	      subframes=0;
-	      //isubframe=0;
-	      insubframe=0;
-	      subnorm=1;
-	      f0=0;
-	      nnsubframe=0;
-	      if (doc.HasMember("subframes")) {	
-		if (doc["subframes"].IsInt()) {
-		  subframes=doc["subframes"].GetInt();
-		}
-	      }	
-	      cprintf(MAGENTA, "%ld\n", subframes);
+	      // cprintf(MAGENTA, "Subframes: ");
+	      // subframes=0;
+	      // //isubframe=0;
+	      // insubframe=0;
+	      // subnorm=1;
+	      // f0=0;
+	      // nnsubframe=0;
+	      // if (doc.HasMember("subframes")) {	
+	      // 	if (doc["subframes"].IsInt()) {
+	      // 	  subframes=doc["subframes"].GetInt();
+	      // 	}
+	      // }	
+	      // cprintf(MAGENTA, "%ld\n", subframes);
 
 	      
 	      newFrame=0;
@@ -811,13 +921,13 @@ int main(int argc, char *argv[]) {
 	  // get data
 	  // acqIndex = doc["acqIndex"].GetUint64();
 
-	  frameIndex       = doc["fIndex"].GetUint64();
+	  frameIndex       = zHeader.frameIndex;////doc["fIndex"].GetUint64();
 
 	  // subFrameIndex    = doc["expLength"].GetUint();
 
 	  //  bunchId=doc["bunchId"].GetUint();
 	  //  timestamp=doc["timestamp"].GetUint();
-	  packetNumber=doc["packetNumber"].GetUint();
+	  packetNumber=zHeader.packetNumber; //doc["packetNumber"].GetUint();
 	  // cout << acqIndex << " " << frameIndex << " " << subFrameIndex << " "<< bunchId << " " << timestamp << " " << packetNumber << endl;
 	  //cprintf(GREEN, "frame\n");
 	  if (packetNumber>=40) {
@@ -866,8 +976,9 @@ int main(int argc, char *argv[]) {
 
 
 	    
- 	    zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);
-
+	    //   zmqsocket2->SendHeaderData (0, false,SLS_DETECTOR_JSON_HEADER_VERSION , dr, fileindex, 1,1,nnx,nny,nnx*nny*dr/8,acqIndex, frameIndex, fname,acqIndex,0 , packetNumber,bunchId, timestamp, modId,xCoord, yCoord, zCoord,debug, roundRNumber, detType, version, 0,0, 0,&additionalJsonHeader);
+	    zHeader.data = true;
+	    zmqsocket2->SendHeader(0,zHeader);
 	    zmqsocket2->SendData((char*)dout,nnx*nny*dr/8);
 	    cprintf(GREEN, "Sent subdata\n");
 		

slsDetectorCalibration/singlePhotonDetector.h

@@ -490,7 +490,7 @@ int *getClusters(char *data,  int *ph=NULL) {
       	  //  (clusters+nph)->ped=getPedestal(ix,iy,0);
 	  for (ir=-(clusterSizeY/2); ir<(clusterSizeY/2)+1; ir++) {
 	    for (ic=-(clusterSize/2); ic<(clusterSize/2)+1; ic++) {
-	      if ((iy+ir)>=iy && (iy+ir)<ny && (ix+ic)>=ix && (ix+ic)<nx) 
+	      if ((iy+ir)>=0  && (iy+ir)<ny &&  (ix+ic)>=0 && (ix+ic)<nx) 
 		(clusters+nph)->set_data(val[iy+ir][ix+ic],ic,ir);
 	    }
       }

slsDetectorCalibration/single_photon_hit.h

@@ -36,16 +36,14 @@ class single_photon_hit {
       \param myFile file descriptor
   */
   size_t write(FILE *myFile) {
-    //fwrite((void*)this, 1, 3*sizeof(int)+4*sizeof(double)+sizeof(quad), myFile); 
-    
-    // if (fwrite((void*)this, 1, sizeof(int)+2*sizeof(int16_t), myFile))
+    //fwrite((void*)this, 1, 3*sizeof(int)+4*sizeof(double)+sizeof(quad), myFile);  // if (fwrite((void*)this, 1, sizeof(int)+2*sizeof(int16_t), myFile))
 #ifdef OLDFORMAT 
     if (fwrite((void*)&iframe, 1,  sizeof(int), myFile)) {};
 #endif  
 #ifndef WRITE_QUAD
       //printf("no quad ");
-    //if (fwrite((void*)&x, 2,  sizeof(int16_t), myFile)) 
-      return fwrite((void*)&x, 1, dx*dy*sizeof(int)+2*sizeof(int16_t), myFile);
+    if (fwrite((void*)&x, sizeof(int16_t), 2, myFile)) 
+      return fwrite((void*)data, sizeof(int), dx*dy, myFile);
 #endif 
 #ifdef WRITE_QUAD
     //  printf("quad ");
@@ -91,8 +89,8 @@ class single_photon_hit {
     default:
       ;
     }
-     if (fwrite((void*)&x, 2,  sizeof(int16_t), myFile)) 
-      return fwrite((void*)qq, 1, 4*sizeof(int), myFile);
+     if (fwrite((void*)&x,   sizeof(int16_t), 2, myFile)) 
+      return fwrite((void*)qq, sizeof(int), 4, myFile);
 #endif
     return 0;
   };   
@@ -109,14 +107,14 @@ class single_photon_hit {
 #endif   
 #ifndef WRITE_QUAD
       // printf( "no quad \n");
-    if (fread((void*)&x, 2,  sizeof(int16_t), myFile))  
-      return fread((void*)data, 1, dx*dy*sizeof(int), myFile);
+    if (fread((void*)&x,  sizeof(int16_t),2, myFile))  
+      return fread((void*)data, sizeof(int), dx*dy,myFile);
 #endif 
 #ifdef WRITE_QUAD
     int qq[4];
-    // printf( "quad \n");
-    if (fread((void*)&x, 2,  sizeof(int16_t), myFile))  
-      if (fread((void*)qq, 1, 4*sizeof(int), myFile)) {
+    printf( "quad \n");
+    if (fread((void*)&x, sizeof(int16_t), 2,  myFile))  
+      if (fread((void*)qq, sizeof(int), 4, myFile)) {
 
 	quad=TOP_RIGHT;
 	/*	int mm=qq[0]; */
@@ -216,7 +214,6 @@ class single_photon_hit {
     for (int iy=0; iy<dy; iy++) {
       for (int ix=0; ix<dx; ix++) {
 	printf("%d \t",data[ix+iy*dx]);
-
       }
     printf("\n");
     }

slsDetectorGui/include/qCloneWidget.h

@@ -14,7 +14,8 @@ class qCloneWidget : public QMainWindow, private Ui::ClonePlotObject {
     qCloneWidget(QWidget *parent, SlsQt1DPlot *p1, SlsQt2DPlot *p2,
                  SlsQt1DPlot *gp1, SlsQt2DPlot *gp, QString title,
                  QString filePath, QString fileName, int64_t aIndex,
-                 bool displayStats, QString min, QString max, QString sum, bool completeImage);
+                 bool displayStats, QString min, QString max, QString sum,
+                 bool completeImage);
 
     ~qCloneWidget();
 

slsDetectorGui/include/qDacWidget.h

@@ -1,7 +1,7 @@
 #pragma once
-#include "ui_form_dac.h"
 #include "Detector.h"
 #include "sls_detector_defs.h"
+#include "ui_form_dac.h"
 #include <string>
 
 class qDacWidget : public QWidget, private Ui::WidgetDacObject {

slsDetectorGui/include/qDefs.h

@@ -6,9 +6,9 @@
 #include <QMessageBox>
 
 #include <chrono>
+#include <cstdint>
 #include <iostream>
 #include <ostream>
-#include <cstdint>
 #include <string>
 
 using std::chrono::duration;

slsDetectorGui/include/qDetectorMain.h

@@ -1,7 +1,7 @@
 #pragma once
-#include "ui_form_detectormain.h"
-#include "qDefs.h"
 #include "Detector.h"
+#include "qDefs.h"
+#include "ui_form_detectormain.h"
 #include <QTabWidget>
 
 class qDrawPlot;

slsDetectorGui/include/qDrawPlot.h

@@ -1,7 +1,7 @@
 #pragma once
-#include "ui_form_plot.h"
-#include "qDefs.h"
 #include "Detector.h"
+#include "qDefs.h"
+#include "ui_form_plot.h"
 #include <mutex>
 
 class SlsQt1DPlot;

slsDetectorGui/include/qTabAdvanced.h

@@ -1,6 +1,6 @@
 #pragma once
-#include "ui_form_tab_advanced.h"
 #include "Detector.h"
+#include "ui_form_tab_advanced.h"
 
 class qDrawPlot;
 

slsDetectorGui/include/qTabDataOutput.h

@@ -1,6 +1,6 @@
 #pragma once
-#include "ui_form_tab_dataoutput.h"
 #include "Detector.h"
+#include "ui_form_tab_dataoutput.h"
 
 class qTabDataOutput : public QWidget, private Ui::TabDataOutputObject {
     Q_OBJECT

slsDetectorGui/include/qTabDebugging.h

@@ -1,6 +1,6 @@
 #pragma once
-#include "ui_form_tab_debugging.h"
 #include "Detector.h"
+#include "ui_form_tab_debugging.h"
 
 class QTreeWidget;
 class QTreeWidgetItem;

slsDetectorGui/include/qTabDeveloper.h

@@ -1,7 +1,7 @@
 #pragma once
-#include "ui_form_tab_developer.h"
 #include "Detector.h"
 #include "sls_detector_defs.h"
+#include "ui_form_tab_developer.h"
 #include <vector>
 
 class qDacWidget;

slsDetectorGui/include/qTabMeasurement.h

@@ -1,6 +1,6 @@
 #pragma once
-#include "ui_form_tab_measurement.h"
 #include "Detector.h"
+#include "ui_form_tab_measurement.h"
 
 class qDrawPlot;
 class QStandardItemModel;

slsDetectorGui/include/qTabPlot.h

@@ -1,6 +1,6 @@
 #pragma once
-#include "ui_form_tab_plot.h"
 #include "Detector.h"
+#include "ui_form_tab_plot.h"
 
 class qDrawPlot;
 class QButtonGroup;

slsDetectorGui/include/qTabSettings.h

@@ -1,6 +1,6 @@
 #pragma once
-#include "ui_form_tab_settings.h"
 #include "Detector.h"
+#include "ui_form_tab_settings.h"
 
 class qTabSettings : public QWidget, private Ui::TabSettingsObject {
     Q_OBJECT

slsDetectorGui/slsDetectorPlotting/include/SlsQt1DPlot.h

@@ -1,8 +1,8 @@
 #ifndef SLSQT1DPLOT_H
 #define SLSQT1DPLOT_H
 
-#include "ansi.h"
 #include "SlsQt1DZoomer.h"
+#include "ansi.h"
 #include <qwt_plot.h>
 #include <qwt_plot_curve.h>
 #include <qwt_plot_marker.h>

slsDetectorGui/slsDetectorPlotting/include/SlsQt2DZoomer.h

@@ -1,9 +1,9 @@
 #ifndef SLSQT2DZOOMER_H
 #define SLSQT2DZOOMER_H
 #include "SlsQt2DHist.h"
+#include <cstdio>
 #include <qwt_plot_panner.h>
 #include <qwt_plot_zoomer.h>
-#include <cstdio>
 
 class SlsQt2DZoomer : public QwtPlotZoomer {
   private:

slsDetectorGui/slsDetectorPlotting/src/SlsQt1DPlot.cpp

@@ -1,7 +1,7 @@
 
 /* TODO! short description */
 #include "SlsQt1DPlot.h"
-#include <qwt_symbol.h>
+#include <iostream>
 #include <qwt_legend.h>
 #include <qwt_math.h>
 #include <qwt_painter.h>
@@ -10,8 +10,8 @@
 #include <qwt_scale_draw.h>
 #include <qwt_scale_engine.h>
 #include <qwt_scale_widget.h>
+#include <qwt_symbol.h>
 #include <stdlib.h>
-#include <iostream>
 
 #define QwtLog10ScaleEngine QwtLogScaleEngine // hmm
 
@@ -314,7 +314,8 @@ void SlsQtH1DList::Remove(SlsQtH1D *hist) {
             hl = hl->the_next;
         else { // match
             if (!hl->the_next)
-                hl->the_hist = nullptr; // first the_hist is zero when there's no next
+                hl->the_hist =
+                    nullptr; // first the_hist is zero when there's no next
             else {
                 SlsQtH1DList *t = hl->the_next;
                 hl->the_hist = t->the_hist;

slsDetectorGui/slsDetectorPlotting/src/SlsQt1DZoomer.cpp

@@ -1,9 +1,9 @@
 /* TODO! short description */
 #include "SlsQt1DZoomer.h"
 #include "SlsQt1DPlot.h"
+#include <iostream>
 #include <qwt_plot.h>
 #include <qwt_scale_div.h>
-#include <iostream>
 
 void SlsQt1DZoomer::ResetZoomBase() {
     SetZoomBase(x0, y0, x1 - x0,

slsDetectorGui/slsDetectorPlotting/src/SlsQt2DPlot.cpp

@@ -224,7 +224,6 @@ QwtLinearColorMap *SlsQt2DPlot::myColourMap(int log) {
     return myColourMap(cs);
 }
 
-
 void SlsQt2DPlot::Update() {
     if (isLog)
         hist->SetMinimumToFirstGreaterThanZero();

slsDetectorGui/src/qDacWidget.cpp

@@ -1,7 +1,6 @@
 #include "qDacWidget.h"
 #include "qDefs.h"
 
-
 qDacWidget::qDacWidget(QWidget *parent, sls::Detector *detector, bool d,
                        std::string n, slsDetectorDefs::dacIndex i)
     : QWidget(parent), det(detector), isDac(d), index(i) {
@@ -56,8 +55,8 @@ void qDacWidget::GetDac() {
 
 void qDacWidget::SetDac() {
     int val = (int)spinDac->value();
-    LOG(logINFO) << "Setting dac:" << lblDac->text().toAscii().data()
-                      << " : " << val;
+    LOG(logINFO) << "Setting dac:" << lblDac->text().toAscii().data() << " : "
+                 << val;
 
     try {
         det->setDAC(index, val, 0, {detectorIndex});

slsDetectorGui/src/qDetectorMain.cpp

@@ -19,8 +19,8 @@
 #include <QScrollArea>
 #include <QSizePolicy>
 
-#include <string>
 #include <getopt.h>
+#include <string>
 #include <sys/stat.h>
 
 int main(int argc, char **argv) {
@@ -57,8 +57,7 @@ int main(int argc, char **argv) {
 
         case 'f':
             fname = optarg;
-            LOG(logDEBUG)
-                << long_options[option_index].name << " " << optarg;
+            LOG(logDEBUG) << long_options[option_index].name << " " << optarg;
             break;
 
         case 'd':
@@ -105,9 +104,10 @@ int main(int argc, char **argv) {
     return 0;
 }
 
-qDetectorMain::qDetectorMain(int multiId, const std::string& fname, bool isDevel)
-    : QMainWindow(nullptr), detType(slsDetectorDefs::GENERIC), isDeveloper(isDevel),
-      heightPlotWindow(0), heightCentralWidget(0) {
+qDetectorMain::qDetectorMain(int multiId, const std::string &fname,
+                             bool isDevel)
+    : QMainWindow(nullptr), detType(slsDetectorDefs::GENERIC),
+      isDeveloper(isDevel), heightPlotWindow(0), heightCentralWidget(0) {
 
     setupUi(this);
     SetUpDetector(fname, multiId);
@@ -115,8 +115,7 @@ qDetectorMain::qDetectorMain(int multiId, const std::string& fname, bool isDevel
 }
 
 qDetectorMain::~qDetectorMain() {
-    disconnect(tabs, SIGNAL(currentChanged(int)), this,
-            SLOT(Refresh(int)));
+    disconnect(tabs, SIGNAL(currentChanged(int)), this, SLOT(Refresh(int)));
 }
 
 void qDetectorMain::SetUpWidgetWindow() {
@@ -132,8 +131,7 @@ void qDetectorMain::SetUpWidgetWindow() {
     layoutTabs->addWidget(tabs);
 
     // creating all the other tab widgets
-    tabMeasurement =
-        new qTabMeasurement(this, det.get(), plot);
+    tabMeasurement = new qTabMeasurement(this, det.get(), plot);
     tabDataOutput = new qTabDataOutput(this, det.get());
     tabPlot = new qTabPlot(this, det.get(), plot);
     tabSettings = new qTabSettings(this, det.get());
@@ -260,8 +258,8 @@ void qDetectorMain::Initialization() {
     //	Measurement tab
     connect(tabMeasurement, SIGNAL(EnableTabsSignal(bool)), this,
             SLOT(EnableTabs(bool)));
-    connect(tabMeasurement, SIGNAL(FileNameChangedSignal(QString)),
-            plot, SLOT(SetSaveFileName(QString)));
+    connect(tabMeasurement, SIGNAL(FileNameChangedSignal(QString)), plot,
+            SLOT(SetSaveFileName(QString)));
     // Plot tab
     connect(tabPlot, SIGNAL(DisableZoomSignal(bool)), this,
             SLOT(SetZoomToolTip(bool)));
@@ -269,8 +267,7 @@ void qDetectorMain::Initialization() {
     // Plotting
     connect(plot, SIGNAL(AcquireFinishedSignal()), tabMeasurement,
             SLOT(AcquireFinished()));
-    connect(plot, SIGNAL(AbortSignal()), tabMeasurement,
-            SLOT(AbortAcquire()));
+    connect(plot, SIGNAL(AbortSignal()), tabMeasurement, SLOT(AbortAcquire()));
 
     // menubar
     // Modes Menu
@@ -372,8 +369,7 @@ void qDetectorMain::ExecuteUtilities(QAction *action) {
                                "The Configuration Parameters have been "
                                "configured successfully.",
                                "qDetectorMain::ExecuteUtilities");
-                LOG(logINFO)
-                    << "Configuration Parameters loaded successfully";
+                LOG(logINFO) << "Configuration Parameters loaded successfully";
             }
         }
 

slsDetectorGui/src/qDrawPlot.cpp

@@ -277,8 +277,7 @@ void qDrawPlot::SetPlotTitlePrefix(QString title) {
 }
 
 void qDrawPlot::SetXAxisTitle(QString title) {
-    LOG(logINFO) << "Setting X Axis Title to "
-                      << title.toAscii().constData();
+    LOG(logINFO) << "Setting X Axis Title to " << title.toAscii().constData();
     if (is1d) {
         xTitle1d = title;
     } else {
@@ -287,8 +286,7 @@ void qDrawPlot::SetXAxisTitle(QString title) {
 }
 
 void qDrawPlot::SetYAxisTitle(QString title) {
-    LOG(logINFO) << "Setting Y Axis Title to "
-                      << title.toAscii().constData();
+    LOG(logINFO) << "Setting Y Axis Title to " << title.toAscii().constData();
     if (is1d) {
         yTitle1d = title;
     } else {
@@ -297,8 +295,7 @@ void qDrawPlot::SetYAxisTitle(QString title) {
 }
 
 void qDrawPlot::SetZAxisTitle(QString title) {
-    LOG(logINFO) << "Setting Z Axis Title to "
-                      << title.toAscii().constData();
+    LOG(logINFO) << "Setting Z Axis Title to " << title.toAscii().constData();
     zTitle2d = title;
 }
 
@@ -309,8 +306,8 @@ void qDrawPlot::SetXYRangeChanged(bool disable, double *xy, bool *isXY) {
     std::copy(xy, xy + 4, xyRange);
     std::copy(isXY, isXY + 4, isXYRange);
 
-    LOG(logDEBUG) << "Setting Disable zoom to " << std::boolalpha
-                       << disable << std::noboolalpha;
+    LOG(logDEBUG) << "Setting Disable zoom to " << std::boolalpha << disable
+                  << std::noboolalpha;
     disableZoom = disable;
 }
 
@@ -348,8 +345,8 @@ double qDrawPlot::GetYMaximum() {
 }
 
 void qDrawPlot::SetDataCallBack(bool enable) {
-    LOG(logINFO) << "Setting data call back to " << std::boolalpha
-                      << enable << std::noboolalpha;
+    LOG(logINFO) << "Setting data call back to " << std::boolalpha << enable
+                 << std::noboolalpha;
     try {
         if (enable) {
             isPlot = true;
@@ -360,7 +357,8 @@ void qDrawPlot::SetDataCallBack(bool enable) {
             det->registerDataCallback(nullptr, this);
             det->setRxZmqDataStream(false);
         }
-    } CATCH_DISPLAY("Could not get set rxr data streaming enable.",
+    }
+    CATCH_DISPLAY("Could not get set rxr data streaming enable.",
                   "qDrawPlot::SetDataCallBack")
 }
 
@@ -570,8 +568,8 @@ void qDrawPlot::ClonePlot() {
     new qCloneWidget(this, cloneplot1D, cloneplot2D, clonegainplot1D,
                      clonegainplot2D, boxPlot->title(), fileSavePath,
                      fileSaveName, currentAcqIndex, displayStatistics,
-                     lblMinDisp->text(), lblMaxDisp->text(),
-                     lblSumDisp->text(), completeImage);
+                     lblMinDisp->text(), lblMaxDisp->text(), lblSumDisp->text(),
+                     completeImage);
 }
 
 void qDrawPlot::SavePlot() {
@@ -673,8 +671,7 @@ void qDrawPlot::AcquireThread() {
     // exception in acquire will not call acquisition finished call back, so
     // handle it
     if (!mess.empty()) {
-        LOG(logERROR) << "Acquisition Finished with an exception: "
-                           << mess;
+        LOG(logERROR) << "Acquisition Finished with an exception: " << mess;
         qDefs::ExceptionMessage("Acquire unsuccessful.", mess,
                                 "qDrawPlot::AcquireFinished");
         try {
@@ -739,8 +736,7 @@ void qDrawPlot::GetData(detectorData *data, uint64_t frameIndex,
                   << "  \t nx: " << data->nx << std::endl
                   << "  \t ny: " << data->ny << std::endl
                   << "  \t data bytes: " << data->databytes << std::endl
-                       << "  \t dynamic range: " << data->dynamicRange
-                       << std::endl
+                  << "  \t dynamic range: " << data->dynamicRange << std::endl
                   << "  \t file index: " << data->fileIndex << std::endl
                   << "  \t complete image: " << data->completeImage << std::endl
                   << "  ]";
@@ -748,8 +744,8 @@ void qDrawPlot::GetData(detectorData *data, uint64_t frameIndex,
     progress = (int)data->progressIndex;
     currentAcqIndex = data->fileIndex;
     currentFrame = frameIndex;
-    LOG(logDEBUG) << "[ Progress:" << progress
-                       << ", Frame:" << currentFrame << " ]";
+    LOG(logDEBUG) << "[ Progress:" << progress << ", Frame:" << currentFrame
+                  << " ]";
 
     // 2d (only image, not gain data, not pedestalvals),
     // check if npixelsX and npixelsY is the same (quad is different)
@@ -757,8 +753,8 @@ void qDrawPlot::GetData(detectorData *data, uint64_t frameIndex,
                   static_cast<int>(nPixelsY) != data->ny)) {
         nPixelsX = data->nx;
         nPixelsY = data->ny;
-        LOG(logINFO) << "Change in Detector Shape:\n\tnPixelsX:"
-                          << nPixelsX << " nPixelsY:" << nPixelsY;
+        LOG(logINFO) << "Change in Detector Shape:\n\tnPixelsX:" << nPixelsX
+                     << " nPixelsY:" << nPixelsY;
 
         delete[] data2d;
         data2d = new double[nPixelsY * nPixelsX];
@@ -815,8 +811,8 @@ void qDrawPlot::GetData(detectorData *data, uint64_t frameIndex,
         }
         // calculate the pedestal value
         if (pedestalCount == NUM_PEDESTAL_FRAMES) {
-            LOG(logINFO) << "Pedestal Calculated after "
-                              << NUM_PEDESTAL_FRAMES << " frames";
+            LOG(logINFO) << "Pedestal Calculated after " << NUM_PEDESTAL_FRAMES
+                         << " frames";
             for (unsigned int px = 0; px < nPixels; ++px)
                 tempPedestalVals[px] =
                     tempPedestalVals[px] / (double)NUM_PEDESTAL_FRAMES;

slsDetectorGui/src/qTabAdvanced.cpp

@@ -531,8 +531,7 @@ void qTabAdvanced::SetROI() {
     roi.xmax = spinXmax->value();
 
     // set roi
-    LOG(logINFO) << "Setting ROI: [" << roi.xmin << ", " << roi.xmax
-                      << "]";
+    LOG(logINFO) << "Setting ROI: [" << roi.xmin << ", " << roi.xmax << "]";
     try {
         det->setROI(roi, {comboReadout->currentIndex()});
     }
@@ -586,8 +585,7 @@ void qTabAdvanced::GetNumStoragecells() {
 }
 
 void qTabAdvanced::SetNumStoragecells(int value) {
-    LOG(logINFO) << "Setting number of additional stoarge cells: "
-                      << value;
+    LOG(logINFO) << "Setting number of additional stoarge cells: " << value;
     try {
         det->setNumberOfAdditionalStorageCells(value);
     }
@@ -621,8 +619,8 @@ void qTabAdvanced::SetSubExposureTime() {
     auto timeNS = qDefs::getNSTime(std::make_pair(
         spinSubExpTime->value(),
         static_cast<qDefs::timeUnit>(comboSubExpTimeUnit->currentIndex())));
-    LOG(logINFO)
-        << "Setting sub frame acquisition time to " << timeNS.count() << " ns"
+    LOG(logINFO) << "Setting sub frame acquisition time to " << timeNS.count()
+                 << " ns"
                  << "/" << spinSubExpTime->value()
                  << qDefs::getUnitString(
                         (qDefs::timeUnit)comboSubExpTimeUnit->currentIndex());
@@ -661,8 +659,7 @@ void qTabAdvanced::SetSubDeadTime() {
         spinSubDeadTime->value(),
         static_cast<qDefs::timeUnit>(comboSubDeadTimeUnit->currentIndex())));
 
-    LOG(logINFO)
-        << "Setting sub frame dead time to " << timeNS.count() << " ns"
+    LOG(logINFO) << "Setting sub frame dead time to " << timeNS.count() << " ns"
                  << "/" << spinSubDeadTime->value()
                  << qDefs::getUnitString(
                         (qDefs::timeUnit)comboSubDeadTimeUnit->currentIndex());

slsDetectorGui/src/qTabDataOutput.cpp

@@ -334,15 +334,13 @@ void qTabDataOutput::SetRateCorrection() {
         // custom dead time
         if (radioCustomDeadtime->isChecked()) {
             int64_t deadtime = spinCustomDeadTime->value();
-            LOG(logINFO)
-                << "Setting Rate Correction with custom dead time: "
+            LOG(logINFO) << "Setting Rate Correction with custom dead time: "
                          << deadtime;
             det->setRateCorrection(sls::ns(deadtime));
         }
         // default dead time
         else {
-            LOG(logINFO)
-                << "Setting Rate Correction with default dead time";
+            LOG(logINFO) << "Setting Rate Correction with default dead time";
             det->setDefaultRateCorrection();
         }
     }
@@ -398,8 +396,7 @@ void qTabDataOutput::SetFlags() {
     auto mode =
         comboEigerParallelFlag->currentIndex() == PARALLEL ? true : false;
     try {
-        LOG(logINFO)
-            << "Setting Readout Flags to "
+        LOG(logINFO) << "Setting Readout Flags to "
                      << comboEigerParallelFlag->currentText().toAscii().data();
         det->setParallelMode(mode);
     }

slsDetectorGui/src/qTabDebugging.cpp

@@ -1,6 +1,6 @@
 #include "qTabDebugging.h"
-#include "qDefs.h"
 #include "ToString.h"
+#include "qDefs.h"
 #include <QDesktopWidget>
 #include <QGridLayout>
 #include <QTreeWidget>
@@ -105,8 +105,9 @@ void qTabDebugging::GetInfo() {
         treeDet->setHeaderLabel("Eiger Detector");
         // get num modules
         for (int i = 0; i < comboDetector->count() / 2; ++i)
-            items.append(new QTreeWidgetItem(
-                (QTreeWidget *)nullptr, QStringList(QString("Module %1").arg(i))));
+            items.append(
+                new QTreeWidgetItem((QTreeWidget *)nullptr,
+                                    QStringList(QString("Module %1").arg(i))));
         treeDet->insertTopLevelItems(0, items);
         // gets det names
         for (int i = 0; i < comboDetector->count(); ++i) {

slsDetectorGui/src/qTabMeasurement.cpp

@@ -771,8 +771,7 @@ void qTabMeasurement::AcquireFinished() {
         if (startingFnumImplemented) {
             GetStartingFrameNumber();
         }
-        LOG(logDEBUG) << "Measurement " << currentMeasurement
-                           << " finished";
+        LOG(logDEBUG) << "Measurement " << currentMeasurement << " finished";
         // next measurement if acq is not stopped
         if (!isAcquisitionStopped &&
             ((currentMeasurement + 1) < numMeasurements)) {
@@ -801,8 +800,9 @@ void qTabMeasurement::Enable(bool enable) {
     frameNotTimeResolved->setEnabled(enable);
 
     // shortcut each time, else it doesnt work a second time
-    btnStart->setShortcut(QApplication::translate(
-        "TabMeasurementObject", "Shift+Space", nullptr, QApplication::UnicodeUTF8));
+    btnStart->setShortcut(QApplication::translate("TabMeasurementObject",
+                                                  "Shift+Space", nullptr,
+                                                  QApplication::UnicodeUTF8));
 }
 
 void qTabMeasurement::Refresh() {

slsDetectorGui/src/qTabPlot.cpp

@@ -6,7 +6,6 @@
 #include <QStackedLayout>
 #include <QStandardItemModel>
 
-
 QString qTabPlot::defaultPlotTitle("");
 QString qTabPlot::defaultHistXAxisTitle("Channel Number");
 QString qTabPlot::defaultHistYAxisTitle("Counts");
@@ -290,16 +289,14 @@ void qTabPlot::SetBinary() {
     bool binary1D = chkBinary->isChecked();
     bool binary2D = chkBinary_2->isChecked();
     if (is1d) {
-        LOG(logINFO) << "Binary Plot "
-                          << (binary1D ? "enabled" : "disabled");
+        LOG(logINFO) << "Binary Plot " << (binary1D ? "enabled" : "disabled");
         lblFrom->setEnabled(binary1D);
         lblTo->setEnabled(binary1D);
         spinFrom->setEnabled(binary1D);
         spinTo->setEnabled(binary1D);
         plot->SetBinary(binary1D, spinFrom->value(), spinTo->value());
     } else {
-        LOG(logINFO) << "Binary Plot "
-                          << (binary2D ? "enabled" : "disabled");
+        LOG(logINFO) << "Binary Plot " << (binary2D ? "enabled" : "disabled");
         lblFrom_2->setEnabled(binary2D);
         lblTo_2->setEnabled(binary2D);
         spinFrom_2->setEnabled(binary2D);
@@ -434,9 +431,9 @@ void qTabPlot::SetXYRange() {
     for (int i = 0; i < 4; ++i) {
         if (chkVal[i] && !dispVal[i].isEmpty()) {
             double val = dispVal[i].toDouble();
-            LOG(logDEBUG)
-                << "Setting "
-                << qDefs::getRangeAsString(static_cast<qDefs::range>(i))
+            LOG(logDEBUG) << "Setting "
+                          << qDefs::getRangeAsString(
+                                 static_cast<qDefs::range>(i))
                           << " to " << val;
             xyRange[i] = val;
             isRange[i] = true;
@@ -482,10 +479,10 @@ void qTabPlot::MaintainAspectRatio(int dimension) {
     ranges[qDefs::YMAX] = plot->GetYMaximum();
     double idealAspectratio = (ranges[qDefs::XMAX] - ranges[qDefs::XMIN]) /
                               (ranges[qDefs::YMAX] - ranges[qDefs::YMIN]);
-    LOG(logDEBUG) << "Ideal Aspect ratio: " << idealAspectratio
-                       << " for x(" << ranges[qDefs::XMIN] << " - "
-                       << ranges[qDefs::XMAX] << "), y(" << ranges[qDefs::YMIN]
-                       << " - " << ranges[qDefs::YMAX] << ")";
+    LOG(logDEBUG) << "Ideal Aspect ratio: " << idealAspectratio << " for x("
+                  << ranges[qDefs::XMIN] << " - " << ranges[qDefs::XMAX]
+                  << "), y(" << ranges[qDefs::YMIN] << " - "
+                  << ranges[qDefs::YMAX] << ")";
 
     // calculate current aspect ratio
     ranges[qDefs::XMIN] = dispXMin->text().toDouble();
@@ -494,10 +491,10 @@ void qTabPlot::MaintainAspectRatio(int dimension) {
     ranges[qDefs::YMAX] = dispYMax->text().toDouble();
     double currentAspectRatio = (ranges[qDefs::XMAX] - ranges[qDefs::XMIN]) /
                                 (ranges[qDefs::YMAX] - ranges[qDefs::YMIN]);
-    LOG(logDEBUG) << "Current Aspect ratio: " << currentAspectRatio
-                       << " for x(" << ranges[qDefs::XMIN] << " - "
-                       << ranges[qDefs::XMAX] << "), y(" << ranges[qDefs::YMIN]
-                       << " - " << ranges[qDefs::YMAX] << ")";
+    LOG(logDEBUG) << "Current Aspect ratio: " << currentAspectRatio << " for x("
+                  << ranges[qDefs::XMIN] << " - " << ranges[qDefs::XMAX]
+                  << "), y(" << ranges[qDefs::YMIN] << " - "
+                  << ranges[qDefs::YMAX] << ")";
 
     if (currentAspectRatio != idealAspectratio) {
         // dimension: 1(x changed: y adjusted), 0(y changed: x adjusted),

slsDetectorGui/src/qTabSettings.cpp

@@ -1,6 +1,6 @@
 #include "qTabSettings.h"
-#include "qDefs.h"
 #include "ToString.h"
+#include "qDefs.h"
 #include <QStandardItemModel>
 
 qTabSettings::qTabSettings(QWidget *parent, sls::Detector *detector)

slsDetectorServers/ctbDetectorServer/RegisterDefs.h

@@ -10,7 +10,8 @@
 #define FPGA_VERSION_BRD_RVSN_MSK   (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
 #define FPGA_VERSION_DTCTR_TYP_OFST (24)
 #define FPGA_VERSION_DTCTR_TYP_MSK  (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
-#define FPGA_VERSION_DTCTR_TYP_CTB_VAL      ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
+#define FPGA_VERSION_DTCTR_TYP_CTB_VAL                                         \
+    ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
 
 /* Fix pattern RO register */
 #define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@@ -57,7 +58,8 @@
 #define STATUS_PLL_PHS_DN_OFST        (23)
 #define STATUS_PLL_PHS_DN_MSK         (0x00000001 << STATUS_PLL_PHS_DN_OFST)
 #define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
-#define STATUS_PT_CNTRL_STTS_OFF_MSK        (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
+#define STATUS_PT_CNTRL_STTS_OFF_MSK                                           \
+    (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
 #define STATUS_IDLE_MSK (0x677FF)
 
 /* Look at me RO register TODO */
@@ -67,24 +69,30 @@
 #define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
 
 #define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
-#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK 	(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
+#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK                                       \
+    (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
 #define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
-#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK 	(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
+#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK                                       \
+    (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
 #define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
-#define SYSTEM_STATUS_DDR3_INT_DN_MSK 		(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
+#define SYSTEM_STATUS_DDR3_INT_DN_MSK                                          \
+    (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
 #define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
-#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK 	(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
+#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK                                        \
+    (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
 #define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
 #define SYSTEM_STATUS_PLL_A_LCK_MSK  (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
 
-/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
+/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
+ * PLL_PARAM_REG 0x50 */
 //#define PLL_PARAM_REG                       (0x05 << MEM_MAP_SHIFT)
 
 /* FIFO Data RO register TODO */
 #define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
 
 #define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
-#define FIFO_DATA_HRDWR_SRL_NMBR_MSK        (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
+#define FIFO_DATA_HRDWR_SRL_NMBR_MSK                                           \
+    (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
 //#define FIFO_DATA_WRD_OFST                  (16)
 //#define FIFO_DATA_WRD_MSK                   (0x0000FFFF << FIFO_DATA_WRD_OFST)
 
@@ -114,7 +122,8 @@
 #define API_VERSION_DTCTR_TYP_OFST (24)
 #define API_VERSION_DTCTR_TYP_MSK  (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
 
-/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
+/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
+ * CONTROL_CRST. TODO */
 #define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
 #define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
 
@@ -135,12 +144,16 @@
 #define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
 
 /* Exposure Time Left 64 bit RO register */
-//#define EXPTIME_LEFT_LSB_REG                (0x1A << MEM_MAP_SHIFT)            // Not used in FW
-//#define EXPTIME_LEFT_MSB_REG                (0x1B << MEM_MAP_SHIFT)            // Not used in FW
+//#define EXPTIME_LEFT_LSB_REG                (0x1A << MEM_MAP_SHIFT) // Not
+// used in FW #define EXPTIME_LEFT_MSB_REG                (0x1B <<
+// MEM_MAP_SHIFT)
+//// Not used in FW
 
 /* Gates Left 64 bit RO register */
-//#define GATES_LEFT_LSB_REG                  (0x1C << MEM_MAP_SHIFT)            // Not used in FW
-//#define GATES_LEFT_MSB_REG                  (0x1D << MEM_MAP_SHIFT)            // Not used in FW
+//#define GATES_LEFT_LSB_REG                  (0x1C << MEM_MAP_SHIFT) // Not
+// used in FW #define GATES_LEFT_MSB_REG                  (0x1D <<
+// MEM_MAP_SHIFT)
+//// Not used in FW
 
 /* Data In 64 bit RO register TODO */
 #define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
@@ -151,14 +164,17 @@
 #define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
 
 /* Frames From Start 64 bit RO register TODO */
-//#define FRAMES_FROM_START_LSB_REG           (0x22 << MEM_MAP_SHIFT)            // Not used in FW
-//#define FRAMES_FROM_START_MSB_REG           (0x23 << MEM_MAP_SHIFT)            // Not used in FW
+//#define FRAMES_FROM_START_LSB_REG           (0x22 << MEM_MAP_SHIFT) // Not
+// used in FW #define FRAMES_FROM_START_MSB_REG           (0x23 <<
+// MEM_MAP_SHIFT)
+//// Not used in FW
 
 /* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
 #define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
 #define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
 
-/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
+/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
+ * start until reset) TODO */
 #define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
 #define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
 
@@ -177,9 +193,11 @@
 /* FIFO Digital In Status RO register */
 #define FIFO_DIN_STATUS_REG            (0x3B << MEM_MAP_SHIFT)
 #define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
-#define FIFO_DIN_STATUS_FIFO_FULL_MSK		(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
+#define FIFO_DIN_STATUS_FIFO_FULL_MSK                                          \
+    (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
 #define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
-#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK		(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
+#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK                                         \
+    (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
 
 /* FIFO Digital In 64 bit RO register */
 #define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
@@ -243,9 +261,11 @@
 #define DUMMY_FIFO_CHNNL_SLCT_OFST    (0)
 #define DUMMY_FIFO_CHNNL_SLCT_MSK     (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
 #define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
-#define DUMMY_ANLG_FIFO_RD_STRBE_MSK        (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
+#define DUMMY_ANLG_FIFO_RD_STRBE_MSK                                           \
+    (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
 #define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
-#define DUMMY_DGTL_FIFO_RD_STRBE_MSK        (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
+#define DUMMY_DGTL_FIFO_RD_STRBE_MSK                                           \
+    (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
 
 /* Receiver IP Address RW register */
 #define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
@@ -313,21 +333,23 @@
 #define CONTROL_STP_ACQSTN_OFST  (1)
 #define CONTROL_STP_ACQSTN_MSK   (0x00000001 << CONTROL_STP_ACQSTN_OFST)
 //#define CONTROL_STRT_FF_TST_OFST            (2)
-//#define CONTROL_STRT_FF_TST_MSK             (0x00000001 << CONTROL_STRT_FF_TST_OFST)
-//#define CONTROL_STP_FF_TST_OFST             (3)
-//#define CONTROL_STP_FF_TST_MSK              (0x00000001 << CONTROL_STP_FF_TST_OFST)
-//#define CONTROL_STRT_RDT_OFST               (4)
-//#define CONTROL_STRT_RDT_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
-//#define CONTROL_STP_RDT_OFST                (5)
-//#define CONTROL_STP_RDT_MSK                 (0x00000001 << CONTROL_STP_RDT_OFST)
+//#define CONTROL_STRT_FF_TST_MSK             (0x00000001 <<
+// CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST             (3)
+//#define CONTROL_STP_FF_TST_MSK              (0x00000001 <<
+// CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST               (4)
+//#define CONTROL_STRT_RDT_MSK                (0x00000001 <<
+// CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST                (5)
+// #define CONTROL_STP_RDT_MSK                 (0x00000001 <<
+// CONTROL_STP_RDT_OFST)
 #define CONTROL_STRT_EXPSR_OFST (6)
 #define CONTROL_STRT_EXPSR_MSK  (0x00000001 << CONTROL_STRT_EXPSR_OFST)
 //#define CONTROL_STP_EXPSR_OFST              (7)
-//#define CONTROL_STP_EXPSR_MSK               (0x00000001 << CONTROL_STP_RDT_OFST)
-//#define CONTROL_STRT_TRN_OFST               (8)
-//#define CONTROL_STRT_TRN_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
+//#define CONTROL_STP_EXPSR_MSK               (0x00000001 <<
+// CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST               (8) #define
+// CONTROL_STRT_TRN_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
 //#define CONTROL_STP_TRN_OFST                (9)
-//#define CONTROL_STP_TRN_MSK                 (0x00000001 << CONTROL_STP_RDT_OFST)
+//#define CONTROL_STP_TRN_MSK                 (0x00000001 <<
+// CONTROL_STP_RDT_OFST)
 #define CONTROL_CRE_RST_OFST    (10)
 #define CONTROL_CRE_RST_MSK     (0x00000001 << CONTROL_CRE_RST_OFST)
 #define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
@@ -335,7 +357,8 @@
 #define CONTROL_MMRY_RST_OFST   (12)
 #define CONTROL_MMRY_RST_MSK    (0x00000001 << CONTROL_MMRY_RST_OFST)
 //#define CONTROL_PLL_RCNFG_WR_OFST           (13)
-//#define CONTROL_PLL_RCNFG_WR_MSK            (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
+//#define CONTROL_PLL_RCNFG_WR_MSK            (0x00000001 <<
+// CONTROL_PLL_RCNFG_WR_OFST)
 #define CONTROL_SND_10GB_PCKT_OFST   (14)
 #define CONTROL_SND_10GB_PCKT_MSK    (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
 #define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
@@ -348,7 +371,8 @@
 #define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
 
 #define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
-#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK		(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
+#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK                                          \
+    (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
 #define PLL_CNTRL_WR_PRMTR_OFST (2)
 #define PLL_CNTRL_WR_PRMTR_MSK  (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
 #define PLL_CNTRL_PLL_RST_OFST  (3)
@@ -378,7 +402,8 @@
 #define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_0_ADDR_STRT_MSK        (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
+#define PATTERN_LOOP_0_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
 #define PATTERN_LOOP_0_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_0_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
 
@@ -389,7 +414,8 @@
 #define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_1_ADDR_STRT_MSK        (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
+#define PATTERN_LOOP_1_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
 #define PATTERN_LOOP_1_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_1_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
 
@@ -400,7 +426,8 @@
 #define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_2_ADDR_STRT_MSK        (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
+#define PATTERN_LOOP_2_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
 #define PATTERN_LOOP_2_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_2_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
 
@@ -445,7 +472,6 @@
 /* Number of Words RW register TODO */
 #define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
 
-
 /* Delay 64 bit RW register. t = DLY x 50 ns. */
 #define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
 #define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
@@ -463,12 +489,14 @@
 #define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
 
 /* Period 64 bit RW register */
-//#define EXPTIME_LSB_REG    			    (0x68 << MEM_MAP_SHIFT)                 // Not used in FW
-//#define EXPTIME_MSB_REG    			    (0x69 << MEM_MAP_SHIFT)                 // Not used in FW
+//#define EXPTIME_LSB_REG    			    (0x68 << MEM_MAP_SHIFT) //
+// Not used in FW #define EXPTIME_MSB_REG    			    (0x69 <<
+// MEM_MAP_SHIFT)                 // Not used in FW
 
 /* Gates 64 bit RW register */
-//#define GATES_LSB_REG                      (0x6A << MEM_MAP_SHIFT)                 // Not used in FW
-//#define GATES_MSB_REG                      (0x6B << MEM_MAP_SHIFT)                 // Not used in FW
+//#define GATES_LSB_REG                      (0x6A << MEM_MAP_SHIFT) // Not used
+// in FW #define GATES_MSB_REG                      (0x6B << MEM_MAP_SHIFT) //
+// Not used in FW
 
 /* Pattern IO Control 64 bit RW regiser
  * Each bit configured as output(1)/ input(0) */
@@ -505,7 +533,6 @@
 #define READOUT_10G_ENABLE_DGTL_OFST (8)
 #define READOUT_10G_ENABLE_DGTL_MSK  (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
 
-
 /* Digital Bit External Trigger RW register */
 #define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
 
@@ -517,11 +544,15 @@
 /* Pin Delay 0 RW register */
 #define OUTPUT_DELAY_0_REG              (0x7C << MEM_MAP_SHIFT)
 #define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
-#define OUTPUT_DELAY_0_OTPT_STTNG_OFST      (0)     //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
-#define OUTPUT_DELAY_0_OTPT_STTNG_MSK       (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
-// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
+#define OUTPUT_DELAY_0_OTPT_STTNG_OFST                                         \
+    (0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
+#define OUTPUT_DELAY_0_OTPT_STTNG_MSK                                          \
+    (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
+// 1: load dynamic output settings, 0: trigger start of dynamic output delay
+// configuration pn falling edge of ODT (output delay trigger) bit
 #define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
-#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK       (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
+#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK                                          \
+    (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
 #define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL   (1)
 #define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
 
@@ -550,6 +581,3 @@
 
 /* Round Robin  */
 #define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
-
-
-

slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h

@@ -1,7 +1,6 @@
 #pragma once
-#include "sls_detector_defs.h"
 #include "RegisterDefs.h"
-
+#include "sls_detector_defs.h"
 
 #define MIN_REQRD_VRSN_T_RD_API 0x181130
 #define REQRD_FRMWR_VRSN        0x191127
@@ -36,10 +35,53 @@ typedef struct udp_header_struct {
 #define UDP_IP_HEADER_LENGTH_BYTES (28)
 
 /* Enums */
-enum ADCINDEX				{V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D, S_ADC0, S_ADC1, S_ADC2, S_ADC3, S_ADC4, S_ADC5, S_ADC6, S_ADC7, S_TMP};
-enum DACINDEX               {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
-                             D10, D11, D12, D13, D14, D15, D16, D17,
-                             D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
+enum ADCINDEX {
+    V_PWR_IO,
+    V_PWR_A,
+    V_PWR_B,
+    V_PWR_C,
+    V_PWR_D,
+    I_PWR_IO,
+    I_PWR_A,
+    I_PWR_B,
+    I_PWR_C,
+    I_PWR_D,
+    S_ADC0,
+    S_ADC1,
+    S_ADC2,
+    S_ADC3,
+    S_ADC4,
+    S_ADC5,
+    S_ADC6,
+    S_ADC7,
+    S_TMP
+};
+enum DACINDEX {
+    D0,
+    D1,
+    D2,
+    D3,
+    D4,
+    D5,
+    D6,
+    D7,
+    D8,
+    D9,
+    D10,
+    D11,
+    D12,
+    D13,
+    D14,
+    D15,
+    D16,
+    D17,
+    D_PWR_D,
+    D_PWR_CHIP,
+    D_PWR_C,
+    D_PWR_B,
+    D_PWR_A,
+    D_PWR_IO
+};
 enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
 #define CLK_NAMES "run", "adc", "sync", "dbit"
 
@@ -85,16 +127,21 @@ enum CLKINDEX               {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
 #define VCHIP_MIN_MV    (1673)
 #define VCHIP_MAX_MV    (2668) // min dac val
 #define POWER_RGLTR_MIN (636)
-#define POWER_RGLTR_MAX             (2638) // min dac val (not vchip-max) because of dac conversions
+#define POWER_RGLTR_MAX                                                        \
+    (2638) // min dac val (not vchip-max) because of dac conversions
 #define VCHIP_POWER_INCRMNT (200)
 #define VIO_MIN_MV          (1200) // for fpga to function
 
 /* Defines in the Firmware */
 #define MAX_PATTERN_LENGTH (0x2000)
-#define DIGITAL_IO_DELAY_MAXIMUM_PS	((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
+#define DIGITAL_IO_DELAY_MAXIMUM_PS                                            \
+    ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) *       \
+     OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
 #define MAX_PHASE_SHIFTS_STEPS (8)
 
-#define WAIT_TME_US_FR_ACQDONE_REG 	(100) // wait time in us after acquisition done to ensure there is no data in fifo
+#define WAIT_TME_US_FR_ACQDONE_REG                                             \
+    (100) // wait time in us after acquisition done to ensure there is no data
+          // in fifo
 #define WAIT_TIME_US_PLL           (10 * 1000)
 #define WAIT_TIME_US_STP_ACQ       (100)
 #define WAIT_TIME_CONFIGURE_MAC    (2 * 1000 * 1000)
@@ -109,4 +156,3 @@ enum CLKINDEX               {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
 
 #define MAXIMUM_ADC_CLK  (65)
 #define PLL_VCO_FREQ_MHZ (800)
-

slsDetectorServers/eigerDetectorServer/9mhvserial_bf.c

@@ -1,14 +1,14 @@
 #include "ansi.h"
 
-#include <termios.h>  	/* POSIX terminal control definitions */
+#include <errno.h>
+#include <fcntl.h>         // File control definitions
+#include <linux/i2c-dev.h> // I2C_SLAVE, __u8 reg
 #include <stdio.h>
 #include <stdlib.h>    // atoi
-#include <fcntl.h>			// File control definitions
-#include <sys/ioctl.h>		// ioctl
-#include <unistd.h>			// read, close
 #include <string.h>    // memset
-#include <linux/i2c-dev.h>	// I2C_SLAVE, __u8 reg
-#include <errno.h>
+#include <sys/ioctl.h> // ioctl
+#include <termios.h>   /* POSIX terminal control definitions */
+#include <unistd.h>    // read, close
 
 #define PORTNAME           "/dev/ttyBF1"
 #define GOODBYE            200
@@ -18,8 +18,6 @@
 //#define I2C_DEVICE_ADDRESS	0x48
 #define I2C_REGISTER_ADDRESS 0x40
 
-
-
 int i2c_open(const char *file, unsigned int addr) {
 
     // device file
@@ -37,7 +35,6 @@ int i2c_open(const char* file,unsigned int addr){
     return fd;
 }
 
-
 int i2c_read() {
 
     int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
@@ -45,7 +42,8 @@ int i2c_read(){
 
     unsigned char buf = reg;
     if (write(fd, &buf, 1) != 1) {
-		LOG(logERROR, ("Warning: Unable to write read request to register %d\n", reg));
+        LOG(logERROR,
+            ("Warning: Unable to write read request to register %d\n", reg));
         return -1;
     }
     // read and update value (but old value read out)
@@ -62,7 +60,6 @@ int i2c_read(){
     return buf;
 }
 
-
 int i2c_write(unsigned int value) {
 
     __u8 val = value & 0xff;
@@ -76,7 +73,8 @@ int i2c_write(unsigned int value){
     buf[0] = reg;
     buf[1] = val;
     if (write(fd, buf, 2) != 2) {
-		LOG(logERROR, ("Warning: Unable to write %d to register %d\n",val, reg));
+        LOG(logERROR,
+            ("Warning: Unable to write %d to register %d\n", val, reg));
         return -1;
     }
 
@@ -84,10 +82,6 @@ int i2c_write(unsigned int value){
     return 0;
 }
 
-
-
-
-
 int main(int argc, char *argv[]) {
 
     int fd = open(PORTNAME, O_RDWR | O_NOCTTY | O_SYNC);
@@ -113,7 +107,8 @@ int main(int argc, char* argv[]) {
         LOG(logERROR, ("Warning: error form tcflush %d\n", errno));
         return 0;
     }
-	// set new options for the port, TCSANOW:changes occur immediately without waiting for data to complete
+    // set new options for the port, TCSANOW:changes occur immediately without
+    // waiting for data to complete
     if (tcsetattr(fd, TCSANOW, &serial_conf) < 0) {
         LOG(logERROR, ("Warning: error form tcsetattr %d\n", errno));
         return 0;
@@ -132,7 +127,6 @@ int main(int argc, char* argv[]) {
     buffer[BUFFERSIZE - 1] = '\n';
     LOG(logINFO, ("Ready...\n"));
 
-
     while (ret != GOODBYE) {
         memset(buffer, 0, BUFFERSIZE);
         n = read(fd, buffer, BUFFERSIZE);
@@ -183,7 +177,8 @@ int main(int argc, char* argv[]) {
                 sprintf(buffer, "%d ", ival);
                 n = write(fd, buffer, BUFFERSIZE);
                 LOG(logINFO, ("Sent %d Bytes\n", n));
-			}else LOG(logERROR, ("%s\n",buffer));
+            } else
+                LOG(logERROR, ("%s\n", buffer));
             break;
 
         case 'e':

slsDetectorServers/eigerDetectorServer/Beb.h

@@ -1,10 +1,9 @@
 #pragma once
 
-
+#include <stdlib.h>
 #include "LocalLinkInterface.h"
 #include "slsDetectorServer_defs.h"
 
-
 struct BebInfo {
     unsigned int beb_number;
     unsigned int serial_address;
@@ -16,11 +15,13 @@ struct BebInfo{
     unsigned int src_port_10GbE;
 };
 
-
 void BebInfo_BebInfo(struct BebInfo *bebInfo, unsigned int beb_num);
 void BebInfo_BebDstInfo(struct BebInfo *bebInfo, unsigned int beb_num);
 int BebInfo_SetSerialAddress(struct BebInfo *bebInfo, unsigned int add);
-int BebInfo_SetHeaderInfo(struct BebInfo* bebInfo, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);//src_port fixed 42000+beb_number or 52000 + beb_number);
+int BebInfo_SetHeaderInfo(
+    struct BebInfo *bebInfo, int ten_gig, char *src_mac, char *src_ip,
+    unsigned int
+        src_port); // src_port fixed 42000+beb_number or 52000 + beb_number);
 unsigned int BebInfo_GetBebNumber(struct BebInfo *bebInfo);
 unsigned int BebInfo_GetSerialAddress(struct BebInfo *bebInfo);
 char *BebInfo_GetSrcMAC(struct BebInfo *bebInfo, int ten_gig);
@@ -32,7 +33,6 @@ int Beb_InitBebInfos();
 int Beb_CheckSourceStuffBebInfo();
 unsigned int Beb_GetBebInfoIndex(unsigned int beb_numb);
 
-
 void Beb_GetModuleConfiguration(int *master, int *top, int *normal);
 int Beb_IsTransmitting(int *retval, int tengiga, int waitForDelay);
 
@@ -61,22 +61,38 @@ int Beb_SetIP(char* ip, uint8_t* dst_ptr);
 int Beb_SetPortNumber(unsigned int port_number, uint8_t *dst_ptr);
 void Beb_AdjustIPChecksum(struct udp_header_type *ip);
 
-int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char* dst_mac, char* dst_ip, unsigned int dst_port);
-int Beb_SetHeaderData1(char* src_mac, char* src_ip, unsigned int src_port, char* dst_mac, char* dst_ip, unsigned int dst_port);
+int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char *dst_mac,
+                      char *dst_ip, unsigned int dst_port);
+int Beb_SetHeaderData1(char *src_mac, char *src_ip, unsigned int src_port,
+                       char *dst_mac, char *dst_ip, unsigned int dst_port);
 
 void Beb_SwapDataFun(int little_endian, unsigned int n, unsigned int *d);
 int Beb_SetByteOrder();
 void Beb_Beb();
-int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);
-int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig, unsigned int header_number, char* dst_mac, char* dst_ip, unsigned int dst_port);
+int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig,
+                             char *src_mac, char *src_ip,
+                             unsigned int src_port);
+int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig,
+                       unsigned int header_number, char *dst_mac, char *dst_ip,
+                       unsigned int dst_port);
 
-/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int  left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
-int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int  left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty);
+/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int
+ * left_right, int ten_gig, unsigned int dst_number, unsigned int npackets,
+ * unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
+int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right,
+                             int ten_gig, unsigned int dst_number,
+                             unsigned int npackets, unsigned int packet_size,
+                             int stop_read_when_fifo_empty);
 
 int Beb_StopAcquisition();
 int Beb_SetUpTransferParameters(short the_bit_mode);
-/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait=0); //all images go to the same destination!*/
-int Beb_RequestNImages(unsigned int beb_number, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait);
+/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int
+ * ten_gig, unsigned int dst_number, unsigned int nimages, int
+ * test_just_send_out_packets_no_wait=0); //all images go to the same
+ * destination!*/
+int Beb_RequestNImages(unsigned int beb_number, int ten_gig,
+                       unsigned int dst_number, unsigned int nimages,
+                       int test_just_send_out_packets_no_wait);
 
 int Beb_Test(unsigned int beb_number);
 
@@ -97,5 +113,3 @@ int Beb_open(u_int32_t** csp0base, u_int32_t offset);
 u_int32_t Beb_Read32(u_int32_t *baseaddr, u_int32_t offset);
 u_int32_t Beb_Write32(u_int32_t *baseaddr, u_int32_t offset, u_int32_t data);
 void Beb_close(int fd, u_int32_t *csp0base);
-
-

slsDetectorServers/eigerDetectorServer/FebControl.h

@@ -2,7 +2,6 @@
 #include "FebInterface.h"
 #include <netinet/in.h>
 
-
 struct Module {
     unsigned int module_number;
     int top_address_valid;
@@ -19,10 +18,12 @@ struct Module{
     int *bottom_dac;
 };
 
-
-void Module_Module(struct Module* mod,unsigned int number, unsigned int address_top);
-void Module_ModuleBottom(struct Module* mod,unsigned int number, unsigned int address_bottom);
-void Module_Module1(struct Module* mod,unsigned int number, unsigned int address_top, unsigned int address_bottom);
+void Module_Module(struct Module *mod, unsigned int number,
+                   unsigned int address_top);
+void Module_ModuleBottom(struct Module *mod, unsigned int number,
+                         unsigned int address_bottom);
+void Module_Module1(struct Module *mod, unsigned int number,
+                    unsigned int address_top, unsigned int address_bottom);
 unsigned int Module_GetModuleNumber(struct Module *mod);
 int Module_TopAddressIsValid(struct Module *mod);
 unsigned int Module_GetTopBaseAddress(struct Module *mod);
@@ -32,9 +33,11 @@ unsigned int Module_GetBottomBaseAddress(struct Module* mod);
 int Module_BottomAddressIsValid(struct Module *mod);
 unsigned int Module_GetBottomLeftAddress(struct Module *mod);
 unsigned int Module_GetBottomRightAddress(struct Module *mod);
-unsigned int Module_SetTopIDelay(struct Module* mod,unsigned int chip,unsigned int value);
+unsigned int Module_SetTopIDelay(struct Module *mod, unsigned int chip,
+                                 unsigned int value);
 unsigned int Module_GetTopIDelay(struct Module *mod, unsigned int chip);
-unsigned int Module_SetBottomIDelay(struct Module* mod,unsigned int chip,unsigned int value);
+unsigned int Module_SetBottomIDelay(struct Module *mod, unsigned int chip,
+                                    unsigned int value);
 unsigned int Module_GetBottomIDelay(struct Module *mod, unsigned int chip);
 
 float Module_SetHighVoltage(struct Module *mod, float value);
@@ -45,29 +48,36 @@ int Module_GetTopDACValue(struct Module* mod,unsigned int i);
 int Module_SetBottomDACValue(struct Module *mod, unsigned int i, int value);
 int Module_GetBottomDACValue(struct Module *mod, unsigned int i);
 
-
 void Feb_Control_activate(int activate);
 
 int Feb_Control_IsBottomModule();
 int Feb_Control_GetModuleNumber();
 
 void Feb_Control_PrintModuleList();
-int Feb_Control_GetModuleIndex(unsigned int module_number, unsigned int* module_index);
+int Feb_Control_GetModuleIndex(unsigned int module_number,
+                               unsigned int *module_index);
 int Feb_Control_CheckModuleAddresses(struct Module *m);
 int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address);
-int Feb_Control_AddModule1(unsigned int module_number, int top_enable, unsigned int top_address, unsigned int bottom_address, int half_module);
+int Feb_Control_AddModule1(unsigned int module_number, int top_enable,
+                           unsigned int top_address,
+                           unsigned int bottom_address, int half_module);
 int Feb_Control_GetDACNumber(char *s, unsigned int *n);
-int  Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, unsigned int* value);
-int  Feb_Control_VoltageToDAC(float value, unsigned int* digital, unsigned int nsteps, float vmin, float vmax);
-float Feb_Control_DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
-int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr, unsigned int channels, unsigned int ndelay_units);
+int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch,
+                             unsigned int *value);
+int Feb_Control_VoltageToDAC(float value, unsigned int *digital,
+                             unsigned int nsteps, float vmin, float vmax);
+float Feb_Control_DACToVoltage(unsigned int digital, unsigned int nsteps,
+                               float vmin, float vmax);
+int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr,
+                            unsigned int channels, unsigned int ndelay_units);
 int Feb_Control_SetStaticBits();
 int Feb_Control_SetStaticBits1(unsigned int the_static_bits);
 int Feb_Control_SendBitModeToBebServer();
 unsigned int Feb_Control_ConvertTimeToRegister(float time_in_sec);
 unsigned int Feb_Control_AddressToAll();
 int Feb_Control_SetCommandRegister(unsigned int cmd);
-int Feb_Control_GetDAQStatusRegister(unsigned int dst_address, unsigned int* ret_status);
+int Feb_Control_GetDAQStatusRegister(unsigned int dst_address,
+                                     unsigned int *ret_status);
 int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us);
 int Feb_Control_ResetChipCompletely();
 int Feb_Control_ResetChipPartially();
@@ -86,14 +96,17 @@ int Feb_Control_SendHighVoltage(int dacvalue);
 int Feb_Control_ReceiveHighVoltage(unsigned int *value);
 
 int Feb_Control_SetIDelays(unsigned int module_num, unsigned int ndelay_units);
-int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
+int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos,
+                            unsigned int ndelay_units);
 
-int Feb_Control_DecodeDACString(char* dac_str, unsigned int* module_index, int* top, int* bottom, unsigned int* dac_ch);
+int Feb_Control_DecodeDACString(char *dac_str, unsigned int *module_index,
+                                int *top, int *bottom, unsigned int *dac_ch);
 int Feb_Control_SetDAC(char *s, int value, int is_a_voltage_mv);
 int Feb_Control_GetDAC(char *s, int *ret_value, int voltage_mv);
 int Feb_Control_GetDACName(unsigned int dac_num, char *s);
 
-int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int* trimbits, int top);
+int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int *trimbits,
+                            int top);
 unsigned int *Feb_Control_GetTrimbits();
 int Feb_Control_SaveAllTrimbitsTo(int value, int top);
 int Feb_Control_Reset();
@@ -111,7 +124,8 @@ unsigned int Feb_Control_GetNExposures();
 int Feb_Control_SetExposureTime(double the_exposure_time_in_sec);
 double Feb_Control_GetExposureTime();
 int64_t Feb_Control_GetExposureTime_in_nsec();
-int Feb_Control_SetSubFrameExposureTime(int64_t the_subframe_exposure_time_in_10nsec);
+int Feb_Control_SetSubFrameExposureTime(
+    int64_t the_subframe_exposure_time_in_10nsec);
 int64_t Feb_Control_GetSubFrameExposureTime();
 int Feb_Control_SetSubFramePeriod(int64_t the_subframe_period_in_10nsec);
 int64_t Feb_Control_GetSubFramePeriod();
@@ -119,10 +133,17 @@ int Feb_Control_SetExposurePeriod(double the_exposure_period_in_sec);
 double Feb_Control_GetExposurePeriod();
 int Feb_Control_SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
 unsigned int Feb_Control_GetDynamicRange();
-int Feb_Control_SetReadoutSpeed(unsigned int readout_speed); //0 was default, 0->full,1->half,2->quarter or 3->super_slow
-int Feb_Control_SetReadoutMode(unsigned int readout_mode); ///0 was default,0->parallel,1->non-parallel,2-> safe_mode
-int Feb_Control_SetTriggerMode(unsigned int trigger_mode, int polarity);//0 and 1 was default,
-int Feb_Control_SetExternalEnableMode(int use_external_enable, int polarity);//0 and 1 was default,
+int Feb_Control_SetReadoutSpeed(
+    unsigned int readout_speed); // 0 was default, 0->full,1->half,2->quarter or
+                                 // 3->super_slow
+int Feb_Control_SetReadoutMode(
+    unsigned int readout_mode); /// 0 was
+                                /// default,0->parallel,1->non-parallel,2->
+                                /// safe_mode
+int Feb_Control_SetTriggerMode(unsigned int trigger_mode,
+                               int polarity); // 0 and 1 was default,
+int Feb_Control_SetExternalEnableMode(int use_external_enable,
+                                      int polarity); // 0 and 1 was default,
 
 int Feb_Control_SetInTestModeVariable(int on);
 int Feb_Control_GetTestModeVariable();
@@ -159,4 +180,3 @@ int Feb_Control_GetReadNLines();
 
 int Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
 int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval);
-

slsDetectorServers/eigerDetectorServer/FebInterface.c

@@ -1,12 +1,10 @@
 #include "FebInterface.h"
 #include "LocalLinkInterface.h"
-#include "xparameters.h"
 #include "clogger.h"
+#include "xparameters.h"
 
 #include <unistd.h>
 
-
-
 struct LocalLinkInterface ll_local, *ll;
 
 unsigned int Feb_Interface_nfebs;
@@ -22,7 +20,6 @@ unsigned int  Feb_Interface_recv_buffer_size;
 unsigned int *Feb_Interface_recv_data_raw;
 unsigned int *Feb_Interface_recv_data;
 
-
 void Feb_Interface_FebInterface() {
     ll = &ll_local;
     Feb_Interface_nfebs = 0;
@@ -30,46 +27,54 @@ void Feb_Interface_FebInterface() {
 
     Feb_Interface_send_ndata = 0;
     Feb_Interface_send_buffer_size = 1026;
-	Feb_Interface_send_data_raw = malloc((Feb_Interface_send_buffer_size+1) * sizeof(unsigned int));
+    Feb_Interface_send_data_raw =
+        malloc((Feb_Interface_send_buffer_size + 1) * sizeof(unsigned int));
     Feb_Interface_send_data = &Feb_Interface_send_data_raw[1];
 
     Feb_Interface_recv_ndata = 0;
     Feb_Interface_recv_buffer_size = 1026;
-	Feb_Interface_recv_data_raw = malloc((Feb_Interface_recv_buffer_size+1) * sizeof(unsigned int));
+    Feb_Interface_recv_data_raw =
+        malloc((Feb_Interface_recv_buffer_size + 1) * sizeof(unsigned int));
     Feb_Interface_recv_data = &Feb_Interface_recv_data_raw[1];
 
-	Local_LocalLinkInterface1(ll,XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
-
+    Local_LocalLinkInterface1(
+        ll, XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
 }
 
-
-
 void Feb_Interface_SendCompleteList(unsigned int n, unsigned int *list) {
     unsigned int i;
-	if (Feb_Interface_feb_numb) free(Feb_Interface_feb_numb);
+    if (Feb_Interface_feb_numb)
+        free(Feb_Interface_feb_numb);
     Feb_Interface_nfebs = n;
     Feb_Interface_feb_numb = malloc(n * sizeof(unsigned int));
-	for(i=0;i<n;i++) Feb_Interface_feb_numb[i] = list[i];
+    for (i = 0; i < n; i++)
+        Feb_Interface_feb_numb[i] = list[i];
 }
 
 int Feb_Interface_WriteTo(unsigned int ch) {
-	if (ch>0xfff) return 0;
+    if (ch > 0xfff)
+        return 0;
 
     LOG(logDEBUG1, ("FIW ch %d\n", ch));
 
     Feb_Interface_send_data_raw[0] = 0x8fff0000;
-if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
+    if (Local_Write(ll, 4, Feb_Interface_send_data_raw) != 4)
+        return 0;
 
     Feb_Interface_send_data_raw[0] = 0x90000000 | (ch << 16);
-if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
+    if (Local_Write(ll, 4, Feb_Interface_send_data_raw) != 4)
+        return 0;
 
     Feb_Interface_send_data_raw[0] = 0xc0000000;
-return ((Feb_Interface_send_ndata+1)*4==Local_Write(ll,(Feb_Interface_send_ndata+1)*4,Feb_Interface_send_data_raw));
+    return ((Feb_Interface_send_ndata + 1) * 4 ==
+            Local_Write(ll, (Feb_Interface_send_ndata + 1) * 4,
+                        Feb_Interface_send_data_raw));
 }
 
 int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys) {
     unsigned int t;
-	if (ch>=0xfff) return 0;
+    if (ch >= 0xfff)
+        return 0;
 
     Feb_Interface_recv_data_raw[0] = 0xa0000000 | (ch << 16);
     Local_Write(ll, 4, Feb_Interface_recv_data_raw);
@@ -77,7 +82,10 @@ int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys) {
 
     Feb_Interface_recv_ndata = -1;
     for (t = 0; t < ntrys; t++) {
-		if ((Feb_Interface_recv_ndata=Local_Read(ll,Feb_Interface_recv_buffer_size*4,Feb_Interface_recv_data_raw)/4)>0) {
+        if ((Feb_Interface_recv_ndata =
+                 Local_Read(ll, Feb_Interface_recv_buffer_size * 4,
+                            Feb_Interface_recv_data_raw) /
+                 4) > 0) {
             Feb_Interface_recv_ndata--;
             break;
         }
@@ -87,80 +95,110 @@ int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys) {
     return (Feb_Interface_recv_ndata >= 0);
 }
 
-
-
 int Feb_Interface_SetByteOrder() {
     Feb_Interface_send_data_raw[0] = 0x8fff0000;
-	if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
+    if (Local_Write(ll, 4, Feb_Interface_send_data_raw) != 4)
+        return 0;
     Feb_Interface_send_ndata = 2;
     Feb_Interface_send_data[0] = 0;
     Feb_Interface_send_data[1] = 0;
     unsigned int i;
     unsigned int dst = 0xff;
-	for(i=0;i<Feb_Interface_nfebs;i++) dst = (dst | Feb_Interface_feb_numb[i]);
+    for (i = 0; i < Feb_Interface_nfebs; i++)
+        dst = (dst | Feb_Interface_feb_numb[i]);
     int passed = Feb_Interface_WriteTo(dst);
 
     return passed;
 }
 
-
-int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read) {
+int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,
+                               unsigned int *value_read) {
     return Feb_Interface_ReadRegisters(sub_num, 1, &reg_num, value_read);
 }
 
-
-int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read) {
+int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads,
+                                unsigned int *reg_nums,
+                                unsigned int *values_read) {
     // here   cout<<"Reading Register ...."<<endl;
     unsigned int i;
     nreads &= 0x3ff;
-	if (!nreads||nreads>Feb_Interface_send_buffer_size-2) return 0;
+    if (!nreads || nreads > Feb_Interface_send_buffer_size - 2)
+        return 0;
 
     Feb_Interface_send_ndata = nreads + 2;
     Feb_Interface_send_data[0] = 0x20000000 | nreads << 14;
 
-	for(i=0;i<nreads;i++) Feb_Interface_send_data[i+1]=reg_nums[i];
+    for (i = 0; i < nreads; i++)
+        Feb_Interface_send_data[i + 1] = reg_nums[i];
     Feb_Interface_send_data[nreads + 1] = 0;
 
-	if (!Feb_Interface_WriteTo(sub_num)||!Feb_Interface_ReadFrom(sub_num,20)||Feb_Interface_recv_ndata!=(int)(nreads+2)) return 0;
+    if (!Feb_Interface_WriteTo(sub_num) ||
+        !Feb_Interface_ReadFrom(sub_num, 20) ||
+        Feb_Interface_recv_ndata != (int)(nreads + 2))
+        return 0;
 
-	for(i=0;i<nreads;i++) values_read[i] = Feb_Interface_recv_data[i+1];
+    for (i = 0; i < nreads; i++)
+        values_read[i] = Feb_Interface_recv_data[i + 1];
 
     return 1;
 }
 
-int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address) {
-	return Feb_Interface_WriteRegisters(sub_num,1,&reg_num,&value,&wait_on,&wait_on_address);
+int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,
+                                unsigned int value, int wait_on,
+                                unsigned int wait_on_address) {
+    return Feb_Interface_WriteRegisters(sub_num, 1, &reg_num, &value, &wait_on,
+                                        &wait_on_address);
 }
 
-int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses) {
+int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites,
+                                 unsigned int *reg_nums, unsigned int *values,
+                                 int *wait_ons,
+                                 unsigned int *wait_on_addresses) {
     unsigned int i;
     nwrites &= 0x3ff; // 10 bits
-	if (!nwrites||2*nwrites>Feb_Interface_send_buffer_size-2) return 0;
+    if (!nwrites || 2 * nwrites > Feb_Interface_send_buffer_size - 2)
+        return 0;
 
-	//cout<<"Write register : "<<this<<"  "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
+    // cout<<"Write register : "<<this<<"  "<<s_num<<" "<<nwrites<<"
+    // "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
     Feb_Interface_send_ndata = 2 * nwrites + 2;
     Feb_Interface_send_data[0] = 0x80000000 | nwrites << 14;
     Feb_Interface_send_data[2 * nwrites + 1] = 0;
 
-	for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] = 0x3fff&reg_nums[i];
-	for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+2] = values[i];
+    for (i = 0; i < nwrites; i++)
+        Feb_Interface_send_data[2 * i + 1] = 0x3fff & reg_nums[i];
+    for (i = 0; i < nwrites; i++)
+        Feb_Interface_send_data[2 * i + 2] = values[i];
     // wait on busy data(28), address of busy flag data(27 downto 14)
-	if (wait_ons&&wait_on_addresses) for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
+    if (wait_ons && wait_on_addresses)
+        for (i = 0; i < nwrites; i++)
+            Feb_Interface_send_data[2 * i + 1] |=
+                (wait_ons[i] << 28 | (0x3fff & wait_on_addresses[i]) << 14);
 
-	if (!Feb_Interface_WriteTo(sub_num)) return 0;
+    if (!Feb_Interface_WriteTo(sub_num))
+        return 0;
 
     return 1;
 }
 
-int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values) {
+int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num,
+                                     unsigned int start_address,
+                                     unsigned int nwrites,
+                                     unsigned int *values) {
     unsigned int max_single_packet_size = 352;
     int passed = 1;
     unsigned int n_to_send = max_single_packet_size;
     unsigned int ndata_sent = 0;
     unsigned int ndata_countdown = nwrites;
     while (ndata_countdown > 0) {
-		n_to_send = ndata_countdown<max_single_packet_size ? ndata_countdown:max_single_packet_size;
-		if (!Feb_Interface_WriteMemory(sub_num,mem_num,start_address,n_to_send,&(values[ndata_sent]))) {passed=0; break;}
+        n_to_send = ndata_countdown < max_single_packet_size
+                        ? ndata_countdown
+                        : max_single_packet_size;
+        if (!Feb_Interface_WriteMemory(sub_num, mem_num, start_address,
+                                       n_to_send, &(values[ndata_sent]))) {
+            passed = 0;
+            break;
+        }
         ndata_countdown -= n_to_send;
         ndata_sent += n_to_send;
         start_address += n_to_send;
@@ -169,7 +207,9 @@ int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num,
     return passed;
 }
 
-int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values) {
+int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num,
+                              unsigned int start_address, unsigned int nwrites,
+                              unsigned int *values) {
     // -1 means write to all
     unsigned int i;
     mem_num &= 0x3f;
@@ -181,15 +221,16 @@ int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsign
     } //*d-1026
 
     Feb_Interface_send_ndata = nwrites + 2; //*d-1026
-	Feb_Interface_send_data[0]         = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
+    Feb_Interface_send_data[0] =
+        0xc0000000 | mem_num << 24 | nwrites << 14 |
+        start_address; // cmd -> write to memory, nwrites, mem number, start
+                       // address
     Feb_Interface_send_data[nwrites + 1] = 0;
-	for(i=0;i<nwrites;i++) Feb_Interface_send_data[i+1] = values[i];
+    for (i = 0; i < nwrites; i++)
+        Feb_Interface_send_data[i + 1] = values[i];
 
-
-	if (!Feb_Interface_WriteTo(sub_num)) return 0;
+    if (!Feb_Interface_WriteTo(sub_num))
+        return 0;
 
     return 1;
 }
-
-
-

slsDetectorServers/eigerDetectorServer/FebInterface.h

@@ -5,10 +5,22 @@ int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys);
 void Feb_Interface_FebInterface();
 void Feb_Interface_SendCompleteList(unsigned int n, unsigned int *list);
 int Feb_Interface_SetByteOrder();
-int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
-int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
-int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
-int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
-int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
-int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
-
+int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,
+                               unsigned int *value_read);
+int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads,
+                                unsigned int *reg_nums,
+                                unsigned int *values_read);
+int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,
+                                unsigned int value, int wait_on,
+                                unsigned int wait_on_address);
+int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites,
+                                 unsigned int *reg_nums, unsigned int *values,
+                                 int *wait_ons,
+                                 unsigned int *wait_on_addresses);
+int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num,
+                                     unsigned int start_address,
+                                     unsigned int nwrites,
+                                     unsigned int *values);
+int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num,
+                              unsigned int start_address, unsigned int nwrites,
+                              unsigned int *values);

slsDetectorServers/eigerDetectorServer/FebRegisterDefs.h

@@ -22,16 +22,16 @@
 #define DAQ_REG_HRDWRE_TOP_OFST        (1)
 #define DAQ_REG_HRDWRE_TOP_MSK         (0x00000001 << DAQ_REG_HRDWRE_TOP_OFST)
 #define DAQ_REG_HRDWRE_INTRRPT_SF_OFST (2)
-#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK   (0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
+#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK                                          \
+    (0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
 
 #define DAQ_REG_RO_OFFSET 20
-#define DAQ_REG_STATUS					(DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
+#define DAQ_REG_STATUS                                                         \
+    (DAQ_REG_RO_OFFSET + 0) // also pg and fifo status register
 #define FEB_REG_STATUS     (DAQ_REG_RO_OFFSET + 3)
 #define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)
 #define MEAS_PERIOD_REG    (DAQ_REG_RO_OFFSET + 5)
 
-
-
 #define DAQ_CTRL_RESET 0x80000000
 #define DAQ_CTRL_START 0x40000000
 #define ACQ_CTRL_START 0x50000000 // this is 0x10000000 (acq) | 0x40000000 (daq)
@@ -54,7 +54,8 @@
 
 #define DAQ_IGNORE_INITIAL_CRAP 0x00000400 // crap before readout
 #define DAQ_READOUT_NROWS       0x00000800
-#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
+#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START                             \
+    0x00001000 // last 4 bit of data in the last frame
 
 #define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT  0x00002000
 #define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
@@ -63,52 +64,62 @@
 #define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
 #define DAQ_SEND_N_TEST_PULSES                0x00020000
 
-#define DAQ_CHIP_CONTROLLER_HALF_SPEED         0x00040000 //everything at 100 MHz (50MHz ddr readout)
-#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED      0x00080000 //everything at  50 MHz (25MHz ddr readout)
-#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED   0x000c0000 //everything at  ~200 kHz (200 kHz MHz ddr readout)
+#define DAQ_CHIP_CONTROLLER_HALF_SPEED                                         \
+    0x00040000 // everything at 100 MHz (50MHz ddr readout)
+#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED                                      \
+    0x00080000 // everything at  50 MHz (25MHz ddr readout)
+#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED                                   \
+    0x000c0000 // everything at  ~200 kHz (200 kHz MHz ddr readout)
 
-//#define DAQ_FIFO_ENABLE                       0x00100000 commented out as it is not used anywhere
+//#define DAQ_FIFO_ENABLE                       0x00100000 commented out as it
+// is not used anywhere
 #define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
 
 // direct chip commands to the DAQ_REG_CHIP_CMDS register
-#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
-#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE         0x00400000 //expose ->readout ->expose -> ..., with store is always closed
+#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE                        \
+    0x00200000 // row clk is before main clk readout sequence
+#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE                                \
+    0x00400000 // expose ->readout ->expose -> ..., with store is always closed
 #define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 // parallel acquire/read mode
 
-//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
-//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES    0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
+// DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware
+// that every image comes with a header #define
+// DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES    0x00800000
+////DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
 
 #define DAQ_NEXPOSURERS_EXTERNAL_ENABLING          0x01000000
 #define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
 #define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY  0x04000000
 
 #define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 // internally controlled
-#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START    0x08000000 //external acquisition start
+#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START                             \
+    0x08000000 // external acquisition start
 #define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 // external image start
-#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
+#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP                          \
+    0x18000000 // externally controlly, external image start and stop
 
 #define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
 #define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
 
-//#define DAQ_MASTER_HALF_MODULE                        0x80000000 currently not used
-
+//#define DAQ_MASTER_HALF_MODULE                        0x80000000 currently not
+// used
 
 // chips static bits
 #define DAQ_STATIC_BIT_PROGRAM 0x00000001
 #define DAQ_STATIC_BIT_M4      0x00000002 // these are the status bits, not bit mode
 #define DAQ_STATIC_BIT_M8      0x00000004 // these are the status bits, not bit mode
-#define DAQ_STATIC_BIT_M12          0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
+#define DAQ_STATIC_BIT_M12                                                     \
+    0x00000000 // these are the status bits, not bit mode, ie. "00" is 12 bit
+               // mode
 #define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
 #define DAQ_STATIC_BIT_ROTEST    0x00000010
 #define DAQ_CS_BAR_LEFT          0x00000020
 #define DAQ_CS_BAR_RIGHT         0x00000040
 
-
 // status flags
 #define DAQ_STATUS_DAQ_RUNNING   0x01
 #define DAQ_DATA_COLLISION_ERROR 0x02
 
-
 #define DAQ_STATUS_CURRENT_M4         0x04
 #define DAQ_STATUS_CURRENT_M8         0x08
 #define DAQ_STATUS_CURRENT_M12        0x00 // in 12 bit mode both are cleared
@@ -146,7 +157,8 @@
 #define FLOW_REG_OFFSET        0x140
 
 #define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST (0)
-#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK		(0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
+#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK                                        \
+    (0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
 #define FLOW_REG_OVERFLOW_32_BIT_OFST (2)
 #define FLOW_REG_OVERFLOW_32_BIT_MSK  (0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
 
@@ -210,19 +222,3 @@
 #define UDP_HEADER_Z_MSK   (0xFFFF << UDP_HEADER_Z_OFST)
 #define UDP_HEADER_Y_OFST  (16)
 #define UDP_HEADER_Y_MSK   (0xFFFF << UDP_HEADER_Y_OFST)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

slsDetectorServers/eigerDetectorServer/HardwareIO.c

@@ -1,49 +1,42 @@
 #include "HardwareIO.h"
 
-xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress)
-{
+xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress) {
     /* read the contents of the I/O location and then synchronize the I/O
      * such that the I/O operation completes before proceeding on
      */
 
     xfs_u8 IoContents;
-    __asm__ volatile ("eieio; lbz %0,0(%1)":"=r" (IoContents):"b"
-              (InAddress));
+    __asm__ volatile("eieio; lbz %0,0(%1)" : "=r"(IoContents) : "b"(InAddress));
     return IoContents;
 }
 
 /*****************************************************************************/
 
-xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress)
-{
+xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress) {
     /* read the contents of the I/O location and then synchronize the I/O
      * such that the I/O operation completes before proceeding on
      */
 
     xfs_u16 IoContents;
-    __asm__ volatile ("eieio; lhz %0,0(%1)":"=r" (IoContents):"b"
-              (InAddress));
+    __asm__ volatile("eieio; lhz %0,0(%1)" : "=r"(IoContents) : "b"(InAddress));
     return IoContents;
 }
 
 /*****************************************************************************/
 
-xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress)
-{
+xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress) {
     /* read the contents of the I/O location and then synchronize the I/O
      * such that the I/O operation completes before proceeding on
      */
 
     xfs_u32 IoContents;
-    __asm__ volatile ("eieio; lwz %0,0(%1)":"=r" (IoContents):"b"
-              (InAddress));
+    __asm__ volatile("eieio; lwz %0,0(%1)" : "=r"(IoContents) : "b"(InAddress));
     return IoContents;
 }
 
 /*****************************************************************************/
 
-void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value)
-{
+void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value) {
     /* write the contents of the I/O location and then synchronize the I/O
      * such that the I/O operation completes before proceeding on
      */
@@ -52,8 +45,7 @@ void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value)
 }
 
 /*****************************************************************************/
-void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value)
-{
+void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value) {
     /* write the contents of the I/O location and then synchronize the I/O
      * such that the I/O operation completes before proceeding on
      */
@@ -63,14 +55,10 @@ void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value)
 
 /*****************************************************************************/
 
-void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value)
-{
+void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value) {
     /* write the contents of the I/O location and then synchronize the I/O
      * such that the I/O operation completes before proceeding on
      */
 
     __asm__ volatile("stw %0,0(%1); eieio" ::"r"(Value), "b"(OutAddress));
 }
-
-
-

slsDetectorServers/eigerDetectorServer/HardwareIO.h

@@ -4,8 +4,6 @@
 
 #include "xfs_types.h"
 
-
-
 xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
 xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
 xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
@@ -13,4 +11,3 @@
 void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
 void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
 void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);
-

slsDetectorServers/eigerDetectorServer/HardwareMMappingDefs.h

@@ -5,7 +5,6 @@
 #ifndef __PLB_LL_FIFO_H__
 #define __PLB_LL_FIFO_H__
 
-
 /******************************************************************************/
 /* definitions                                                                */
 /******************************************************************************/
@@ -20,7 +19,6 @@
 #define PLB_LL_FIFO_CTRL_LL_SOF       0x10000000
 #define PLB_LL_FIFO_CTRL_LL_MASK      0xF0000000
 
-
 #define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
 #define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
 
@@ -38,10 +36,8 @@
 // reset Rx and Tx Fifo and set User Reset
 #define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
 
-
 #define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
 
-
 #define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
 #define PLB_LL_FIFO_STATUS_LL_REM       0xC0000000
 #define PLB_LL_FIFO_STATUS_LL_EOF       0x20000000
@@ -56,7 +52,4 @@
 
 #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
 
-
 #endif // __PLB_LL_FIFO_H__
-
-

slsDetectorServers/eigerDetectorServer/LocalLinkInterface.c

@@ -2,28 +2,28 @@
 #include "HardwareMMappingDefs.h"
 #include "clogger.h"
 
-#include <unistd.h>
-#include <sys/mman.h>
 #include <fcntl.h>
+#include <sys/mman.h>
+#include <unistd.h>
 
-
-void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr) {
+void Local_LocalLinkInterface1(struct LocalLinkInterface *ll,
+                               unsigned int ll_fifo_badr) {
     LOG(logDEBUG1, ("Initialize PLB LL FIFOs\n"));
     ll->ll_fifo_base = 0;
     ll->ll_fifo_ctrl_reg = 0;
     if (Local_Init(ll, ll_fifo_badr)) {
         Local_Reset(ll);
-		LOG(logDEBUG1, ("\tFIFO Status : 0x%08x\n\n\n", Local_StatusVector(ll)));
-	} else LOG(logERROR, ("\tCould not map LocalLink : 0x%08x\n\n\n", ll_fifo_badr));
+        LOG(logDEBUG1,
+            ("\tFIFO Status : 0x%08x\n\n\n", Local_StatusVector(ll)));
+    } else
+        LOG(logERROR,
+            ("\tCould not map LocalLink : 0x%08x\n\n\n", ll_fifo_badr));
 }
 
-
 void Local_LocalLinkInterface(struct LocalLinkInterface *ll) {
     LOG(logDEBUG1, ("Initializing new memory\n"));
 }
 
-
-
 int Local_Init(struct LocalLinkInterface *ll, unsigned int ll_fifo_badr) {
     int fd;
     void *plb_ll_fifo_ptr;
@@ -33,7 +33,8 @@ int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr) {
         return 0;
     }
 
-	plb_ll_fifo_ptr =  mmap(0, getpagesize(), PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
+    plb_ll_fifo_ptr = mmap(0, getpagesize(), PROT_READ | PROT_WRITE,
+                           MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
     close(fd);
 
     if (plb_ll_fifo_ptr == MAP_FAILED) {
@@ -47,8 +48,6 @@ int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr) {
     return 1;
 }
 
-
-
 int Local_Reset(struct LocalLinkInterface *ll) {
     return Local_Reset1(ll, PLB_LL_FIFO_CTRL_RESET_STD);
 }
@@ -57,24 +56,28 @@ int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask) {
     ll->ll_fifo_ctrl_reg |= rst_mask;
     LOG(logDEBUG1, ("\tCTRL Register bits: 0x%08x\n", ll->ll_fifo_ctrl_reg));
 
-	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
-	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
-	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
-	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+    HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
+                   ll->ll_fifo_ctrl_reg);
+    HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
+                   ll->ll_fifo_ctrl_reg);
+    HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
+                   ll->ll_fifo_ctrl_reg);
+    HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
+                   ll->ll_fifo_ctrl_reg);
 
     ll->ll_fifo_ctrl_reg &= (~rst_mask);
 
-	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+    HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
+                   ll->ll_fifo_ctrl_reg);
     return 1;
 }
 
-
-
 unsigned int Local_StatusVector(struct LocalLinkInterface *ll) {
     return HWIO_xfs_in32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_STATUS);
 }
 
-int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
+int Local_Write(struct LocalLinkInterface *ll, unsigned int buffer_len,
+                void *buffer) {
     // note: buffer must be word (4 byte) aligned
     // frame_len in byte
     int vacancy = 0;
@@ -85,48 +88,55 @@ int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buf
     unsigned int fifo_ctrl;
     xfs_u32 status;
 
-	if (buffer_len < 1) return -1;
+    if (buffer_len < 1)
+        return -1;
 
     last_word = (buffer_len - 1) / 4;
     word_ptr = (unsigned int *)buffer;
 
-	LOG(logDEBUG1, ("LL Write - Len: %2d - If: %X - Data: ",buffer_len, ll->ll_fifo_base));
+    LOG(logDEBUG1, ("LL Write - Len: %2d - If: %X - Data: ", buffer_len,
+                    ll->ll_fifo_base));
     for (i = 0; i < buffer_len / 4; i++)
         LOG(logDEBUG1, ("%.8X ", *(((unsigned *)buffer) + i)));
 
-	while (words_send <= last_word)
-	{
+    while (words_send <= last_word) {
         while (!vacancy) // wait for Fifo to be empty again
         {
-			status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
-			if ((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0) vacancy = 1;
+            status =
+                HWIO_xfs_in32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_STATUS);
+            if ((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0)
+                vacancy = 1;
             if (vacancy == 0) {
                 LOG(logERROR, ("Fifo full!\n"));
             }
         }
 
         // Just to know: #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS    100
-		for (i=0; ((i<PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) && (words_send <= last_word)); i++)
-		{
+        for (i = 0; ((i < PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) &&
+                     (words_send <= last_word));
+             i++) {
             fifo_ctrl = 0;
-			if (words_send == 0)
-			{
-				fifo_ctrl = PLB_LL_FIFO_CTRL_LL_SOF;//announce the start of file
+            if (words_send == 0) {
+                fifo_ctrl =
+                    PLB_LL_FIFO_CTRL_LL_SOF; // announce the start of file
             }
 
-			if (words_send == last_word)
-			{
-				fifo_ctrl |= (PLB_LL_FIFO_CTRL_LL_EOF | (( (buffer_len-1)<<PLB_LL_FIFO_CTRL_LL_REM_SHIFT) & PLB_LL_FIFO_CTRL_LL_REM)  );
+            if (words_send == last_word) {
+                fifo_ctrl |=
+                    (PLB_LL_FIFO_CTRL_LL_EOF |
+                     (((buffer_len - 1) << PLB_LL_FIFO_CTRL_LL_REM_SHIFT) &
+                      PLB_LL_FIFO_CTRL_LL_REM));
             }
             Local_ctrl_reg_write_mask(ll, PLB_LL_FIFO_CTRL_LL_MASK, fifo_ctrl);
-			HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO,word_ptr[words_send++]);
+            HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_FIFO,
+                           word_ptr[words_send++]);
         }
     }
     return buffer_len;
 }
 
-
-int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
+int Local_Read(struct LocalLinkInterface *ll, unsigned int buffer_len,
+               void *buffer) {
     static unsigned int buffer_ptr = 0;
     // note: buffer must be word (4 byte) aligned
     // frame_len in byte
@@ -139,16 +149,12 @@ int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buff
     LOG(logDEBUG1, ("LL Read - If: %X - Data: ", ll->ll_fifo_base));
 
     word_ptr = (unsigned int *)buffer;
-	do
-	{
+    do {
         status = HWIO_xfs_in32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_STATUS);
 
-		if (!(status & PLB_LL_FIFO_STATUS_EMPTY))
-		{
-			if (status & PLB_LL_FIFO_STATUS_LL_SOF)
-			{
-				if (buffer_ptr)
-				{
+        if (!(status & PLB_LL_FIFO_STATUS_EMPTY)) {
+            if (status & PLB_LL_FIFO_STATUS_LL_SOF) {
+                if (buffer_ptr) {
                     buffer_ptr = 0;
                     return -1; // buffer overflow
                 }
@@ -156,52 +162,49 @@ int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buff
                 sof = 1;
             }
 
-			fifo_val = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO);  //read from fifo
+            fifo_val = HWIO_xfs_in32(
+                ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_FIFO); // read from fifo
 
-			if ((buffer_ptr > 0) || sof)
-			{
-				if ( (buffer_len >> 2) > buffer_ptr)
-				{
+            if ((buffer_ptr > 0) || sof) {
+                if ((buffer_len >> 2) > buffer_ptr) {
                     LOG(logDEBUG1, ("%.8X ", fifo_val));
                     word_ptr[buffer_ptr++] = fifo_val; // write to buffer
-				}
-				else
-				{
+                } else {
                     buffer_ptr = 0;
                     return -2; // buffer overflow
                 }
 
-				if (status & PLB_LL_FIFO_STATUS_LL_EOF)
-				{
-					len = (buffer_ptr << 2) -3 + ( (status & PLB_LL_FIFO_STATUS_LL_REM)>>PLB_LL_FIFO_STATUS_LL_REM_SHIFT );
+                if (status & PLB_LL_FIFO_STATUS_LL_EOF) {
+                    len = (buffer_ptr << 2) - 3 +
+                          ((status & PLB_LL_FIFO_STATUS_LL_REM) >>
+                           PLB_LL_FIFO_STATUS_LL_REM_SHIFT);
                     LOG(logDEBUG1, ("Len: %d\n", len));
                     buffer_ptr = 0;
                     return len;
                 }
-
             }
         }
-	}
-	while(!(status & PLB_LL_FIFO_STATUS_EMPTY));
+    } while (!(status & PLB_LL_FIFO_STATUS_EMPTY));
 
     return 0;
 }
 
-int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val) {
+int Local_ctrl_reg_write_mask(struct LocalLinkInterface *ll, unsigned int mask,
+                              unsigned int val) {
     ll->ll_fifo_ctrl_reg &= (~mask);
     ll->ll_fifo_ctrl_reg |= (mask & val);
-	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+    HWIO_xfs_out32(ll->ll_fifo_base + 4 * PLB_LL_FIFO_REG_CTRL,
+                   ll->ll_fifo_ctrl_reg);
     return 1;
 }
 
-
-int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
+int Local_Test(struct LocalLinkInterface *ll, unsigned int buffer_len,
+               void *buffer) {
 
     int len;
     unsigned int rec_buff_len = 4096;
     unsigned int rec_buffer[4097];
 
-
     Local_Write(ll, buffer_len, buffer);
     usleep(10000);
 
@@ -217,4 +220,3 @@ int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buff
 
     return 1;
 }
-

slsDetectorServers/eigerDetectorServer/LocalLinkInterface.h

@@ -2,7 +2,6 @@
 
 #include "HardwareIO.h"
 
-
 struct LocalLinkInterface {
     xfs_u32 ll_fifo_base;
     unsigned int ll_fifo_ctrl_reg;
@@ -10,12 +9,16 @@ struct LocalLinkInterface{
 
 int Local_Init(struct LocalLinkInterface *ll, unsigned int ll_fifo_badr);
 int Local_Reset1(struct LocalLinkInterface *ll, unsigned int rst_mask);
-int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val);
-void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
+int Local_ctrl_reg_write_mask(struct LocalLinkInterface *ll, unsigned int mask,
+                              unsigned int val);
+void Local_LocalLinkInterface1(struct LocalLinkInterface *ll,
+                               unsigned int ll_fifo_badr);
 unsigned int Local_StatusVector(struct LocalLinkInterface *ll);
 int Local_Reset(struct LocalLinkInterface *ll);
-int  Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
-int  Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
-int  Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
+int Local_Write(struct LocalLinkInterface *ll, unsigned int buffer_len,
+                void *buffer);
+int Local_Read(struct LocalLinkInterface *ll, unsigned int buffer_len,
+               void *buffer);
+int Local_Test(struct LocalLinkInterface *ll, unsigned int buffer_len,
+               void *buffer);
 void Local_LocalLinkInterface(struct LocalLinkInterface *ll);
-

slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h

@@ -10,8 +10,27 @@
 #define STATUS_ERROR   2
 
 /* Enums */
-enum DACINDEX					 			{E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_LR,E_CAL,E_VCMP_RL,E_RXB_RB,E_RXB_LB,E_VCMP_RR,E_VCP,E_VCN,E_VIS,E_VTHRESHOLD};
-#define DEFAULT_DAC_VALS	 	 			{	\
+enum DACINDEX {
+    E_SVP,
+    E_VTR,
+    E_VRF,
+    E_VRS,
+    E_SVN,
+    E_VTGSTV,
+    E_VCMP_LL,
+    E_VCMP_LR,
+    E_CAL,
+    E_VCMP_RL,
+    E_RXB_RB,
+    E_RXB_LB,
+    E_VCMP_RR,
+    E_VCP,
+    E_VCN,
+    E_VIS,
+    E_VTHRESHOLD
+};
+#define DEFAULT_DAC_VALS                                                       \
+    {                                                                          \
         0,    /* SvP		*/                                                       \
         2480, /* Vtr		*/                                                       \
         3300, /* Vrf		*/                                                       \
@@ -29,7 +48,16 @@ enum DACINDEX					 			{E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_L
         2000, /* Vcn		*/                                                       \
         1550  /* Vis		*/                                                       \
     };
-enum ADCINDEX						 		{TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
+enum ADCINDEX {
+    TEMP_FPGAEXT,
+    TEMP_10GE,
+    TEMP_DCDC,
+    TEMP_SODL,
+    TEMP_SODR,
+    TEMP_FPGA,
+    TEMP_FPGAFEBL,
+    TEMP_FPGAFEBR
+};
 enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
 enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
 enum CLKINDEX { RUN_CLK, NUM_CLOCKS };
@@ -40,13 +68,13 @@ enum CLKINDEX                      			{RUN_CLK, NUM_CLOCKS};
 #define NCHIP (4)
 #define NDAC  (16)
 
-
 #define TEN_GIGA_BUFFER_SIZE         (4112)
 #define ONE_GIGA_BUFFER_SIZE         (1040)
 #define TEN_GIGA_CONSTANT            (4)
 #define ONE_GIGA_CONSTANT            (16)
 #define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
-#define NORMAL_HIGHVOLTAGE_OUTPUTPORT 		"/sys/class/hwmon/hwmon5/device/out0_output"
+#define NORMAL_HIGHVOLTAGE_OUTPUTPORT                                          \
+    "/sys/class/hwmon/hwmon5/device/out0_output"
 #define SPECIAL9M_HIGHVOLTAGE_PORT       "/dev/ttyS1"
 #define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
 #define DEFAULT_UDP_SOURCE_PORT          (0xE185)
@@ -86,12 +114,14 @@ enum CLKINDEX                      			{RUN_CLK, NUM_CLOCKS};
 
 #define DAC_MIN_MV (0)
 #define DAC_MAX_MV (2048)
-#define LTC2620_MIN_VAL                     (0)     // including LTC defines instead of LTC262.h (includes bit banging and blackfin read and write)
+#define LTC2620_MIN_VAL                                                        \
+    (0) // including LTC defines instead of LTC262.h (includes bit banging and
+        // blackfin read and write)
 #define LTC2620_MAX_VAL (4095) // 12 bits
 #define DAC_MAX_STEPS   (4096)
 
-#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS	(0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
+#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS                                      \
+    (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
 
 #define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
 #define HIGH_VOLTAGE_TOLERANCE      (5)
-

slsDetectorServers/eigerDetectorServer/xfs_types.h

@@ -14,10 +14,8 @@ typedef signed int xfs_i32;
 typedef signed short xfs_i16;
 typedef signed char xfs_i8;
 
-
 // UDP Header
-struct udp_header_type
-{
+struct udp_header_type {
     // ethternet frame  (14 byte)
     uint8_t dst_mac[6];
     uint8_t src_mac[6];
@@ -41,8 +39,4 @@ struct udp_header_type
     uint8_t dst_port[2];
     uint8_t udp_message_len[2];
     uint8_t udp_checksum[2];
-
 };
-
-
-

slsDetectorServers/eigerDetectorServer/xparameters.h

@@ -1,4 +1,5 @@
-/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx compilation, this file should be replaced with updated values
+/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx
+compilation, this file should be replaced with updated values
 XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
 XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
 XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
@@ -24,27 +25,22 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 
 /******************************************************************/
 
-
 /* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
 #define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
 #define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
 
-
 /* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
 #define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
 #define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
 
-
 /* Definitions for peripheral PLB_BRAM_10G */
 #define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
 #define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
 
-
 /* Definitions for peripheral PLB_BRAM_TEMAC */
 #define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
 #define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
 
-
 /* Definitions for peripheral PLB_GPIO_SYS */
 #define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
 #define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
@@ -52,12 +48,9 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 /** Command Generator */
 #define XPAR_CMD_GENERATOR 0xC5000000
 
-
 /** Version Numbers */
 #define XPAR_VERSION 0xc6000000
 
-
-
 /* Definitions for peripheral PLB_GPIO_TEST */
 #define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
 #define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
@@ -66,9 +59,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define UDP_HEADER_FRAME_NUMBER_LSB_OFST (0x0140)
 #define UDP_HEADER_FRAME_NUMBER_MSB_OFST (0x0160)
 
-
-
-
 /* Definitions for packet, frame and delay down counters */
 #define XPAR_COUNTER_BASEADDR 0xD1020000
 #define XPAR_COUNTER_HIGHADDR 0xD102FFFF
@@ -83,8 +73,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define UDP_HEADER_GET_FNUM_10G_RIGHT_LSB_OFST (0x00C4)
 #define UDP_HEADER_GET_FNUM_10G_RIGHT_MSB_OFST (0x00E4)
 
-
-
 /* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
 #define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
 #define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
@@ -92,46 +80,37 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 /* Definitions for a new memory */
 //#define XPAR_PLB_LL_NEW_MEMORY        0xD1000000//0xD1000084//0xC4200000
 
-
 /* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
 #define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
 #define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
 
-
 /* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
 #define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
 #define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
 
-
 /* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
 #define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
 #define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
 
-
 /* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
 #define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
 #define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
 
-
 /* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
 #define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
 #define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
 #define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR   0xD0000000
 #define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR   0xDFFFFFFF
 
-
 /* Definitions for peripheral PPC_SRAM */
 #define XPAR_PPC_SRAM_BASEADDR 0x00000000
 #define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
 
-
 /******************************************************************/
 
-
 /* Definitions for peripheral PFLASH */
 #define XPAR_PFLASH_NUM_BANKS_MEM 1
 
-
 /******************************************************************/
 
 /* Definitions for peripheral PFLASH */
@@ -155,13 +134,11 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_PLB_SHT1X_IF_CH1_BASEADDR  0xD2200000
 #define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR  0xD220FFFF
 
-
 /* Definitions for peripheral PLB_SHT1X_IF_CH2 */
 #define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
 #define XPAR_PLB_SHT1X_IF_CH2_BASEADDR  0xD2210000
 #define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR  0xD221FFFF
 
-
 /******************************************************************/
 
 /* Definitions for driver UARTLITE */
@@ -176,10 +153,8 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_RS232_ODD_PARITY 0
 #define XPAR_RS232_DATA_BITS  8
 
-
 /******************************************************************/
 
-
 /* Canonical definitions for peripheral RS232 */
 #define XPAR_UARTLITE_0_DEVICE_ID  XPAR_RS232_DEVICE_ID
 #define XPAR_UARTLITE_0_BASEADDR   0xC0000000
@@ -190,7 +165,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_UARTLITE_0_DATA_BITS  8
 #define XPAR_UARTLITE_0_SIO_CHAN   1
 
-
 /******************************************************************/
 
 /* Definitions for driver SPI */
@@ -205,7 +179,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_SPI_FLASH_NUM_SS_BITS       1
 #define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
 
-
 /* Definitions for peripheral XPS_SPI_FEB_CFG */
 #define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID         1
 #define XPAR_XPS_SPI_FEB_CFG_BASEADDR          0xD2010000
@@ -215,10 +188,8 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS       2
 #define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
 
-
 /******************************************************************/
 
-
 /* Canonical definitions for peripheral SPI_FLASH */
 #define XPAR_SPI_0_DEVICE_ID         XPAR_SPI_FLASH_DEVICE_ID
 #define XPAR_SPI_0_BASEADDR          0xD2000000
@@ -228,7 +199,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_SPI_0_NUM_SS_BITS       1
 #define XPAR_SPI_0_NUM_TRANSFER_BITS 8
 
-
 /* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
 #define XPAR_SPI_1_DEVICE_ID         XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
 #define XPAR_SPI_1_BASEADDR          0xD2010000
@@ -238,7 +208,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_SPI_1_NUM_SS_BITS       2
 #define XPAR_SPI_1_NUM_TRANSFER_BITS 8
 
-
 /******************************************************************/
 
 /* Definitions for driver LLTEMAC */
@@ -275,23 +244,18 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_LLTEMAC_0_MCAST_EXTEND 0
 #define XPAR_LLTEMAC_0_INTR         1
 
-
 /* LocalLink TYPE Enumerations */
 #define XPAR_LL_FIFO 1
 #define XPAR_LL_DMA  2
 
-
 /* Canonical LocalLink parameters for TEMAC_INST */
 
-
 /******************************************************************/
 
-
 /* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
 #define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
 #define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
 
-
 /******************************************************************/
 
 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
@@ -306,7 +270,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_XPS_INTC_PPC440_HIGHADDR     0xC100FFFF
 #define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
 
-
 /******************************************************************/
 
 #define XPAR_INTC_SINGLE_BASEADDR                                0xC1000000
@@ -331,10 +294,14 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_INTC_0_HIGHADDR     0xC100FFFF
 #define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
 
-#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
-#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
-#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
+#define XPAR_INTC_0_LLFIFO_0_VEC_ID                                            \
+    XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
+#define XPAR_INTC_0_LLTEMAC_0_VEC_ID                                           \
+    XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
+#define XPAR_INTC_0_TMRCTR_0_VEC_ID                                            \
+    XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
+#define XPAR_INTC_0_SPI_0_VEC_ID                                               \
+    XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
 #define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
 
 /******************************************************************/
@@ -347,7 +314,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR  0xC4000000
 #define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR  0xC400FFFF
 
-
 /******************************************************************/
 
 /* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
@@ -355,7 +321,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_LLFIFO_0_BASEADDR  0xC4000000
 #define XPAR_LLFIFO_0_HIGHADDR  0xC400FFFF
 
-
 /******************************************************************/
 
 /* Definitions for driver SYSMON */
@@ -367,17 +332,14 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR     0xD001FFFF
 #define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
 
-
 /******************************************************************/
 
-
 /* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
 #define XPAR_SYSMON_0_DEVICE_ID    XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
 #define XPAR_SYSMON_0_BASEADDR     0xD0010000
 #define XPAR_SYSMON_0_HIGHADDR     0xD001FFFF
 #define XPAR_SYSMON_0_INCLUDE_INTR 1
 
-
 /******************************************************************/
 
 /* Definitions for driver TMRCTR */
@@ -388,16 +350,13 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_XPS_TIMER_PPC440_BASEADDR  0xC2000000
 #define XPAR_XPS_TIMER_PPC440_HIGHADDR  0xC200FFFF
 
-
 /******************************************************************/
 
-
 /* Canonical definitions for peripheral XPS_TIMER_PPC440 */
 #define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
 #define XPAR_TMRCTR_0_BASEADDR  0xC2000000
 #define XPAR_TMRCTR_0_HIGHADDR  0xC200FFFF
 
-
 /******************************************************************/
 
 /* Definitions for bus frequencies */
@@ -553,4 +512,3 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
 #define XPAR_PPC440_VIRTEX5_HW_VER                      "1.01.a"
 
 /******************************************************************/
-

slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h

@@ -1,9 +1,7 @@
 #pragma once
 
-
 #define REG_OFFSET (4)
 
-
 /* Base addresses 0x1804 0000 ---------------------------------------------*/
 /* Reconfiguration core for readout pll */
 #define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
@@ -39,9 +37,8 @@
 /* UDP datagram generator */
 #define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
 
-
-
-/* Clock Generation registers ------------------------------------------------------*/
+/* Clock Generation registers
+ * ------------------------------------------------------*/
 #define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
 
 #define PLL_RESET_READOUT_OFST (0)
@@ -49,8 +46,6 @@
 #define PLL_RESET_SYSTEM_OFST  (1)
 #define PLL_RESET_SYSTEM_MSK   (0x00000001 << PLL_RESET_SYSTEM_OFST)
 
-
-
 /* Control registers --------------------------------------------------*/
 
 /* Module Control Board Serial Number register */
@@ -73,7 +68,8 @@
 #define API_VERSION_OFST               (0)
 #define API_VERSION_MSK                (0x00FFFFFF << API_VERSION_OFST)
 #define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
-#define API_VERSION_DETECTOR_TYPE_MSK   (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST)  //Not used in software
+#define API_VERSION_DETECTOR_TYPE_MSK                                          \
+    (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
 
 /* Fix pattern register */
 #define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
@@ -105,15 +101,14 @@
 #define CONTROL_CLR_ACQSTN_FIFO_OFST   (15)
 #define CONTROL_CLR_ACQSTN_FIFO_MSK    (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
 #define CONTROL_TIMING_SOURCE_EXT_OFST (17)
-#define CONTROL_TIMING_SOURCE_EXT_MSK   (0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
+#define CONTROL_TIMING_SOURCE_EXT_MSK                                          \
+    (0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
 #define CONTROL_PWR_CHIP_OFST (31)
 #define CONTROL_PWR_CHIP_MSK  (0x00000001 << CONTROL_PWR_CHIP_OFST)
 
 /** DTA Offset Register */
 #define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
 
-
-
 /* ASIC registers --------------------------------------------------*/
 
 /* ASIC Config register */
@@ -121,17 +116,25 @@
 
 #define ASIC_CONFIG_RUN_MODE_OFST (0)
 #define ASIC_CONFIG_RUN_MODE_MSK  (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
-#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL  ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK) 
-#define ASIC_CONFIG_RUN_MODE_CONT_VAL       ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
-#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL  ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
+#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL                                     \
+    ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
+#define ASIC_CONFIG_RUN_MODE_CONT_VAL                                          \
+    ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
+#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL                                     \
+    ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
 #define ASIC_CONFIG_GAIN_OFST (4)
 #define ASIC_CONFIG_GAIN_MSK  (0x00000003 << ASIC_CONFIG_GAIN_OFST)
-#define ASIC_CONFIG_DYNAMIC_GAIN_VAL    ((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK) 
-#define ASIC_CONFIG_FIX_GAIN_1_VAL      ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK) 
-#define ASIC_CONFIG_FIX_GAIN_2_VAL      ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK) 
-#define ASIC_CONFIG_RESERVED_VAL        ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK) 
+#define ASIC_CONFIG_DYNAMIC_GAIN_VAL                                           \
+    ((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
+#define ASIC_CONFIG_FIX_GAIN_1_VAL                                             \
+    ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
+#define ASIC_CONFIG_FIX_GAIN_2_VAL                                             \
+    ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
+#define ASIC_CONFIG_RESERVED_VAL                                               \
+    ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
 #define ASIC_CONFIG_CURRENT_SRC_EN_OFST (7)
-#define ASIC_CONFIG_CURRENT_SRC_EN_MSK  (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
+#define ASIC_CONFIG_CURRENT_SRC_EN_MSK                                         \
+    (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
 #define ASIC_CONFIG_RST_DAC_OFST (15)
 #define ASIC_CONFIG_RST_DAC_MSK  (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
 #define ASIC_CONFIG_DONE_OFST    (31)
@@ -151,8 +154,6 @@
 #define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
 #define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
 
-
-
 /* Packetizer -------------------------------------------------------------*/
 
 /* Packetizer Config Register */
@@ -175,8 +176,8 @@
 #define COORD_RESERVED_OFST (0)
 #define COORD_RESERVED_MSK  (0x0000FFFF << COORD_RESERVED_OFST)
 #define COORD_ID_OFST       (16) // Not connected in firmware TODO
-#define COORD_ID_MSK				    (0x0000FFFF << COORD_ID_OFST)   // Not connected in firmware TODO
-
+#define COORD_ID_MSK                                                           \
+    (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
 
 /* Flow control registers --------------------------------------------------*/
 
@@ -186,13 +187,16 @@
 #define FLOW_STATUS_RUN_BUSY_OFST       (0)
 #define FLOW_STATUS_RUN_BUSY_MSK        (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
 #define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
-#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK	(0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
+#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK                                         \
+    (0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
 #define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
-#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK	(0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
+#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK                                         \
+    (0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
 #define FLOW_STATUS_FIFO_FULL_OFST      (5)
 #define FLOW_STATUS_FIFO_FULL_MSK       (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
 #define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
-#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK	(0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
+#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK                                         \
+    (0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
 #define FLOW_STATUS_CSM_BUSY_OFST (17)
 #define FLOW_STATUS_CSM_BUSY_MSK  (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
 
@@ -216,7 +220,8 @@
 #define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
 #define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
 
-/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
+/* Get Frames from Start 64 bit register (frames from last reset using
+ * CONTROL_CRST) */
 #define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
 #define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)
 

slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h

@@ -44,12 +44,12 @@
 #define DEFAULT_CURRENT_SOURCE      (0)
 #define DEFAULT_TIMING_SOURCE       (TIMING_INTERNAL)
 
-#define DEFAULT_READOUT_C0          (144444448) // rdo_clk, 144 MHz  
-#define DEFAULT_READOUT_C1          (144444448) // rdo_x2_clk, 144 MHz  
-#define DEFAULT_SYSTEM_C0			(144444448) // run_clk, 144 MHz 
-#define DEFAULT_SYSTEM_C1			(72222224) // chip_clk, 72 MHz 
-#define DEFAULT_SYSTEM_C2			(18055556) // sync_clk, 18 MHz 
-#define DEFAULT_SYSTEM_C3			(144444448) // str_clk, 144 MHz
+#define DEFAULT_READOUT_C0 (8)  //(108333336) // rdo_clk, 108 MHz
+#define DEFAULT_READOUT_C1 (8)  //(108333336) // rdo_x2_clk, 108 MHz
+#define DEFAULT_SYSTEM_C0  (5)  //(144444448) // run_clk, 144 MHz
+#define DEFAULT_SYSTEM_C1  (10) //(72222224) // chip_clk, 72 MHz
+#define DEFAULT_SYSTEM_C2  (5)  //(144444448) // sync_clk, 144 MHz
+#define DEFAULT_SYSTEM_C3  (5)  //(144444448) // str_clk, 144 MHz
 
 /* Firmware Definitions */
 #define IP_HEADER_SIZE          (20)
@@ -62,42 +62,58 @@
 #define BIT16_MASK (0xFFFF)
 
 /* Enums */
-enum DACINDEX				        {G2_VREF_H_ADC, /* 0 */		\
-									G2_DAC_UNUSED,  /* 1 */		\
-									G2_VB_COMP_FE,  /* 2 */		\
-        							G2_VB_COMP_ADC, /* 3 */		\
-        							G2_VCOM_CDS,    /* 4 */		\
-        							G2_VREF_RSTORE,/* 5 */		\
-        							G2_VB_OPA_1ST,  /* 6 */		\
-        							G2_VREF_COMP_FE,/* 7 */		\
-        							G2_VCOM_ADC1,   /* 8 */		\
-        							G2_VREF_PRECH,  /* 9 */		\
-        							G2_VREF_L_ADC,  /* 10 */ 	\
-        							G2_VREF_CDS,    /* 11 */	\
-        							G2_VB_CS,       /* 12 */	\
-        							G2_VB_OPA_FD,   /* 13 */	\
-		  							G2_DAC_UNUSED2, /* 14 */	\
-        							G2_VCOM_ADC2    /* 15*/		\
+enum DACINDEX {
+    G2_VREF_H_ADC,   /* 0 */
+    G2_DAC_UNUSED,   /* 1 */
+    G2_VB_COMP_FE,   /* 2 */
+    G2_VB_COMP_ADC,  /* 3 */
+    G2_VCOM_CDS,     /* 4 */
+    G2_VREF_RSTORE,  /* 5 */
+    G2_VB_OPA_1ST,   /* 6 */
+    G2_VREF_COMP_FE, /* 7 */
+    G2_VCOM_ADC1,    /* 8 */
+    G2_VREF_PRECH,   /* 9 */
+    G2_VREF_L_ADC,   /* 10 */
+    G2_VREF_CDS,     /* 11 */
+    G2_VB_CS,        /* 12 */
+    G2_VB_OPA_FD,    /* 13 */
+    G2_DAC_UNUSED2,  /* 14 */
+    G2_VCOM_ADC2     /* 15*/
 };
-#define  DAC_NAMES					"vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", "vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", "vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", "dac_unused2", "vcom_adc2"
+#define DAC_NAMES                                                              \
+    "vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds",       \
+        "vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1",              \
+        "vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd",          \
+        "dac_unused2", "vcom_adc2"
 
-enum ONCHIP_DACINDEX				{G2_VCHIP_COMP_FE, 		/* 0 */		\
-									G2_VCHIP_OPA_1ST,  		/* 1 */		\
-									G2_VCHIP_OPA_FD,  		/* 2 */		\
-        							G2_VCHIP_COMP_ADC, 		/* 3 */		\
-									G2_VCHIP_UNUSED, 		/* 4 */		\
-        							G2_VCHIP_REF_COMP_FE,	/* 5 */		\
-        							G2_VCHIP_CS				/* 6 */		\
+enum ONCHIP_DACINDEX {
+    G2_VCHIP_COMP_FE,     /* 0 */
+    G2_VCHIP_OPA_1ST,     /* 1 */
+    G2_VCHIP_OPA_FD,      /* 2 */
+    G2_VCHIP_COMP_ADC,    /* 3 */
+    G2_VCHIP_UNUSED,      /* 4 */
+    G2_VCHIP_REF_COMP_FE, /* 5 */
+    G2_VCHIP_CS           /* 6 */
 };
-#define  ONCHIP_DAC_NAMES			"vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", "vchip_unused", "vchip_ref_comp_fe", "vchip_cs"	
+#define ONCHIP_DAC_NAMES                                                       \
+    "vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc",        \
+        "vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
 
-
-enum CLKINDEX                       {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
-#define CLK_NAMES					"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
+enum CLKINDEX {
+    READOUT_C0,
+    READOUT_C1,
+    SYSTEM_C0,
+    SYSTEM_C1,
+    SYSTEM_C2,
+    SYSTEM_C3,
+    NUM_CLOCKS
+};
+#define CLK_NAMES                                                              \
+    "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2",         \
+        "SYSTEM_C3"
 
 enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
 
-
 /** Chip Definitions */
 #define ASIC_ADDR_MAX_BITS       (4)
 #define ASIC_CURRENT_INJECT_ADDR (0x9)

slsDetectorServers/gotthardDetectorServer/RegisterDefs.h

@@ -8,11 +8,16 @@
 
 #define GAIN_CONFGAIN_OFST (0)
 #define GAIN_CONFGAIN_MSK  (0x000000FF << GAIN_CONFGAIN_OFST)
-#define GAIN_CONFGAIN_HGH_GAIN_VAL      ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
-#define GAIN_CONFGAIN_DYNMC_GAIN_VAL    ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
-#define GAIN_CONFGAIN_LW_GAIN_VAL       ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
-#define GAIN_CONFGAIN_MDM_GAIN_VAL      ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
-#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL  ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_HGH_GAIN_VAL                                             \
+    ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_DYNMC_GAIN_VAL                                           \
+    ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_LW_GAIN_VAL                                              \
+    ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_MDM_GAIN_VAL                                             \
+    ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL                                         \
+    ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
 
 /** Flow Control register */
 //#define FLOW_CONTROL_REG                (0x11 << MEM_MAP_SHIFT)
@@ -60,12 +65,16 @@
 
 #define DAQ_TKN_TMNG_OFST (0)
 #define DAQ_TKN_TMNG_MSK  (0x0000FFFF << DAQ_TKN_TMNG_OFST)
-#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL     ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
-#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL     ((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
+#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL                                            \
+    ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
+#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL                                            \
+    ((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
 #define DAQ_PCKT_LNGTH_OFST (16)
 #define DAQ_PCKT_LNGTH_MSK  (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
-#define DAQ_PCKT_LNGTH_NO_ROI_VAL       ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
-#define DAQ_PCKT_LNGTH_ROI_VAL          ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
+#define DAQ_PCKT_LNGTH_NO_ROI_VAL                                              \
+    ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
+#define DAQ_PCKT_LNGTH_ROI_VAL                                                 \
+    ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
 
 /** Time From Start register */
 //#define TIME_FROM_START_REG             (0x16 << MEM_MAP_SHIFT)
@@ -95,27 +104,37 @@
 
 #define ADC_SYNC_ENET_STRT_DLY_OFST (0)
 #define ADC_SYNC_ENET_STRT_DLY_MSK  (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
-#define ADC_SYNC_ENET_STRT_DLY_VAL      ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
+#define ADC_SYNC_ENET_STRT_DLY_VAL                                             \
+    ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
 #define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
 #define ADC_SYNC_TKN1_HGH_DLY_MSK  (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
-#define ADC_SYNC_TKN1_HGH_DLY_VAL       ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
+#define ADC_SYNC_TKN1_HGH_DLY_VAL                                              \
+    ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
 #define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
 #define ADC_SYNC_TKN2_HGH_DLY_MSK  (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
-#define ADC_SYNC_TKN2_HGH_DLY_VAL       ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
+#define ADC_SYNC_TKN2_HGH_DLY_VAL                                              \
+    ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
 #define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
 #define ADC_SYNC_TKN1_LOW_DLY_MSK  (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
-#define ADC_SYNC_TKN1_LOW_DLY_VAL       ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
+#define ADC_SYNC_TKN1_LOW_DLY_VAL                                              \
+    ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
 #define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
 #define ADC_SYNC_TKN2_LOW_DLY_MSK  (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
-#define ADC_SYNC_TKN2_LOW_DLY_VAL       ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
+#define ADC_SYNC_TKN2_LOW_DLY_VAL                                              \
+    ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
 // 0x32214
-#define ADC_SYNC_TKN_VAL                (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL |  ADC_SYNC_TKN2_LOW_DLY_VAL)
+#define ADC_SYNC_TKN_VAL                                                       \
+    (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL |                  \
+     ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL |                   \
+     ADC_SYNC_TKN2_LOW_DLY_VAL)
 #define ADC_SYNC_CLEAN_FIFOS_OFST (20)
 #define ADC_SYNC_CLEAN_FIFOS_MSK  (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
 #define ADC_SYNC_ENET_DELAY_OFST  (24)
 #define ADC_SYNC_ENET_DELAY_MSK   (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
-#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL  ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
-#define ADC_SYNC_ENET_DELAY_ROI_VAL     ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
+#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL                                         \
+    ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
+#define ADC_SYNC_ENET_DELAY_ROI_VAL                                            \
+    ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
 
 /** Time From Start register */
 //#define MU_TIME_REG                     (0x1a << MEM_MAP_SHIFT)
@@ -131,7 +150,9 @@
 #define TEMP_SPI_IN_T2_CLK_MSK  (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
 #define TEMP_SPI_IN_T2_CS_OFST  (3)
 #define TEMP_SPI_IN_T2_CS_MSK   (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
-#define TEMP_SPI_IN_IDLE_MSK            (TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T2_CLK_MSK)
+#define TEMP_SPI_IN_IDLE_MSK                                                   \
+    (TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK |  \
+     TEMP_SPI_IN_T2_CLK_MSK)
 
 /** Temperatre SPI Out register */
 #define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
@@ -171,7 +192,8 @@
 #define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
 
 #define FPGA_VERSION_OFST (0)
-#define FPGA_VERSION_MSK                (0x00FFFFFF << FPGA_VERSION_OFST)       // to get in format yymmdd
+#define FPGA_VERSION_MSK                                                       \
+    (0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
 
 /* Fix Pattern register */
 #define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
@@ -260,7 +282,8 @@
 #define EXT_SIGNAL_MSK               (0x00000007 << EXT_SIGNAL_OFST)
 #define EXT_SIGNAL_OFF_VAL           ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
 #define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
-#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL   ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL                                          \
+    ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
 
 /** Look at me register */
 //#define LOOK_AT_ME_REG                  (0x28 << MEM_MAP_SHIFT)
@@ -274,7 +297,8 @@
 #define CHIP_OF_INTRST_ADC_SEL_OFST    (0)
 #define CHIP_OF_INTRST_ADC_SEL_MSK     (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
 #define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
-#define CHIP_OF_INTRST_NUM_CHNNLS_MSK   (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
+#define CHIP_OF_INTRST_NUM_CHNNLS_MSK                                          \
+    (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
 
 /** Out MUX register */
 //#define OUT_MUX_REG                     (0x2b << MEM_MAP_SHIFT)
@@ -366,4 +390,3 @@
 
 /* Counter Block Memory starting address */
 #define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)
-

slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c

@@ -1,7 +1,7 @@
 #include "slsDetectorFunctionList.h"
-#include "versionAPI.h"
-#include "clogger.h"
 #include "RegisterDefs.h"
+#include "clogger.h"
+#include "versionAPI.h"
 
 #include "LTC2620.h" // dacs
 #ifdef VIRTUAL
@@ -10,8 +10,8 @@
 #endif
 
 #include "string.h"
-#include <unistd.h>     // usleep
 #include <netinet/in.h>
+#include <unistd.h> // usleep
 #ifdef VIRTUAL
 #include <pthread.h>
 #include <time.h>
@@ -61,9 +61,7 @@ int slaveadcphase = 0;
 int rsttosw1delay = 2;
 int startacqdelay = 1;
 
-int isInitCheckDone() {
-	return initCheckDone;
-}
+int isInitCheckDone() { return initCheckDone; }
 
 int getInitResult(char **mess) {
     *mess = initErrorMessage;
@@ -93,9 +91,10 @@ void basictests() {
     }
 
     // does check only if flag is 0 (by default), set by command line
-	if (((checkType() == FAIL) || (testFpga() == FAIL) || (testBus() == FAIL))) {
-		strcpy(initErrorMessage,
-				"Could not pass basic tests of FPGA and bus. Dangerous to continue.\n");
+    if (((checkType() == FAIL) || (testFpga() == FAIL) ||
+         (testBus() == FAIL))) {
+        strcpy(initErrorMessage, "Could not pass basic tests of FPGA and bus. "
+                                 "Dangerous to continue.\n");
         LOG(logERROR, ("%s\n\n", initErrorMessage));
         initError = FAIL;
         return;
@@ -108,7 +107,8 @@ void basictests() {
     int64_t swversion = getServerVersion();
     int64_t client_sw_apiversion = getClientServerAPIVersion();
 
-	LOG(logINFOBLUE, ("************ Gotthard Server *********************\n"
+    LOG(logINFOBLUE,
+        ("************ Gotthard Server *********************\n"
          "Board Revision         : 0x%x\n"
 
          "Detector IP Addr       : 0x%x\n"
@@ -120,13 +120,10 @@ void basictests() {
          "********************************************************\n",
          boardrev,
 
-			ipadd,
-			(long  long unsigned int)macadd,
+         ipadd, (long long unsigned int)macadd,
 
-			(long  long int)fwversion,
-			(long  long int)swversion,
-			(long long int)client_sw_apiversion
-	));
+         (long long int)fwversion, (long long int)swversion,
+         (long long int)client_sw_apiversion));
 
     LOG(logINFO, ("Basic Tests - success\n"));
 #endif
@@ -136,9 +133,11 @@ int checkType() {
 #ifdef VIRTUAL
     return OK;
 #endif
-	u_int32_t type = ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
+    u_int32_t type =
+        ((bus_r(BOARD_REVISION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
     if (type == DETECTOR_TYPE_MOENCH_VAL) {
-			LOG(logERROR, ("This is not a Gotthard firmware (read %d, expected ?)\n", type));
+        LOG(logERROR,
+            ("This is not a Gotthard firmware (read %d, expected ?)\n", type));
         return FAIL;
     }
     return OK;
@@ -156,7 +155,9 @@ int testFpga() {
     if (val == FIX_PATT_VAL) {
         LOG(logINFO, ("Fixed pattern: successful match (0x%08x)\n", val));
     } else {
-		LOG(logERROR, ("Fixed pattern does not match! Read 0x%08x, expected 0x%08x\n", val, FIX_PATT_VAL));
+        LOG(logERROR,
+            ("Fixed pattern does not match! Read 0x%08x, expected 0x%08x\n",
+             val, FIX_PATT_VAL));
         ret = FAIL;
     }
 
@@ -207,7 +208,8 @@ int testFpga() {
         }
         bus_w(addr, 0);
         if (ret == OK) {
-	        LOG(logINFO, ("Successfully tested FPGA Dummy Register %d times\n", times));
+            LOG(logINFO,
+                ("Successfully tested FPGA Dummy Register %d times\n", times));
         }
     }
 
@@ -231,8 +233,8 @@ int testBus() {
         bus_w(addr, val);
         readval = bus_r(addr);
         if (readval != val) {
-			LOG(logERROR, ("Mismatch! Loop(%d): Wrote 0x%x, read 0x%x\n",
-					i, val, readval));
+            LOG(logERROR, ("Mismatch! Loop(%d): Wrote 0x%x, read 0x%x\n", i,
+                           val, readval));
             ret = FAIL;
         }
     }
@@ -245,7 +247,6 @@ int testBus() {
     return ret;
 }
 
-
 void setTestImageMode(int ival) {
     uint32_t addr = MULTI_PURPOSE_REG;
     if (ival >= 0) {
@@ -265,13 +266,9 @@ int getTestImageMode() {
 
 /* Ids */
 
-uint64_t getServerVersion() {
-    return APIGOTTHARD;
-}
+uint64_t getServerVersion() { return APIGOTTHARD; }
 
-uint64_t getClientServerAPIVersion() {
-    return APIGOTTHARD;
-}
+uint64_t getClientServerAPIVersion() { return APIGOTTHARD; }
 
 u_int64_t getFirmwareVersion() {
 #ifdef VIRTUAL
@@ -293,7 +290,8 @@ u_int64_t  getDetectorMAC() {
 #else
     char output[255], mac[255] = "";
     u_int64_t res = 0;
-	FILE* sysFile = popen("ifconfig eth0 | grep HWaddr | cut -d \" \" -f 11", "r");
+    FILE *sysFile =
+        popen("ifconfig eth0 | grep HWaddr | cut -d \" \" -f 11", "r");
     fgets(output, sizeof(output), sysFile);
     pclose(sysFile);
     // getting rid of ":"
@@ -316,7 +314,9 @@ u_int32_t  getDetectorIP(){
     u_int32_t res = 0;
     // execute and get address
     char output[255];
-	FILE* sysFile = popen("ifconfig  | grep 'inet addr:'| grep -v '127.0.0.1' | cut -d: -f2", "r");
+    FILE *sysFile = popen(
+        "ifconfig  | grep 'inet addr:'| grep -v '127.0.0.1' | cut -d: -f2",
+        "r");
     fgets(output, sizeof(output), sysFile);
     pclose(sysFile);
 
@@ -338,10 +338,10 @@ u_int32_t getBoardRevision() {
 #ifdef VIRTUAL
     return 0;
 #endif
-    return ((bus_r(BOARD_REVISION_REG) & BOARD_REVISION_MSK) >> BOARD_REVISION_OFST);
+    return ((bus_r(BOARD_REVISION_REG) & BOARD_REVISION_MSK) >>
+            BOARD_REVISION_OFST);
 }
 
-
 /* initialization */
 
 void initControlServer() {
@@ -353,7 +353,8 @@ void initControlServer(){
 
 void initStopServer() {
     if (mapCSP0() == FAIL) {
-		LOG(logERROR, ("Stop Server: Map Fail. Dangerous to continue. Goodbye!\n"));
+        LOG(logERROR,
+            ("Stop Server: Map Fail. Dangerous to continue. Goodbye!\n"));
         exit(EXIT_FAILURE);
     }
 #ifdef VIRTUAL
@@ -364,7 +365,6 @@ void initStopServer() {
 #endif
 }
 
-
 /* set up detector */
 
 void setupDetector() {
@@ -385,17 +385,24 @@ void setupDetector() {
 
     // adc
     if (getBoardRevision() == 1) {
-        AD9252_SetDefines(ADC_SPI_REG, ADC_SPI_SRL_CS_OTPT_MSK, ADC_SPI_SRL_CLK_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_OFST);
+        AD9252_SetDefines(ADC_SPI_REG, ADC_SPI_SRL_CS_OTPT_MSK,
+                          ADC_SPI_SRL_CLK_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_MSK,
+                          ADC_SPI_SRL_DT_OTPT_OFST);
         AD9252_Disable();
         AD9252_Configure();
     } else {
-        AD9257_SetDefines(ADC_SPI_REG, ADC_SPI_SRL_CS_OTPT_MSK, ADC_SPI_SRL_CLK_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_OFST);
+        AD9257_SetDefines(ADC_SPI_REG, ADC_SPI_SRL_CS_OTPT_MSK,
+                          ADC_SPI_SRL_CLK_OTPT_MSK, ADC_SPI_SRL_DT_OTPT_MSK,
+                          ADC_SPI_SRL_DT_OTPT_OFST);
         AD9257_Disable();
         AD9257_Configure();
     }
 
     // dac
-    LTC2620_SetDefines(SPI_REG, SPI_DAC_SRL_CS_OTPT_MSK, SPI_DAC_SRL_CLK_OTPT_MSK, SPI_DAC_SRL_DGTL_OTPT_MSK, SPI_DAC_SRL_DGTL_OTPT_OFST, NDAC, DAC_MIN_MV, DAC_MAX_MV);
+    LTC2620_SetDefines(SPI_REG, SPI_DAC_SRL_CS_OTPT_MSK,
+                       SPI_DAC_SRL_CLK_OTPT_MSK, SPI_DAC_SRL_DGTL_OTPT_MSK,
+                       SPI_DAC_SRL_DGTL_OTPT_OFST, NDAC, DAC_MIN_MV,
+                       DAC_MAX_MV);
     LTC2620_Disable();
     LTC2620_Configure();
     setDefaultDacs();
@@ -424,7 +431,6 @@ void setupDetector() {
     setExpTime(DEFAULT_EXPTIME);
     setPeriod(DEFAULT_PERIOD);
     setDelayAfterTrigger(DEFAULT_DELAY);
-
 }
 
 int setDefaultDacs() {
@@ -449,7 +455,6 @@ uint32_t writeRegister16And32(uint32_t offset, uint32_t data) {
         return writeRegister16(offset, data);
     } else
         return writeRegister(offset, data);
-
 }
 
 uint32_t readRegister16And32(uint32_t offset) {
@@ -470,11 +475,14 @@ void setPhaseShiftOnce() {
     // first time detector has switched on
     if (!val) {
         detectorFirstServer = 1;
-        LOG(logINFO, ("Implementing the first phase shift of %d\n", phaseShift));
+        LOG(logINFO,
+            ("Implementing the first phase shift of %d\n", phaseShift));
         int times = 0;
         for (times = 1; times < phaseShift; ++times) {
-            bus_w(addr,(INT_RSTN_MSK | ENT_RSTN_MSK | SW1_MSK | PHS_STP_MSK));      //0x1821
-            bus_w(addr,(INT_RSTN_MSK | ENT_RSTN_MSK | (SW1_MSK &~ PHS_STP_MSK)));   //0x1820
+            bus_w(addr, (INT_RSTN_MSK | ENT_RSTN_MSK | SW1_MSK |
+                         PHS_STP_MSK)); // 0x1821
+            bus_w(addr, (INT_RSTN_MSK | ENT_RSTN_MSK |
+                         (SW1_MSK & ~PHS_STP_MSK))); // 0x1820
         }
         LOG(logDEBUG1, ("Multipurpose reg: 0x%x\n", val));
     } else
@@ -506,8 +514,9 @@ void setADCSyncRegister() {
     u_int32_t addr = ADC_SYNC_REG;
 
     // 0x88(no roi), 0x1b(roi) (MSB)
-    u_int32_t tokenDelay =  ((adcConfigured == -1) ?
-            ADC_SYNC_ENET_DELAY_NO_ROI_VAL : ADC_SYNC_ENET_DELAY_ROI_VAL);
+    u_int32_t tokenDelay =
+        ((adcConfigured == -1) ? ADC_SYNC_ENET_DELAY_NO_ROI_VAL
+                               : ADC_SYNC_ENET_DELAY_ROI_VAL);
 
     // 0x88032214(no roi), 0x1b032214(with roi)
     u_int32_t val = (ADC_SYNC_TKN_VAL | tokenDelay);
@@ -521,12 +530,13 @@ void setDAQRegister() {
     u_int32_t addr = DAQ_REG;
 
     // 0x1f16(board rev 1) 0x1f0f(board rev 2)
-    u_int32_t tokenTiming = ((getBoardRevision() == 1) ?
-            DAQ_TKN_TMNG_BRD_RVSN_1_VAL : DAQ_TKN_TMNG_BRD_RVSN_2_VAL);
+    u_int32_t tokenTiming =
+        ((getBoardRevision() == 1) ? DAQ_TKN_TMNG_BRD_RVSN_1_VAL
+                                   : DAQ_TKN_TMNG_BRD_RVSN_2_VAL);
 
     // 0x13f(no roi), 0x7f(roi)
-    u_int32_t packetLength = ((adcConfigured == -1) ?
-            DAQ_PCKT_LNGTH_NO_ROI_VAL : DAQ_PCKT_LNGTH_ROI_VAL);
+    u_int32_t packetLength = ((adcConfigured == -1) ? DAQ_PCKT_LNGTH_NO_ROI_VAL
+                                                    : DAQ_PCKT_LNGTH_ROI_VAL);
 
     // MSB: packetLength LSB: tokenTiming
     u_int32_t val = (tokenTiming | packetLength);
@@ -540,13 +550,16 @@ void setChipOfInterestRegister(int adc) {
     u_int32_t addr = CHIP_OF_INTRST_REG;
 
     // 0x1f(no roi), 0xXX(roi)
-    u_int32_t adcSelect = ((adcConfigured == -1) ?
-            CHIP_OF_INTRST_ADC_SEL_MSK :
-            (((1 << adc) << CHIP_OF_INTRST_ADC_SEL_OFST) & CHIP_OF_INTRST_ADC_SEL_MSK));
+    u_int32_t adcSelect =
+        ((adcConfigured == -1) ? CHIP_OF_INTRST_ADC_SEL_MSK
+                               : (((1 << adc) << CHIP_OF_INTRST_ADC_SEL_OFST) &
+                                  CHIP_OF_INTRST_ADC_SEL_MSK));
 
     // 0x0500(no roi), 0x0100(roi)
-    u_int32_t numChannels = (adcConfigured == -1) ? (NCHIP * NCHAN) : (NCHIPS_PER_ADC * NCHAN);
-    numChannels = ((numChannels << CHIP_OF_INTRST_NUM_CHNNLS_OFST) & CHIP_OF_INTRST_NUM_CHNNLS_MSK);
+    u_int32_t numChannels =
+        (adcConfigured == -1) ? (NCHIP * NCHAN) : (NCHIPS_PER_ADC * NCHAN);
+    numChannels = ((numChannels << CHIP_OF_INTRST_NUM_CHNNLS_OFST) &
+                   CHIP_OF_INTRST_NUM_CHNNLS_MSK);
 
     // 0x500001f(no roi), 0x10000xx(roi) MSB:num channels, LSB: selected ADC
     u_int32_t val = (numChannels | adcSelect);
@@ -564,8 +577,10 @@ void setROIADC(int adc) {
     cleanFifos();                   // clean fifos
     setChipOfInterestRegister(adc); // num channels & select adc
 
-    ipPacketSize = ((adcConfigured == -1) ? IP_PACKET_SIZE_NO_ROI : IP_PACKET_SIZE_ROI);
-    udpPacketSize = ((adcConfigured == -1) ? UDP_PACKETSIZE_NO_ROI : UDP_PACKETSIZE_ROI);
+    ipPacketSize =
+        ((adcConfigured == -1) ? IP_PACKET_SIZE_NO_ROI : IP_PACKET_SIZE_ROI);
+    udpPacketSize =
+        ((adcConfigured == -1) ? UDP_PACKETSIZE_NO_ROI : UDP_PACKETSIZE_ROI);
 }
 
 void setGbitReadout() {
@@ -615,14 +630,17 @@ int readConfigFile() {
                 masterflags = NO_MASTER;
                 LOG(logINFOBLUE, ("\tNo Master\n"));
             } else {
-                LOG(logERROR, ("\tCould not scan masterflags %s value from config file\n", value));
+                LOG(logERROR,
+                    ("\tCould not scan masterflags %s value from config file\n",
+                     value));
                 scan = FAIL;
                 break;
             }
 
             // not first server since detector power on
             if (!detectorFirstServer) {
-                LOG(logINFOBLUE, ("\tServer has been started up before. Ignoring rest of config file\n"));
+                LOG(logINFOBLUE, ("\tServer has been started up before. "
+                                  "Ignoring rest of config file\n"));
                 fclose(fd);
                 return FAIL;
             }
@@ -633,7 +651,9 @@ int readConfigFile() {
             // convert value to int
             int ival = 0;
             if (sscanf(value, "%d", &ival) <= 0) {
-                LOG(logERROR, ("\tCould not scan parameter %s value %s from config file\n", key, value));
+                LOG(logERROR, ("\tCould not scan parameter %s value %s from "
+                               "config file\n",
+                               key, value));
                 scan = FAIL;
                 break;
             }
@@ -653,7 +673,8 @@ int readConfigFile() {
             else if (!strcasecmp(key, "startacqdelay"))
                 startacqdelay = ival;
             else {
-                LOG(logERROR, ("\tCould not scan parameter %s from config file\n", key));
+                LOG(logERROR,
+                    ("\tCould not scan parameter %s from config file\n", key));
                 scan = FAIL;
                 break;
             }
@@ -663,21 +684,16 @@ int readConfigFile() {
     if (scan == FAIL)
         exit(EXIT_FAILURE);
 
-    LOG(logINFOBLUE, (
-            "\tmasterdefaultdelay:%d\n"
+    LOG(logINFOBLUE,
+        ("\tmasterdefaultdelay:%d\n"
          "\tpatternphase:%d\n"
          "\tadcphase:%d\n"
          "\tslavepatternphase:%d\n"
          "\tslaveadcphase:%d\n"
          "\trsttosw1delay:%d\n"
          "\tstartacqdelay:%d\n",
-            masterdefaultdelay,
-            patternphase,
-            adcphase,
-            slavepatternphase,
-            slaveadcphase,
-            rsttosw1delay,
-            startacqdelay));
+         masterdefaultdelay, patternphase, adcphase, slavepatternphase,
+         slaveadcphase, rsttosw1delay, startacqdelay));
     return OK;
 }
 
@@ -694,7 +710,8 @@ void setMasterSlaveConfiguration() {
         setDelayAfterTrigger(0);
 
         // Set pattern phase for the master module
-        u_int32_t val = (bus_r(MULTI_PURPOSE_REG) & (~(PLL_CLK_SL_MSK))); // unset mask
+        u_int32_t val =
+            (bus_r(MULTI_PURPOSE_REG) & (~(PLL_CLK_SL_MSK))); // unset mask
         bus_w(MULTI_PURPOSE_REG, val | PLL_CLK_SL_MSTR_VAL);
         setPhaseShift(patternphase);
 
@@ -715,26 +732,26 @@ void setMasterSlaveConfiguration() {
 
         // Set start acq delay
         val = (bus_r(MULTI_PURPOSE_REG) & (~(STRT_ACQ_DLY_MSK))); // unset mask
-        val = val | ((startacqdelay << STRT_ACQ_DLY_OFST) & STRT_ACQ_DLY_MSK); // set val
+        val = val | ((startacqdelay << STRT_ACQ_DLY_OFST) &
+                     STRT_ACQ_DLY_MSK); // set val
         bus_w(MULTI_PURPOSE_REG, val);
         LOG(logDEBUG1, ("\tMultipurpose reg: 0x%x\n", val));
     }
 
     // all configuration - Set RST to SW1 delay
-    u_int32_t val = (bus_r(MULTI_PURPOSE_REG) & (~(RST_TO_SW1_DLY_MSK))); // unset mask
-    val = val | ((rsttosw1delay << RST_TO_SW1_DLY_OFST) & RST_TO_SW1_DLY_MSK); // set val
+    u_int32_t val =
+        (bus_r(MULTI_PURPOSE_REG) & (~(RST_TO_SW1_DLY_MSK))); // unset mask
+    val = val | ((rsttosw1delay << RST_TO_SW1_DLY_OFST) &
+                 RST_TO_SW1_DLY_MSK); // set val
     bus_w(MULTI_PURPOSE_REG, val);
     LOG(logDEBUG1, ("\tMultipurpose reg: 0x%x\n", val));
 
     LOG(logINFO, ("\tMaster Slave Configuration has been set up\n"));
 }
 
-
 /* set parameters -  dr, roi */
 
-int setDynamicRange(int dr){
-	return DYNAMIC_RANGE;
-}
+int setDynamicRange(int dr) { return DYNAMIC_RANGE; }
 
 int setROI(ROI arg) {
 
@@ -747,7 +764,8 @@ int setROI(ROI arg) {
         LOG(logINFO, ("Setting ROI:(%d, %d)\n", arg.xmin, arg.xmax));
         // validation
         // xmin divisible by 256 and less than 1280
-        if (((arg.xmin % NCHAN_PER_ADC) != 0) || (arg.xmin >= (NCHAN * NCHIP))) {
+        if (((arg.xmin % NCHAN_PER_ADC) != 0) ||
+            (arg.xmin >= (NCHAN * NCHIP))) {
             LOG(logERROR, ("Could not set roi. xmin is invalid\n"));
             return FAIL;
         }
@@ -761,8 +779,8 @@ int setROI(ROI arg) {
         adc = arg.xmin / NCHAN_PER_ADC;
     }
     LOG(logINFO, ("\tAdc to be configured: %d\n", adc));
-    LOG(logINFO, ("\tROI to be configured: (%d, %d)\n",
-            (adc == -1) ? 0 :  (rois.xmin),
+    LOG(logINFO,
+        ("\tROI to be configured: (%d, %d)\n", (adc == -1) ? 0 : (rois.xmin),
          (adc == -1) ? (NCHIP * NCHAN - 1) : (rois.xmax)));
 
     // set adc of interest
@@ -782,7 +800,6 @@ ROI getROI() {
     return rois;
 }
 
-
 /* parameters - timer */
 void setNumFrames(int64_t val) {
     if (val > 0) {
@@ -825,7 +842,8 @@ int setExpTime(int64_t val) {
 }
 
 int64_t getExpTime() {
-    return get64BitReg(SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) / (1E-9 * CLK_FREQ);
+    return get64BitReg(SET_EXPTIME_LSB_REG, SET_EXPTIME_MSB_REG) /
+           (1E-9 * CLK_FREQ);
 }
 
 int setPeriod(int64_t val) {
@@ -847,12 +865,14 @@ int setPeriod(int64_t val) {
 }
 
 int64_t getPeriod() {
-    return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG)/ (1E-9 * CLK_FREQ);
+    return get64BitReg(SET_PERIOD_LSB_REG, SET_PERIOD_MSB_REG) /
+           (1E-9 * CLK_FREQ);
 }
 
 int setDelayAfterTrigger(int64_t val) {
     if (val < 0) {
-        LOG(logERROR, ("Invalid delay after trigger: %lld ns\n", (long long int)val));
+        LOG(logERROR,
+            ("Invalid delay after trigger: %lld ns\n", (long long int)val));
         return FAIL;
     }
     LOG(logINFO, ("Setting delay after trigger %lld ns\n", (long long int)val));
@@ -860,7 +880,10 @@ int setDelayAfterTrigger(int64_t val) {
         val += masterdefaultdelay;
         LOG(logINFO, ("\tActual Delay (master): %lld\n", (long long int)val));
     }
-    val = (val * 1E-9 * CLK_FREQ) + 0.5; //because of the master delay of 62 ns (not really double of clkfreq), losing precision and 0 delay becomes -31ns, so adding +0.5. Also adding +0.5 for more tolerance for gotthard1.
+    val = (val * 1E-9 * CLK_FREQ) +
+          0.5; // because of the master delay of 62 ns (not really double of
+               // clkfreq), losing precision and 0 delay becomes -31ns, so adding
+               // +0.5. Also adding +0.5 for more tolerance for gotthard1.
     set64BitReg(val, SET_DELAY_LSB_REG, SET_DELAY_MSB_REG);
 
     // validate for tolerance
@@ -874,9 +897,11 @@ int setDelayAfterTrigger(int64_t val) {
 }
 
 int64_t getDelayAfterTrigger() {
-    int64_t retval = get64BitReg(SET_DELAY_LSB_REG, SET_DELAY_MSB_REG) / (1E-9 * CLK_FREQ);
+    int64_t retval =
+        get64BitReg(SET_DELAY_LSB_REG, SET_DELAY_MSB_REG) / (1E-9 * CLK_FREQ);
     if (masterflags == IS_MASTER) {
-        LOG(logDEBUG1, ("\tActual Delay read (master): %lld\n", (long long int) retval));
+        LOG(logDEBUG1,
+            ("\tActual Delay read (master): %lld\n", (long long int)retval));
         retval -= masterdefaultdelay;
     }
     return retval;
@@ -891,24 +916,26 @@ int64_t getNumTriggersLeft() {
 }
 
 int64_t getPeriodLeft() {
-    return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) / (1E-9 * CLK_FREQ);
+    return get64BitReg(GET_PERIOD_LSB_REG, GET_PERIOD_MSB_REG) /
+           (1E-9 * CLK_FREQ);
 }
 
 int64_t getDelayAfterTriggerLeft() {
-    int64_t retval = get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * CLK_FREQ);
+    int64_t retval =
+        get64BitReg(GET_DELAY_LSB_REG, GET_DELAY_MSB_REG) / (1E-9 * CLK_FREQ);
     if (masterflags == IS_MASTER) {
-        LOG(logDEBUG1, ("\tGetting Actual delay (master): %lld\n", (long long int) retval));
+        LOG(logDEBUG1,
+            ("\tGetting Actual delay (master): %lld\n", (long long int)retval));
         retval -= masterdefaultdelay;
     }
     return retval;
 }
 
 int64_t getExpTimeLeft() {
-    return get64BitReg(GET_EXPTIME_LSB_REG, GET_EXPTIME_MSB_REG) / (1E-9 * CLK_FREQ);
+    return get64BitReg(GET_EXPTIME_LSB_REG, GET_EXPTIME_MSB_REG) /
+           (1E-9 * CLK_FREQ);
 }
 
-
-
 /* parameters - channel, chip, module, settings */
 
 int setModule(sls_detector_module myMod, char *mess) {
@@ -977,7 +1004,9 @@ enum detectorSettings setSettings(enum detectorSettings sett){
             confgain = GAIN_CONFGAIN_VRY_HGH_GAIN_VAL;
             break;
         default:
-            LOG(logERROR, ("This settings is not defined for this detector %d\n", (int)sett));
+            LOG(logERROR,
+                ("This settings is not defined for this detector %d\n",
+                 (int)sett));
             return -1;
         }
         // set conf gain
@@ -995,7 +1024,8 @@ enum detectorSettings getSettings(){
     uint32_t val = regval & GAIN_CONFGAIN_MSK;
     switch (val) {
     case GAIN_CONFGAIN_DYNMC_GAIN_VAL:
-        LOG(logDEBUG1, ("Settings read: Dynamic Gain. Gain Reg: 0x%x\n", regval));
+        LOG(logDEBUG1,
+            ("Settings read: Dynamic Gain. Gain Reg: 0x%x\n", regval));
         thisSettings = DYNAMICGAIN;
         break;
     case GAIN_CONFGAIN_HGH_GAIN_VAL:
@@ -1007,11 +1037,13 @@ enum detectorSettings getSettings(){
         thisSettings = LOWGAIN;
         break;
     case GAIN_CONFGAIN_MDM_GAIN_VAL:
-        LOG(logDEBUG1, ("Settings read: Medium Gain. Gain Reg: 0x%x\n", regval));
+        LOG(logDEBUG1,
+            ("Settings read: Medium Gain. Gain Reg: 0x%x\n", regval));
         thisSettings = MEDIUMGAIN;
         break;
     case GAIN_CONFGAIN_VRY_HGH_GAIN_VAL:
-        LOG(logDEBUG1, ("Settings read: Very High Gain. Gain Reg: 0x%x\n", regval));
+        LOG(logDEBUG1,
+            ("Settings read: Very High Gain. Gain Reg: 0x%x\n", regval));
         thisSettings = VERYHIGHGAIN;
         break;
     default:
@@ -1022,14 +1054,14 @@ enum detectorSettings getSettings(){
     return thisSettings;
 }
 
-
 /* parameters - dac, adc, hv */
 
 void setDAC(enum DACINDEX ind, int val, int mV) {
     if (val < 0)
         return;
 
-    LOG(logDEBUG1, ("Setting dac[%d]: %d %s \n", (int)ind, val, (mV ? "mV" : "dac units")));
+    LOG(logDEBUG1, ("Setting dac[%d]: %d %s \n", (int)ind, val,
+                    (mV ? "mV" : "dac units")));
     int dacval = val;
 #ifdef VIRTUAL
     if (!mV) {
@@ -1052,14 +1084,12 @@ int getDAC(enum DACINDEX ind, int mV) {
     }
     int voltage = -1;
     LTC2620_DacToVoltage(dacValues[ind], &voltage);
-    LOG(logDEBUG1, ("Getting DAC %d : %d dac (%d mV)\n",ind, dacValues[ind], voltage));
+    LOG(logDEBUG1,
+        ("Getting DAC %d : %d dac (%d mV)\n", ind, dacValues[ind], voltage));
     return voltage;
 }
 
-int getMaxDacSteps() {
-    return LTC2620_GetMaxNumSteps();
-}
-
+int getMaxDacSteps() { return LTC2620_GetMaxNumSteps(); }
 
 int getADC(enum ADCINDEX ind) {
 #ifdef VIRTUAL
@@ -1075,7 +1105,8 @@ int getADC(enum ADCINDEX ind){
     u_int32_t value = 0;
 
     // standby, high clk, high cs
-	bus_w(addr, (TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CLK_MSK | TEMP_SPI_IN_T2_CS_MSK));
+    bus_w(addr, (TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T1_CS_MSK |
+                 TEMP_SPI_IN_T2_CLK_MSK | TEMP_SPI_IN_T2_CS_MSK));
 
     // high clk low cs
     bus_w(addr, (TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T2_CLK_MSK));
@@ -1095,15 +1126,18 @@ int getADC(enum ADCINDEX ind){
             // only the first time
             if (i <= 10) {
                 if (ind == TEMP_ADC)
-                    value = (value << 1) + (bus_r(addrout) & TEMP_SPI_OUT_T1_DT_MSK);
+                    value = (value << 1) +
+                            (bus_r(addrout) & TEMP_SPI_OUT_T1_DT_MSK);
                 else
-                    value = (value << 1) + (bus_r(addrout) & TEMP_SPI_OUT_T2_DT_MSK);
+                    value = (value << 1) +
+                            (bus_r(addrout) & TEMP_SPI_OUT_T2_DT_MSK);
             }
         }
     }
 
     // standby high clk, high cs
-    bus_w(addr, (TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CLK_MSK | TEMP_SPI_IN_T2_CS_MSK));
+    bus_w(addr, (TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T1_CS_MSK |
+                 TEMP_SPI_IN_T2_CLK_MSK | TEMP_SPI_IN_T2_CS_MSK));
 
     LOG(logDEBUG1, ("\tInitial Temperature value: %u\n", value));
     // conversion
@@ -1141,7 +1175,8 @@ int setHighVoltage(int val){
             sel = HV_SEL_200_VAL;
             break;
         default:
-            LOG(logERROR, ("%d high voltage is not defined for this detector\n", val));
+            LOG(logERROR,
+                ("%d high voltage is not defined for this detector\n", val));
             return setHighVoltage(-1);
         }
         LOG(logDEBUG1, ("\tHigh voltage value to be sent: 0x%x\n", sel));
@@ -1189,10 +1224,8 @@ int setHighVoltage(int val){
     return retval;
 }
 
-
 /* parameters - timing, extsig */
 
-
 void setTiming(enum timingMode arg) {
     u_int32_t addr = EXT_SIGNAL_REG;
     switch (arg) {
@@ -1228,23 +1261,23 @@ enum timingMode getTiming() {
 void setExtSignal(enum externalSignalFlag mode) {
     switch (mode) {
     case TRIGGER_IN_RISING_EDGE:
-        LOG(logINFO, ("Setting External Signal flag: Trigger in Rising Edge\n"));
+        LOG(logINFO,
+            ("Setting External Signal flag: Trigger in Rising Edge\n"));
         break;
     case TRIGGER_IN_FALLING_EDGE:
-        LOG(logINFO, ("Setting External Signal flag: Trigger in Falling Edge\n"));
+        LOG(logINFO,
+            ("Setting External Signal flag: Trigger in Falling Edge\n"));
         break;
     default:
-        LOG(logERROR, ("Extsig (signal mode) %d not defined for this detector\n", mode));
+        LOG(logERROR,
+            ("Extsig (signal mode) %d not defined for this detector\n", mode));
         return;
     }
     signalMode = mode;
     setTiming(getTiming());
 }
 
-int getExtSignal() {
-    return signalMode;
-}
-
+int getExtSignal() { return signalMode; }
 
 /* configure mac */
 
@@ -1265,7 +1298,8 @@ void calcChecksum(mac_conf* mac, int sourceip, int destip) {
 
     int count = sizeof(mac->ip);
     unsigned short *addr;
-	addr = (unsigned short*)(&(mac->ip)); /* warning: assignment from incompatible pointer type */
+    addr = (unsigned short *)(&(
+        mac->ip)); /* warning: assignment from incompatible pointer type */
 
     long int sum = 0;
     while (count > 1) {
@@ -1290,21 +1324,20 @@ int configureMAC() {
     int dstport = udpDetails.dstport;
 
     LOG(logINFOBLUE, ("Configuring MAC\n"));
-	char src_mac[50], src_ip[INET_ADDRSTRLEN],dst_mac[50], dst_ip[INET_ADDRSTRLEN];
+    char src_mac[50], src_ip[INET_ADDRSTRLEN], dst_mac[50],
+        dst_ip[INET_ADDRSTRLEN];
     getMacAddressinString(src_mac, 50, srcmac);
     getMacAddressinString(dst_mac, 50, dstmac);
     getIpAddressinString(src_ip, srcip);
     getIpAddressinString(dst_ip, dstip);
 
-	LOG(logINFO, (
-	        "\tSource IP   : %s\n"
+    LOG(logINFO, ("\tSource IP   : %s\n"
                   "\tSource MAC  : %s\n"
                   "\tSource Port : %d\n"
                   "\tDest IP     : %s\n"
                   "\tDest MAC    : %s\n"
                   "\tDest Port   : %d\n",
-	        src_ip, src_mac, srcport,
-	        dst_ip, dst_mac, dstport));
+                  src_ip, src_mac, srcport, dst_ip, dst_mac, dstport));
 
 #ifdef VIRTUAL
     if (setUDPDestinationDetails(0, dst_ip, dstport) == FAIL) {
@@ -1330,42 +1363,39 @@ int configureMAC() {
 
     // write shadow regs
     bus_w(addr, bus_r(addr) | (ENT_RSTN_MSK | WRT_BCK_MSK));
-    LOG(logDEBUG1, ("\tWrite shadow regs. MultiPurpose reg: 0x%x\n", bus_r(addr)));
+    LOG(logDEBUG1,
+        ("\tWrite shadow regs. MultiPurpose reg: 0x%x\n", bus_r(addr)));
 
     // release write back
     bus_w(addr, bus_r(addr) & (~WRT_BCK_MSK));
-    LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
+    LOG(logDEBUG1,
+        ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
 
     LOG(logDEBUG1, ("\tConfiguring MAC CONF\n"));
-    mac_conf *mac_conf_regs = (mac_conf*)(Blackfin_getBaseAddress() + ENET_CONF_REG / 2);    // direct write
+    mac_conf *mac_conf_regs = (mac_conf *)(Blackfin_getBaseAddress() +
+                                           ENET_CONF_REG / 2); // direct write
     mac_conf_regs->mac.mac_dest_mac1 = ((dstmac >> (8 * 5)) & 0xFF);
     mac_conf_regs->mac.mac_dest_mac2 = ((dstmac >> (8 * 4)) & 0xFF);
     mac_conf_regs->mac.mac_dest_mac3 = ((dstmac >> (8 * 3)) & 0xFF);
     mac_conf_regs->mac.mac_dest_mac4 = ((dstmac >> (8 * 2)) & 0xFF);
     mac_conf_regs->mac.mac_dest_mac5 = ((dstmac >> (8 * 1)) & 0xFF);
     mac_conf_regs->mac.mac_dest_mac6 = ((dstmac >> (8 * 0)) & 0xFF);
-    LOG(logDEBUG1, ("\tDestination Mac: %llx %x:%x:%x:%x:%x:%x\n",
-            dstmac,
-            mac_conf_regs->mac.mac_dest_mac1,
-            mac_conf_regs->mac.mac_dest_mac2,
-            mac_conf_regs->mac.mac_dest_mac3,
-            mac_conf_regs->mac.mac_dest_mac4,
-            mac_conf_regs->mac.mac_dest_mac5,
-            mac_conf_regs->mac.mac_dest_mac6));
+    LOG(logDEBUG1,
+        ("\tDestination Mac: %llx %x:%x:%x:%x:%x:%x\n", dstmac,
+         mac_conf_regs->mac.mac_dest_mac1, mac_conf_regs->mac.mac_dest_mac2,
+         mac_conf_regs->mac.mac_dest_mac3, mac_conf_regs->mac.mac_dest_mac4,
+         mac_conf_regs->mac.mac_dest_mac5, mac_conf_regs->mac.mac_dest_mac6));
     mac_conf_regs->mac.mac_src_mac1 = ((srcmac >> (8 * 5)) & 0xFF);
     mac_conf_regs->mac.mac_src_mac2 = ((srcmac >> (8 * 4)) & 0xFF);
     mac_conf_regs->mac.mac_src_mac3 = ((srcmac >> (8 * 3)) & 0xFF);
     mac_conf_regs->mac.mac_src_mac4 = ((srcmac >> (8 * 2)) & 0xFF);
     mac_conf_regs->mac.mac_src_mac5 = ((srcmac >> (8 * 1)) & 0xFF);
     mac_conf_regs->mac.mac_src_mac6 = ((srcmac >> (8 * 0)) & 0xFF);
-    LOG(logDEBUG1, ("\tSource Mac: %llx %x:%x:%x:%x:%x:%x\n",
-            srcmac,
-            mac_conf_regs->mac.mac_src_mac1,
-            mac_conf_regs->mac.mac_src_mac2,
-            mac_conf_regs->mac.mac_src_mac3,
-            mac_conf_regs->mac.mac_src_mac4,
-            mac_conf_regs->mac.mac_src_mac5,
-            mac_conf_regs->mac.mac_src_mac6));
+    LOG(logDEBUG1,
+        ("\tSource Mac: %llx %x:%x:%x:%x:%x:%x\n", srcmac,
+         mac_conf_regs->mac.mac_src_mac1, mac_conf_regs->mac.mac_src_mac2,
+         mac_conf_regs->mac.mac_src_mac3, mac_conf_regs->mac.mac_src_mac4,
+         mac_conf_regs->mac.mac_src_mac5, mac_conf_regs->mac.mac_src_mac6));
     mac_conf_regs->mac.mac_ether_type = 0x0800; // ipv4
 
     calcChecksum(mac_conf_regs, srcip, dstip);
@@ -1375,13 +1405,15 @@ int configureMAC() {
     mac_conf_regs->udp.udp_chksum = 0x0000;
 
     LOG(logDEBUG1, ("\tConfiguring TSE\n"));
-    tse_conf *tse_conf_regs = (tse_conf*)(Blackfin_getBaseAddress() + TSE_CONF_REG / 2);     // direct write
+    tse_conf *tse_conf_regs = (tse_conf *)(Blackfin_getBaseAddress() +
+                                           TSE_CONF_REG / 2); // direct write
     tse_conf_regs->rev = 0xA00;
     tse_conf_regs->scratch = 0xCCCCCCCC;
     tse_conf_regs->command_config = 0xB;
     tse_conf_regs->mac_0 = 0x17231C00;
     tse_conf_regs->mac_1 = 0xCB4A;
-    tse_conf_regs->frm_length          = 0x5DC;      //max frame length (1500 bytes) (was 0x41C)
+    tse_conf_regs->frm_length =
+        0x5DC; // max frame length (1500 bytes) (was 0x41C)
     tse_conf_regs->pause_quant = 0x0;
     tse_conf_regs->rx_section_empty = 0x7F0;
     tse_conf_regs->rx_section_full = 0x10;
@@ -1396,13 +1428,16 @@ int configureMAC() {
     mac_conf_regs->cdone = 0xFFFFFFFF;
 
     bus_w(addr, bus_r(addr) | (INT_RSTN_MSK | WRT_BCK_MSK));
-    LOG(logDEBUG1, ("\tWrite shadow regs with int reset. MultiPurpose reg: 0x%x\n", bus_r(addr)));
+    LOG(logDEBUG1,
+        ("\tWrite shadow regs with int reset. MultiPurpose reg: 0x%x\n",
+         bus_r(addr)));
 
     usleep(100000);
 
     // release write back
     bus_w(addr, bus_r(addr) & (~WRT_BCK_MSK));
-    LOG(logDEBUG1, ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
+    LOG(logDEBUG1,
+        ("\tWrite back released. MultiPurpose reg: 0x%x\n", bus_r(addr)));
 
     bus_w(addr, bus_r(addr) | SW1_MSK);
     LOG(logDEBUG1, ("\tSw1. MultiPurpose reg: 0x%x\n", bus_r(addr)));
@@ -1410,8 +1445,9 @@ int configureMAC() {
     usleep(1000 * 1000);
     LOG(logDEBUG1, ("\tConfigure Mac Done\n"));
     {
-        /** send out first image as first packet does not give 0xcacacaca (needed to know if first image
-         * when switching back and forth between roi and no roi
+        /** send out first image as first packet does not give 0xcacacaca
+         * (needed to know if first image when switching back and forth between
+         * roi and no roi
          */
         LOG(logINFOBLUE, ("Sending an image to counter the packet numbers\n"));
         // remember old parameters
@@ -1431,12 +1467,15 @@ int configureMAC() {
         setTiming(AUTO_TIMING);
         setNumFrames(1);
         setNumTriggers(1);
-        setPeriod(1e9); // important to keep this until we have to wait for acquisition to start
+        setPeriod(1e9); // important to keep this until we have to wait for
+                        // acquisition to start
         setExpTime(900 * 1000);
 
         // take an image
         if (masterflags == IS_MASTER)
-            usleep(1 * 1000 * 1000); // required to ensure master starts acquisition only after slave has changed to basic parameters and is waiting
+            usleep(1 * 1000 * 1000); // required to ensure master starts
+                                     // acquisition only after slave has changed
+                                     // to basic parameters and is waiting
 
         int loop = 0;
         startStateMachine();
@@ -1448,7 +1487,8 @@ int configureMAC() {
         }
 
         LOG(logINFO, ("\twaited %d loops to start\n", loop));
-        LOG(logINFO, ("\tWaiting for acquisition to end (frames left: %lld)\n", (long long int)getNumFramesLeft()));
+        LOG(logINFO, ("\tWaiting for acquisition to end (frames left: %lld)\n",
+                      (long long int)getNumFramesLeft()));
         // wait for status to be done
         while (runBusy()) {
             usleep(500);
@@ -1461,8 +1501,9 @@ int configureMAC() {
                       "\ttriggers: %lld\n"
                       "\tperiod: %lld ns\n"
                       "\texptime:%lld ns\n",
-                (int)oldtiming, (long long int)oldframes, (long long int)oldtriggers,
-                (long long int)oldPeriod, (long long int)oldExptime));
+                      (int)oldtiming, (long long int)oldframes,
+                      (long long int)oldtriggers, (long long int)oldPeriod,
+                      (long long int)oldExptime));
         setTiming(oldtiming);
         setNumFrames(oldframes);
         setNumTriggers(oldtriggers);
@@ -1473,19 +1514,14 @@ int configureMAC() {
     return OK;
 }
 
-
-int getAdcConfigured(){
-    return adcConfigured;
-}
+int getAdcConfigured() { return adcConfigured; }
 
 int setDetectorPosition(int pos[]) {
     memcpy(detPos, pos, sizeof(detPos));
     return OK;
 }
 
-int* getDetectorPosition() {
-    return detPos;
-}
+int *getDetectorPosition() { return detPos; }
 
 /* gotthard specific - adc phase */
 int setPhase(enum CLKINDEX ind, int val, int degrees) {
@@ -1550,11 +1586,11 @@ void* start_timer(void* arg) {
     }
 
     int64_t periodNs = getPeriod();
-	int numFrames = (getNumFrames() *
-						getNumTriggers() );
+    int numFrames = (getNumFrames() * getNumTriggers());
     int64_t expUs = getExpTime() / 1000;
 
-    int imageSize = adcConfigured == -1 ? DATA_BYTES : NCHAN_PER_ADC * NUM_BITS_PER_PIXEL;
+    int imageSize =
+        adcConfigured == -1 ? DATA_BYTES : NCHAN_PER_ADC * NUM_BITS_PER_PIXEL;
     int dataSize = adcConfigured == -1 ? 1280 : 512;
     int packetSize = adcConfigured == -1 ? 1286 : 518;
     int packetsPerFrame = adcConfigured == -1 ? 2 : 1;
@@ -1725,7 +1761,8 @@ enum runStatus getRunStatus(){
             LOG(logINFOBLUE, ("Status: IDLE\n"));
             s = IDLE;
         } else {
-            LOG(logINFORED, ("Status: Unknown Status: 0x%x. Trying again.\n", retval));
+            LOG(logINFORED,
+                ("Status: Unknown Status: 0x%x. Trying again.\n", retval));
             int iloop = 0;
             for (iloop = 0; iloop < 10; ++iloop) {
                 usleep(1000 * 1000);
@@ -1741,8 +1778,7 @@ enum runStatus getRunStatus(){
         if (retval & STATUS_WTNG_FR_TRGGR_MSK) {
             LOG(logINFOBLUE, ("Status: Waiting\n"));
             s = WAITING;
-	    }
-	    else{
+        } else {
             LOG(logINFOBLUE, ("Status: Running\n"));
             s = RUNNING;
         }
@@ -1768,7 +1804,8 @@ void readFrame(int *ret, char *mess){
     *ret = (int)OK;
     int64_t retval = getNumFramesLeft() + 1;
     if (retval > -1) {
-		LOG(logERROR, ("No data and run stopped: %lld frames left\n",(long  long int)retval));
+        LOG(logERROR, ("No data and run stopped: %lld frames left\n",
+                       (long long int)retval));
     } else {
         LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
     }
@@ -1795,13 +1832,11 @@ u_int32_t runState(enum TLogLevel lev) {
 
 /* common */
 
-int calculateDataBytes(){
-	return DATA_BYTES;
-}
+int calculateDataBytes() { return DATA_BYTES; }
 
-int getTotalNumberOfChannels() {return  (getNumberOfChannelsPerChip() * getNumberOfChips());}
+int getTotalNumberOfChannels() {
+    return (getNumberOfChannelsPerChip() * getNumberOfChips());
+}
 int getNumberOfChips() { return NCHIP; }
 int getNumberOfDACs() { return NDAC; }
 int getNumberOfChannelsPerChip() { return NCHAN; }
-
-

slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h

@@ -4,11 +4,21 @@
 
 /* Enums */
 enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
-enum DACINDEX				        {G_VREF_DS, G_VCASCN_PB, G_VCASCP_PB, G_VOUT_CM, G_VCASC_OUT, G_VIN_CM, G_VREF_COMP, G_IB_TESTC};
+enum DACINDEX {
+    G_VREF_DS,
+    G_VCASCN_PB,
+    G_VCASCP_PB,
+    G_VOUT_CM,
+    G_VCASC_OUT,
+    G_VIN_CM,
+    G_VREF_COMP,
+    G_IB_TESTC
+};
 enum CLKINDEX { ADC_CLK, NUM_CLOCKS };
 #define CLK_NAMES "adc"
 
-#define DEFAULT_DAC_VALS   	        { 	                        \
+#define DEFAULT_DAC_VALS                                                       \
+    {                                                                          \
         660,  /* G_VREF_DS */                                                  \
         650,  /* G_VCASCN_PB */                                                \
         1480, /* G_VCASCP_PB */                                                \
@@ -34,10 +44,12 @@ enum CLKINDEX                      	{ADC_CLK, NUM_CLOCKS};
 #define CLK_FREQ           (32007729) /* Hz */
 
 /** Firmware Definitions */
-#define IP_PACKET_SIZE_NO_ROI       (NCHIP * (NCHAN / 2) * 2 + 14 + 20)     // 2 packets, so divide by 2
+#define IP_PACKET_SIZE_NO_ROI                                                  \
+    (NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
 #define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
 
-#define UDP_PACKETSIZE_NO_ROI       (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2)  // 2 packets, so divide by 2
+#define UDP_PACKETSIZE_NO_ROI                                                  \
+    (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
 #define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
 
 /** Default Parameters */
@@ -124,4 +136,3 @@ typedef struct tse_conf_struct{
     u_int32_t mdio_addr0; // 0xF
     u_int32_t mdio_addr1;
 } tse_conf;
-

slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h

@@ -11,8 +11,6 @@
 #define DETECTOR_TYPE_OFST         (24)
 #define DETECTOR_TYPE_MSK          (0x000000FF << DETECTOR_TYPE_OFST)
 
-
-
 /* Fix pattern register */
 #define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
 
@@ -34,27 +32,30 @@
 #define RUNMACHINE_BUSY_OFST     (17)
 #define RUNMACHINE_BUSY_MSK      (0x00000001 << RUNMACHINE_BUSY_OFST)
 
-
 /* Look at me register */
-#define LOOK_AT_ME_REG          		(0x03 << MEM_MAP_SHIFT)								//Not used in firmware or software
+#define LOOK_AT_ME_REG                                                         \
+    (0x03 << MEM_MAP_SHIFT) // Not used in firmware or software
 
 /* System Status register */
 #define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT) // Not used in software
 
 #define DDR3_CAL_DONE_OFST (0) // Not used in software
-#define DDR3_CAL_DONE_MSK 				(0x00000001 << DDR3_CAL_DONE_OFST)			//Not used in software
+#define DDR3_CAL_DONE_MSK                                                      \
+    (0x00000001 << DDR3_CAL_DONE_OFST) // Not used in software
 #define DDR3_CAL_FAIL_OFST (1)         // Not used in software
-#define DDR3_CAL_FAIL_MSK 				(0x00000001 << DDR3_CAL_FAIL_OFST)			//Not used in software
+#define DDR3_CAL_FAIL_MSK                                                      \
+    (0x00000001 << DDR3_CAL_FAIL_OFST) // Not used in software
 #define DDR3_INIT_DONE_OFST (2)        // Not used in software
-#define DDR3_INIT_DONE_MSK 				(0x00000001 << DDR3_INIT_DONE_OFST)			//Not used in software
+#define DDR3_INIT_DONE_MSK                                                     \
+    (0x00000001 << DDR3_INIT_DONE_OFST) // Not used in software
 #define RECONFIG_PLL_LCK_OFST (3)       // Not used in software
-#define RECONFIG_PLL_LCK_MSK 			(0x00000001 << RECONFIG_PLL_LCK_OFST)		//Not used in software
+#define RECONFIG_PLL_LCK_MSK                                                   \
+    (0x00000001 << RECONFIG_PLL_LCK_OFST)               // Not used in software
 #define PLL_A_LCK_OFST   (4)                            // Not used in software
 #define PLL_A_LCK_MSK    (0x00000001 << PLL_A_LCK_OFST) // Not used in software
 #define DD3_PLL_LCK_OFST (5)                            // Not used in software
 #define DD3_PLL_LCK_MSK  (0x00000001 << DD3_PLL_LCK_OFST) // Not used in software
 
-
 /* Module Control Board Serial Number Register */
 #define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT)
 
@@ -62,8 +63,8 @@
 #define HARDWARE_SERIAL_NUM_MSK   (0x000000FF << HARDWARE_SERIAL_NUM_OFST)
 #define HARDWARE_VERSION_NUM_OFST (16)
 #define HARDWARE_VERSION_NUM_MSK  (0x0000003F << HARDWARE_VERSION_NUM_OFST)
-#define HARDWARE_VERSION_2_VAL          ((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
-
+#define HARDWARE_VERSION_2_VAL                                                 \
+    ((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
 
 /* API Version Register */
 #define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
@@ -71,7 +72,8 @@
 #define API_VERSION_OFST               (0)
 #define API_VERSION_MSK                (0x00FFFFFF << API_VERSION_OFST)
 #define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
-#define API_VERSION_DETECTOR_TYPE_MSK   (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST)  //Not used in software
+#define API_VERSION_DETECTOR_TYPE_MSK                                          \
+    (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
 
 /* Time from Start 64 bit register */
 #define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
@@ -94,14 +96,17 @@
 #define GET_PERIOD_MSB_REG (0x19 << MEM_MAP_SHIFT)
 
 /** Get Temperature Carlos, incorrectl as get gates */
-#define GET_TEMPERATURE_TMP112_REG		(0x1c << MEM_MAP_SHIFT)							// (after multiplying by 625) in 10ths of millidegrees of TMP112
+#define GET_TEMPERATURE_TMP112_REG                                             \
+    (0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of
+                            // millidegrees of TMP112
 
 #define TEMPERATURE_VALUE_BIT    (0)
 #define TEMPERATURE_VALUE_MSK    (0x000007FF << TEMPERATURE_VALUE_BIT)
 #define TEMPERATURE_POLARITY_BIT (11)
 #define TEMPERATURE_POLARITY_MSK (0x00000001 << TEMPERATURE_POLARITY_BIT)
 
-/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
+/* Get Frames from Start 64 bit register (frames from last reset using
+ * CONTROL_CRST) */
 #define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT)
 #define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
 
@@ -157,19 +162,25 @@
 /* Configuration Register */
 #define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
 
-// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT = (RDT + 1) * 25ns
+// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT =
+// (RDT + 1) * 25ns
 #define CONFIG_RDT_TMR_OFST             (0)
 #define CONFIG_RDT_TMR_MSK              (0x0000FFFF << CONFIG_RDT_TMR_OFST)
 #define CONFIG_OPRTN_MDE_2_X_10GbE_OFST (16)
-#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK  (0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
+#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK                                         \
+    (0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
 // if 0, outer is the primary interface
 #define CONFIG_INNR_PRIMRY_INTRFCE_OFST (17)
-#define CONFIG_INNR_PRIMRY_INTRFCE_MSK  (0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
+#define CONFIG_INNR_PRIMRY_INTRFCE_MSK                                         \
+    (0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
 #define CONFIG_READOUT_SPEED_OFST (20)
 #define CONFIG_READOUT_SPEED_MSK  (0x00000003 << CONFIG_READOUT_SPEED_OFST)
-#define CONFIG_QUARTER_SPEED_10MHZ_VAL	((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
-#define CONFIG_HALF_SPEED_20MHZ_VAL		((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
-#define CONFIG_FULL_SPEED_40MHZ_VAL		((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_QUARTER_SPEED_10MHZ_VAL                                         \
+    ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_HALF_SPEED_20MHZ_VAL                                            \
+    ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_FULL_SPEED_40MHZ_VAL                                            \
+    ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
 #define CONFIG_TDMA_ENABLE_OFST      (24)
 #define CONFIG_TDMA_ENABLE_MSK       (0x00000001 << CONFIG_TDMA_ENABLE_OFST)
 #define CONFIG_TDMA_TIMESLOT_OFST    (25) // 1ms
@@ -193,20 +204,24 @@
 #define CONTROL_CORE_RST_OFST       (10)
 #define CONTROL_CORE_RST_MSK        (0x00000001 << CONTROL_CORE_RST_OFST)
 #define CONTROL_PERIPHERAL_RST_OFST (11) // DDR3 HMem Ctrlr, GBE, Temp
-#define CONTROL_PERIPHERAL_RST_MSK		(0x00000001 << CONTROL_PERIPHERAL_RST_OFST)	//DDR3 HMem Ctrlr, GBE, Temp
-#define CONTROL_DDR3_MEM_RST_OFST		(12)										//only PHY, not DDR3 PLL ,Not used in software
-#define CONTROL_DDR3_MEM_RST_MSK		(0x00000001 << CONTROL_DDR3_MEM_RST_OFST)	//only PHY, not DDR3 PLL ,Not used in software
+#define CONTROL_PERIPHERAL_RST_MSK                                             \
+    (0x00000001 << CONTROL_PERIPHERAL_RST_OFST) // DDR3 HMem Ctrlr, GBE, Temp
+#define CONTROL_DDR3_MEM_RST_OFST                                              \
+    (12) // only PHY, not DDR3 PLL ,Not used in software
+#define CONTROL_DDR3_MEM_RST_MSK                                               \
+    (0x00000001 << CONTROL_DDR3_MEM_RST_OFST) // only PHY, not DDR3 PLL ,Not
+                                              // used in software
 #define CONTROL_ACQ_FIFO_CLR_OFST     (14)
 #define CONTROL_ACQ_FIFO_CLR_MSK      (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
 #define CONTROL_STORAGE_CELL_NUM_OFST (16)
-#define CONTROL_STORAGE_CELL_NUM_MSK    (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
+#define CONTROL_STORAGE_CELL_NUM_MSK                                           \
+    (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
 #define CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST (20)
-#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK  (0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
+#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK                                       \
+    (0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
 #define CONTROL_RX_ENDPTS_START_OFST (26)
 #define CONTROL_RX_ENDPTS_START_MSK  (0x0000003F << CONTROL_RX_ENDPTS_START_OFST)
 
-
-
 /* Reconfiguratble PLL Paramater Register */
 #define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
 
@@ -214,7 +229,8 @@
 #define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
 
 #define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0) // parameter reset
-#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK	(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)	//parameter reset
+#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK                                          \
+    (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) // parameter reset
 #define PLL_CNTRL_WR_PRMTR_OFST      (2)
 #define PLL_CNTRL_WR_PRMTR_MSK       (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
 #define PLL_CNTRL_PLL_RST_OFST       (3)
@@ -229,50 +245,86 @@
 
 #define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
 #define SAMPLE_ADC_SAMPLE_SEL_MSK  (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
-#define SAMPLE_ADC_SAMPLE_0_VAL			((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
-#define SAMPLE_ADC_SAMPLE_1_VAL			((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
-#define SAMPLE_ADC_SAMPLE_2_VAL			((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
-#define SAMPLE_ADC_SAMPLE_3_VAL			((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
-#define SAMPLE_ADC_SAMPLE_4_VAL			((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
-#define SAMPLE_ADC_SAMPLE_5_VAL			((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
-#define SAMPLE_ADC_SAMPLE_6_VAL			((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
-#define SAMPLE_ADC_SAMPLE_7_VAL			((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_0_VAL                                                \
+    ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_1_VAL                                                \
+    ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_2_VAL                                                \
+    ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_3_VAL                                                \
+    ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_4_VAL                                                \
+    ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_5_VAL                                                \
+    ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_6_VAL                                                \
+    ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_7_VAL                                                \
+    ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
 // Decimation = ADF + 1
 #define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
 #define SAMPLE_ADC_DECMT_FACTOR_MSK  (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
-#define SAMPLE_ADC_DECMT_FACTOR_0_VAL	((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
-#define SAMPLE_ADC_DECMT_FACTOR_1_VAL	((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
-#define SAMPLE_ADC_DECMT_FACTOR_2_VAL	((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
-#define SAMPLE_ADC_DECMT_FACTOR_3_VAL	((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
-#define SAMPLE_ADC_DECMT_FACTOR_4_VAL	((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
-#define SAMPLE_ADC_DECMT_FACTOR_5_VAL	((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
-#define SAMPLE_ADC_DECMT_FACTOR_6_VAL	((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
-#define SAMPLE_ADC_DECMT_FACTOR_7_VAL	((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_0_VAL                                          \
+    ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_1_VAL                                          \
+    ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_2_VAL                                          \
+    ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_3_VAL                                          \
+    ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_4_VAL                                          \
+    ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_5_VAL                                          \
+    ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_6_VAL                                          \
+    ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_7_VAL                                          \
+    ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
 
 #define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
 #define SAMPLE_DGTL_SAMPLE_SEL_MSK  (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
-#define SAMPLE_DGTL_SAMPLE_0_VAL		((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_1_VAL		((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_2_VAL		((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_3_VAL		((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_4_VAL		((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_5_VAL		((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_6_VAL		((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_7_VAL		((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_8_VAL		((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_9_VAL		((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_10_VAL		((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_11_VAL		((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_12_VAL		((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_13_VAL		((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_14_VAL		((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
-#define SAMPLE_DGTL_SAMPLE_15_VAL		((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_0_VAL                                               \
+    ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_1_VAL                                               \
+    ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_2_VAL                                               \
+    ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_3_VAL                                               \
+    ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_4_VAL                                               \
+    ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_5_VAL                                               \
+    ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_6_VAL                                               \
+    ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_7_VAL                                               \
+    ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_8_VAL                                               \
+    ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_9_VAL                                               \
+    ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_10_VAL                                              \
+    ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_11_VAL                                              \
+    ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_12_VAL                                              \
+    ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_13_VAL                                              \
+    ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_14_VAL                                              \
+    ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_15_VAL                                              \
+    ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
 
 #define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
-#define SAMPLE_DGTL_DECMT_FACTOR_MSK	(0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
-#define SAMPLE_DECMT_FACTOR_FULL_VAL	((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
-#define SAMPLE_DECMT_FACTOR_HALF_VAL	((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
-#define SAMPLE_DECMT_FACTOR_QUARTER_VAL	((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+#define SAMPLE_DGTL_DECMT_FACTOR_MSK                                           \
+    (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
+#define SAMPLE_DECMT_FACTOR_FULL_VAL                                           \
+    ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+#define SAMPLE_DECMT_FACTOR_HALF_VAL                                           \
+    ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+#define SAMPLE_DECMT_FACTOR_QUARTER_VAL                                        \
+    ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
 
 /** Vref Comp Mod Register */
 #define EXT_DAQ_CTRL_REG (0x5C << MEM_MAP_SHIFT)
@@ -280,21 +332,25 @@
 #define EXT_DAQ_CTRL_VREF_COMP_OFST    (0)
 #define EXT_DAQ_CTRL_VREF_COMP_MSK     (0x00000FFF << EXT_DAQ_CTRL_VREF_COMP_OFST)
 #define EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST (15)
-#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK  (0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
+#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK                                          \
+    (0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
 #define EXT_DAQ_CTRL_INPT_DETECT_OFST (16)
-#define EXT_DAQ_CTRL_INPT_DETECT_MSK    (0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
+#define EXT_DAQ_CTRL_INPT_DETECT_MSK                                           \
+    (0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
 #define EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST (19)
-#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK  (0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
-
+#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK                                      \
+    (0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
 
 /** DAQ Register */
 #define DAQ_REG (0x5D << MEM_MAP_SHIFT)
 
-#define DAQ_SETTINGS_MSK                (DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_SETTINGS_MSK                                                       \
+    (DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
 #define DAQ_HIGH_GAIN_OFST     (0)
 #define DAQ_HIGH_GAIN_MSK      (0x00000001 << DAQ_HIGH_GAIN_OFST)
 #define DAQ_FIX_GAIN_DYNMC_VAL ((0x0 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
-#define DAQ_FIX_GAIN_HIGHGAIN_VAL       ((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
+#define DAQ_FIX_GAIN_HIGHGAIN_VAL                                              \
+    ((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
 #define DAQ_FIX_GAIN_OFST        (1)
 #define DAQ_FIX_GAIN_MSK         (0x00000003 << DAQ_FIX_GAIN_OFST)
 #define DAQ_FIX_GAIN_STG_1_VAL   ((0x1 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
@@ -305,8 +361,10 @@
 #define DAQ_STRG_CELL_SLCT_MSK   (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
 #define DAQ_FRCE_SWTCH_GAIN_OFST (12)
 #define DAQ_FRCE_SWTCH_GAIN_MSK  (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
-#define DAQ_FRCE_GAIN_STG_1_VAL         ((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
-#define DAQ_FRCE_GAIN_STG_2_VAL         ((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_FRCE_GAIN_STG_1_VAL                                                \
+    ((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_FRCE_GAIN_STG_2_VAL                                                \
+    ((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
 #define DAQ_ELCTRN_CLLCTN_MDE_OFST   (14)
 #define DAQ_ELCTRN_CLLCTN_MDE_MSK    (0x00000001 << DAQ_ELCTRN_CLLCTN_MDE_OFST)
 #define DAQ_G2_CNNT_OFST             (15)
@@ -326,19 +384,18 @@
 #define CHIP_POWER_STATUS_OFST (1)
 #define CHIP_POWER_STATUS_MSK  (0x00000001 << CHIP_POWER_STATUS_OFST)
 
-
 /** Temperature Control Register */
 #define TEMP_CTRL_REG (0x5F << MEM_MAP_SHIFT)
 
 #define TEMP_CTRL_PROTCT_THRSHLD_OFST (0)
-#define TEMP_CTRL_PROTCT_THRSHLD_MSK    (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
+#define TEMP_CTRL_PROTCT_THRSHLD_MSK                                           \
+    (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
 #define TEMP_CTRL_PROTCT_ENABLE_OFST (16)
 #define TEMP_CTRL_PROTCT_ENABLE_MSK  (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
 // set when temp higher than over threshold, write 1 to clear it
 #define TEMP_CTRL_OVR_TMP_EVNT_OFST (31)
 #define TEMP_CTRL_OVR_TMP_EVNT_MSK  (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
 
-
 /* Set Delay 64 bit register */
 #define SET_DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT) // different kind of delay
 #define SET_DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT) // different kind of delay
@@ -383,7 +440,6 @@
 #define COORD_COL_INNER_OFST (16)
 #define COORD_COL_INNER_MSK  (0x0000FFFF << COORD_COL_INNER_OFST)
 
-
 /** Module column coordinates */
 #define COORD_RESERVED_REG (0x7E << MEM_MAP_SHIFT)
 
@@ -397,39 +453,42 @@
 // tPC = (PCT + 1) * 25ns
 #define ASIC_CTRL_PRCHRG_TMR_OFST (0)
 #define ASIC_CTRL_PRCHRG_TMR_MSK  (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
-#define ASIC_CTRL_PRCHRG_TMR_VAL        ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
+#define ASIC_CTRL_PRCHRG_TMR_VAL                                               \
+    ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
 // tDS = (DST + 1) * 25ns
 #define ASIC_CTRL_DS_TMR_OFST (8)
 #define ASIC_CTRL_DS_TMR_MSK  (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
-#define ASIC_CTRL_DS_TMR_VAL            ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
-// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage cells)
+#define ASIC_CTRL_DS_TMR_VAL                                                   \
+    ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
+// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage
+// cells)
 #define ASIC_CTRL_EXPSRE_TMR_OFST    (16)
 #define ASIC_CTRL_EXPSRE_TMR_MSK     (0x0000FFFF << ASIC_CTRL_EXPSRE_TMR_OFST)
 #define ASIC_CTRL_EXPSRE_TMR_MAX_VAL (0x0000FFFF / (CLK_RUN * 1E-3))
 
-
 /* ADC 0 Deserializer Control */
 #define ADC_DSRLZR_0_REG                (0xF0 << MEM_MAP_SHIFT)
 #define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */
-#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
+#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK                                         \
+    (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
 
 /* ADC 0 Deserializer Control */
 #define ADC_DSRLZR_1_REG                (0xF1 << MEM_MAP_SHIFT)
 #define ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST (31)
-#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
+#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK                                         \
+    (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
 
 /* ADC 0 Deserializer Control */
 #define ADC_DSRLZR_2_REG                (0xF2 << MEM_MAP_SHIFT)
 #define ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST (31)
-#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
+#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK                                         \
+    (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
 
 /* ADC 0 Deserializer Control */
 #define ADC_DSRLZR_3_REG                (0xF3 << MEM_MAP_SHIFT)
 #define ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST (31)
-#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
-
-
-
+#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK                                         \
+    (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
 
 /* Round Robin  */
 #define RXR_ENDPOINTS_MAX            (64)
@@ -437,8 +496,3 @@
 #define RXR_ENDPOINT_INNER_START_REG (0x2000 << MEM_MAP_SHIFT)
 
 #define RXR_ENDPOINT_OFST (0x10 << MEM_MAP_SHIFT)
-
-
-
-
-

slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h

@@ -1,7 +1,6 @@
 #pragma once
-#include "sls_detector_defs.h"
 #include "RegisterDefs.h"
-
+#include "sls_detector_defs.h"
 
 #define MIN_REQRD_VRSN_T_RD_API  0x171220
 #define REQRD_FRMWRE_VRSN_BOARD2 0x190716 // old
@@ -36,11 +35,21 @@ typedef struct udp_header_struct {
 #define IP_HEADER_SIZE             (20)
 #define UDP_IP_HEADER_LENGTH_BYTES (28)
 
-
 /* Enums */
 enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
-enum DACINDEX				{J_VB_COMP, J_VDD_PROT, J_VIN_COM, J_VREF_PRECH, J_VB_PIXBUF, J_VB_DS, J_VREF_DS, J_VREF_COMP };
-#define DEFAULT_DAC_VALS   	{ 	1220,	/* J_VB_COMP */		\
+enum DACINDEX {
+    J_VB_COMP,
+    J_VDD_PROT,
+    J_VIN_COM,
+    J_VREF_PRECH,
+    J_VB_PIXBUF,
+    J_VB_DS,
+    J_VREF_DS,
+    J_VREF_COMP
+};
+#define DEFAULT_DAC_VALS                                                       \
+    {                                                                          \
+        1220, /* J_VB_COMP */                                                  \
         3000, /* J_VDD_PROT */                                                 \
         1053, /* J_VIN_COM */                                                  \
         1450, /* J_VREF_PRECH */                                               \
@@ -97,8 +106,6 @@ enum CLKINDEX               {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
 #define MAX_PHASE_SHIFTS (160)
 #define BIT16_MASK       (0xFFFF)
 
-
-
 #define ADC_OFST_FULL_SPEED_VAL           (0xf)
 #define ADC_OFST_HALF_SPEED_VAL           (0xb)
 #define ADC_OFST_QUARTER_SPEED_VAL        (0x7)
@@ -108,11 +115,21 @@ enum CLKINDEX               {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
 #define ADC_PORT_INVERT_VAL        (0x5A5A5A5A)
 #define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
 
-#define SAMPLE_ADC_FULL_SPEED				(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
-#define SAMPLE_ADC_HALF_SPEED	 			(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
-#define SAMPLE_ADC_QUARTER_SPEED 			(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL)	// 0x2630 
-#define SAMPLE_ADC_HALF_SPEED_BOARD2 	 	(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
-#define SAMPLE_ADC_QUARTER_SPEED_BOARD2  	(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL)	// 0x2b10 
+#define SAMPLE_ADC_FULL_SPEED                                                  \
+    (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL +                 \
+     SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
+#define SAMPLE_ADC_HALF_SPEED                                                  \
+    (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL +                 \
+     SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
+#define SAMPLE_ADC_QUARTER_SPEED                                               \
+    (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL +                 \
+     SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
+#define SAMPLE_ADC_HALF_SPEED_BOARD2                                           \
+    (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL +                 \
+     SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
+#define SAMPLE_ADC_QUARTER_SPEED_BOARD2                                        \
+    (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL +                 \
+     SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
 
 #define ADC_PHASE_FULL_SPEED           (28)
 #define ADC_PHASE_HALF_SPEED           (35)
@@ -120,7 +137,6 @@ enum CLKINDEX               {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
 #define ADC_PHASE_HALF_SPEED_BOARD2    (0x1E) // 30
 #define ADC_PHASE_QUARTER_SPEED_BOARD2 (0x1E) // 30
 
-
 #define DBIT_PHASE_FULL_SPEED           (37)
 #define DBIT_PHASE_HALF_SPEED           (37)
 #define DBIT_PHASE_QUARTER_SPEED        (37)

slsDetectorServers/moenchDetectorServer/RegisterDefs.h

@@ -3,7 +3,6 @@
 /* Definitions for FPGA */
 #define MEM_MAP_SHIFT 1
 
-
 /* FPGA Version RO register */
 #define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
 
@@ -11,7 +10,8 @@
 #define FPGA_VERSION_BRD_RVSN_MSK   (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
 #define FPGA_VERSION_DTCTR_TYP_OFST (24)
 #define FPGA_VERSION_DTCTR_TYP_MSK  (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
-#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL   ((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
+#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL                                      \
+    ((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
 
 /* Fix pattern RO register */
 #define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@@ -58,7 +58,8 @@
 #define STATUS_PLL_PHS_DN_OFST        (23)
 #define STATUS_PLL_PHS_DN_MSK         (0x00000001 << STATUS_PLL_PHS_DN_OFST)
 #define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
-#define STATUS_PT_CNTRL_STTS_OFF_MSK        (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
+#define STATUS_PT_CNTRL_STTS_OFF_MSK                                           \
+    (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
 #define STATUS_IDLE_MSK (0x677FF)
 
 /* Look at me RO register TODO */
@@ -68,24 +69,30 @@
 #define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
 
 #define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
-#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK 	(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
+#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK                                       \
+    (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
 #define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
-#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK 	(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
+#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK                                       \
+    (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
 #define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
-#define SYSTEM_STATUS_DDR3_INT_DN_MSK 		(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
+#define SYSTEM_STATUS_DDR3_INT_DN_MSK                                          \
+    (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
 #define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
-#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK 	(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
+#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK                                        \
+    (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
 #define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
 #define SYSTEM_STATUS_PLL_A_LCK_MSK  (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
 
-/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
+/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
+ * PLL_PARAM_REG 0x50 */
 //#define PLL_PARAM_REG                       (0x05 << MEM_MAP_SHIFT)
 
 /* FIFO Data RO register TODO */
 #define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
 
 #define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
-#define FIFO_DATA_HRDWR_SRL_NMBR_MSK        (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
+#define FIFO_DATA_HRDWR_SRL_NMBR_MSK                                           \
+    (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
 //#define FIFO_DATA_WRD_OFST                  (16)
 //#define FIFO_DATA_WRD_MSK                   (0x0000FFFF << FIFO_DATA_WRD_OFST)
 
@@ -115,7 +122,8 @@
 #define API_VERSION_DTCTR_TYP_OFST (24)
 #define API_VERSION_DTCTR_TYP_MSK  (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
 
-/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
+/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
+ * CONTROL_CRST. TODO */
 #define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
 #define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
 
@@ -136,12 +144,16 @@
 #define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
 
 /* Exposure Time Left 64 bit RO register */
-//#define EXPTIME_LEFT_LSB_REG                (0x1A << MEM_MAP_SHIFT)            // Not used in FW
-//#define EXPTIME_LEFT_MSB_REG                (0x1B << MEM_MAP_SHIFT)            // Not used in FW
+//#define EXPTIME_LEFT_LSB_REG                (0x1A << MEM_MAP_SHIFT) // Not
+// used in FW #define EXPTIME_LEFT_MSB_REG                (0x1B <<
+// MEM_MAP_SHIFT)
+//// Not used in FW
 
 /* Gates Left 64 bit RO register */
-//#define GATES_LEFT_LSB_REG                  (0x1C << MEM_MAP_SHIFT)            // Not used in FW
-//#define GATES_LEFT_MSB_REG                  (0x1D << MEM_MAP_SHIFT)            // Not used in FW
+//#define GATES_LEFT_LSB_REG                  (0x1C << MEM_MAP_SHIFT) // Not
+// used in FW #define GATES_LEFT_MSB_REG                  (0x1D <<
+// MEM_MAP_SHIFT)
+//// Not used in FW
 
 /* Data In 64 bit RO register TODO */
 #define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
@@ -152,14 +164,17 @@
 #define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
 
 /* Frames From Start 64 bit RO register TODO */
-//#define FRAMES_FROM_START_LSB_REG           (0x22 << MEM_MAP_SHIFT)            // Not used in FW
-//#define FRAMES_FROM_START_MSB_REG           (0x23 << MEM_MAP_SHIFT)            // Not used in FW
+//#define FRAMES_FROM_START_LSB_REG           (0x22 << MEM_MAP_SHIFT) // Not
+// used in FW #define FRAMES_FROM_START_MSB_REG           (0x23 <<
+// MEM_MAP_SHIFT)
+//// Not used in FW
 
 /* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
 #define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
 #define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
 
-/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
+/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
+ * start until reset) TODO */
 #define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
 #define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
 
@@ -178,9 +193,11 @@
 /* FIFO Digital In Status RO register */
 #define FIFO_DIN_STATUS_REG            (0x3B << MEM_MAP_SHIFT)
 #define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
-#define FIFO_DIN_STATUS_FIFO_FULL_MSK		(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
+#define FIFO_DIN_STATUS_FIFO_FULL_MSK                                          \
+    (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
 #define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
-#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK		(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
+#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK                                         \
+    (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
 
 /* FIFO Digital In 64 bit RO register */
 #define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
@@ -244,9 +261,11 @@
 #define DUMMY_FIFO_CHNNL_SLCT_OFST    (0)
 #define DUMMY_FIFO_CHNNL_SLCT_MSK     (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
 #define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
-#define DUMMY_ANLG_FIFO_RD_STRBE_MSK        (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
+#define DUMMY_ANLG_FIFO_RD_STRBE_MSK                                           \
+    (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
 #define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
-#define DUMMY_DGTL_FIFO_RD_STRBE_MSK        (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
+#define DUMMY_DGTL_FIFO_RD_STRBE_MSK                                           \
+    (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
 
 /* Receiver IP Address RW register */
 #define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
@@ -314,21 +333,23 @@
 #define CONTROL_STP_ACQSTN_OFST  (1)
 #define CONTROL_STP_ACQSTN_MSK   (0x00000001 << CONTROL_STP_ACQSTN_OFST)
 //#define CONTROL_STRT_FF_TST_OFST            (2)
-//#define CONTROL_STRT_FF_TST_MSK             (0x00000001 << CONTROL_STRT_FF_TST_OFST)
-//#define CONTROL_STP_FF_TST_OFST             (3)
-//#define CONTROL_STP_FF_TST_MSK              (0x00000001 << CONTROL_STP_FF_TST_OFST)
-//#define CONTROL_STRT_RDT_OFST               (4)
-//#define CONTROL_STRT_RDT_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
-//#define CONTROL_STP_RDT_OFST                (5)
-//#define CONTROL_STP_RDT_MSK                 (0x00000001 << CONTROL_STP_RDT_OFST)
+//#define CONTROL_STRT_FF_TST_MSK             (0x00000001 <<
+// CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST             (3)
+//#define CONTROL_STP_FF_TST_MSK              (0x00000001 <<
+// CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST               (4)
+//#define CONTROL_STRT_RDT_MSK                (0x00000001 <<
+// CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST                (5)
+// #define CONTROL_STP_RDT_MSK                 (0x00000001 <<
+// CONTROL_STP_RDT_OFST)
 #define CONTROL_STRT_EXPSR_OFST (6)
 #define CONTROL_STRT_EXPSR_MSK  (0x00000001 << CONTROL_STRT_EXPSR_OFST)
 //#define CONTROL_STP_EXPSR_OFST              (7)
-//#define CONTROL_STP_EXPSR_MSK               (0x00000001 << CONTROL_STP_RDT_OFST)
-//#define CONTROL_STRT_TRN_OFST               (8)
-//#define CONTROL_STRT_TRN_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
+//#define CONTROL_STP_EXPSR_MSK               (0x00000001 <<
+// CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST               (8) #define
+// CONTROL_STRT_TRN_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
 //#define CONTROL_STP_TRN_OFST                (9)
-//#define CONTROL_STP_TRN_MSK                 (0x00000001 << CONTROL_STP_RDT_OFST)
+//#define CONTROL_STP_TRN_MSK                 (0x00000001 <<
+// CONTROL_STP_RDT_OFST)
 #define CONTROL_CRE_RST_OFST    (10)
 #define CONTROL_CRE_RST_MSK     (0x00000001 << CONTROL_CRE_RST_OFST)
 #define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
@@ -336,7 +357,8 @@
 #define CONTROL_MMRY_RST_OFST   (12)
 #define CONTROL_MMRY_RST_MSK    (0x00000001 << CONTROL_MMRY_RST_OFST)
 //#define CONTROL_PLL_RCNFG_WR_OFST           (13)
-//#define CONTROL_PLL_RCNFG_WR_MSK            (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
+//#define CONTROL_PLL_RCNFG_WR_MSK            (0x00000001 <<
+// CONTROL_PLL_RCNFG_WR_OFST)
 #define CONTROL_SND_10GB_PCKT_OFST   (14)
 #define CONTROL_SND_10GB_PCKT_MSK    (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
 #define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
@@ -349,7 +371,8 @@
 #define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
 
 #define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
-#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK		(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
+#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK                                          \
+    (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
 #define PLL_CNTRL_WR_PRMTR_OFST (2)
 #define PLL_CNTRL_WR_PRMTR_MSK  (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
 #define PLL_CNTRL_PLL_RST_OFST  (3)
@@ -379,7 +402,8 @@
 #define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_0_ADDR_STRT_MSK        (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
+#define PATTERN_LOOP_0_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
 #define PATTERN_LOOP_0_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_0_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
 
@@ -390,7 +414,8 @@
 #define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_1_ADDR_STRT_MSK        (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
+#define PATTERN_LOOP_1_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
 #define PATTERN_LOOP_1_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_1_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
 
@@ -401,7 +426,8 @@
 #define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_2_ADDR_STRT_MSK        (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
+#define PATTERN_LOOP_2_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
 #define PATTERN_LOOP_2_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_2_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
 
@@ -446,7 +472,6 @@
 /* Number of Words RW register TODO */
 #define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
 
-
 /* Delay 64 bit RW register. t = DLY x 50 ns. */
 #define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
 #define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
@@ -464,12 +489,14 @@
 #define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
 
 /* Period 64 bit RW register */
-//#define EXPTIME_LSB_REG    			    (0x68 << MEM_MAP_SHIFT)                 // Not used in FW
-//#define EXPTIME_MSB_REG    			    (0x69 << MEM_MAP_SHIFT)                 // Not used in FW
+//#define EXPTIME_LSB_REG    			    (0x68 << MEM_MAP_SHIFT) //
+// Not used in FW #define EXPTIME_MSB_REG    			    (0x69 <<
+// MEM_MAP_SHIFT)                 // Not used in FW
 
 /* Gates 64 bit RW register */
-//#define GATES_LSB_REG                      (0x6A << MEM_MAP_SHIFT)                 // Not used in FW
-//#define GATES_MSB_REG                      (0x6B << MEM_MAP_SHIFT)                 // Not used in FW
+//#define GATES_LSB_REG                      (0x6A << MEM_MAP_SHIFT) // Not used
+// in FW #define GATES_MSB_REG                      (0x6B << MEM_MAP_SHIFT) //
+// Not used in FW
 
 /* Pattern IO Control 64 bit RW regiser
  * Each bit configured as output(1)/ input(0) */
@@ -507,7 +534,8 @@
 #define READOUT_10G_ENABLE_DGTL_MSK  (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
 
 /* Digital Bit External Trigger RW register */
-#define DBIT_EXT_TRG_REG                    (0x7B << MEM_MAP_SHIFT)                 // Not used in firmware or software
+#define DBIT_EXT_TRG_REG                                                       \
+    (0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
 
 #define DBIT_EXT_TRG_SRC_OFST      (0)
 #define DBIT_EXT_TRG_SRC_MSK       (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
@@ -515,20 +543,26 @@
 #define DBIT_EXT_TRG_OPRTN_MD_MSK  (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
 
 /* Pin Delay 0 RW register */
-#define OUTPUT_DELAY_0_REG                  (0x7C << MEM_MAP_SHIFT)                 // Not used in firmware or software
+#define OUTPUT_DELAY_0_REG                                                     \
+    (0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
 
 #define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
-#define OUTPUT_DELAY_0_OTPT_STTNG_OFST      (0)     //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
-#define OUTPUT_DELAY_0_OTPT_STTNG_MSK       (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
-// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
+#define OUTPUT_DELAY_0_OTPT_STTNG_OFST                                         \
+    (0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
+#define OUTPUT_DELAY_0_OTPT_STTNG_MSK                                          \
+    (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
+// 1: load dynamic output settings, 0: trigger start of dynamic output delay
+// configuration pn falling edge of ODT (output delay trigger) bit
 #define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
-#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK       (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
+#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK                                          \
+    (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
 #define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL   (1)
 #define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
 
 /* Pin Delay 1 RW register
  * Each bit configured as enable for dynamic output delay configuration */
-#define PIN_DELAY_1_REG                     (0x7D << MEM_MAP_SHIFT)                 // Not used in firmware or software
+#define PIN_DELAY_1_REG                                                        \
+    (0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
 
 /** Pattern Mask 64 bit RW regiser */
 #define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
@@ -540,5 +574,3 @@
 
 /* Round Robin  */
 #define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
-
-

slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h

@@ -1,7 +1,6 @@
 #pragma once
-#include "sls_detector_defs.h"
 #include "RegisterDefs.h"
-
+#include "sls_detector_defs.h"
 
 #define MIN_REQRD_VRSN_T_RD_API 0x180314
 #define REQRD_FRMWR_VRSN        0x200302
@@ -36,9 +35,22 @@ typedef struct udp_header_struct {
 #define UDP_IP_HEADER_LENGTH_BYTES (28)
 
 /* Enums */
-enum DACINDEX               {MO_VBP_COLBUF, MO_VIPRE, MO_VIN_CM, MO_VB_SDA, MO_VCASC_SFP, MO_VOUT_CM, MO_VIPRE_CDS, MO_IBIAS_SFP};
-#define DAC_NAMES			"vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", "vipre_cds", "ibias_sfp"
-#define DEFAULT_DAC_VALS   	{ 	1300,	/* MO_VBP_COLBUF */		\
+enum DACINDEX {
+    MO_VBP_COLBUF,
+    MO_VIPRE,
+    MO_VIN_CM,
+    MO_VB_SDA,
+    MO_VCASC_SFP,
+    MO_VOUT_CM,
+    MO_VIPRE_CDS,
+    MO_IBIAS_SFP
+};
+#define DAC_NAMES                                                              \
+    "vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm",         \
+        "vipre_cds", "ibias_sfp"
+#define DEFAULT_DAC_VALS                                                       \
+    {                                                                          \
+        1300, /* MO_VBP_COLBUF */                                              \
         1000, /* MO_VIPRE */                                                   \
         1400, /* MO_VIN_CM */                                                  \
         680,  /* MO_VB_SDA */                                                  \
@@ -106,10 +118,14 @@ enum CLKINDEX               {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
 
 /* Defines in the Firmware */
 #define MAX_PATTERN_LENGTH (0x2000)
-#define DIGITAL_IO_DELAY_MAXIMUM_PS	((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
+#define DIGITAL_IO_DELAY_MAXIMUM_PS                                            \
+    ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) *       \
+     OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
 #define MAX_PHASE_SHIFTS_STEPS (8)
 
-#define WAIT_TME_US_FR_ACQDONE_REG 	(100) // wait time in us after acquisition done to ensure there is no data in fifo
+#define WAIT_TME_US_FR_ACQDONE_REG                                             \
+    (100) // wait time in us after acquisition done to ensure there is no data
+          // in fifo
 #define WAIT_TIME_US_PLL           (10 * 1000)
 #define WAIT_TIME_US_STP_ACQ       (100)
 #define WAIT_TIME_CONFIGURE_MAC    (2 * 1000 * 1000)
@@ -125,4 +141,3 @@ enum CLKINDEX               {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
 #define ADC_PORT_INVERT_VAL (0x4a342593)
 #define MAXIMUM_ADC_CLK     (20)
 #define PLL_VCO_FREQ_MHZ    (800)
-

slsDetectorServers/mythen3DetectorServer/Makefile

@@ -5,7 +5,7 @@ support_lib = ../../slsSupportLib/include/
 
 CROSS  		= nios2-buildroot-linux-gnu-
 CC    		= $(CROSS)gcc
-CFLAGS		+=  -Wall -DMYTHEN3D  -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir) -DDEBUG1 #-DVERBOSEI #-DVERBOSE 
+CFLAGS		+=  -Wall -DMYTHEN3D  -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir) #-DDEBUG1 #-DVERBOSEI #-DVERBOSE 
 LDLIBS		+= 	-lm
 PROGS		= 	mythen3DetectorServer 
 DESTDIR		?= 	bin

slsDetectorServers/mythen3DetectorServer/RegisterDefs.h

@@ -1,6 +1,5 @@
 #pragma once
 
-
 #define REG_OFFSET (4)
 
 /* Base addresses 0x1804 0000 ---------------------------------------------*/
@@ -43,9 +42,8 @@
 /* Pattern RAM. Pattern table */
 #define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF
 
-
-
-/* Clock Generation registers ------------------------------------------------------*/
+/* Clock Generation registers
+ * ------------------------------------------------------*/
 #define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
 
 #define PLL_RESET_READOUT_OFST (0)
@@ -53,8 +51,6 @@
 #define PLL_RESET_SYSTEM_OFST  (1)
 #define PLL_RESET_SYSTEM_MSK   (0x00000001 << PLL_RESET_SYSTEM_OFST)
 
-
-
 /* Control registers --------------------------------------------------*/
 
 /* Module Control Board Serial Number Register */
@@ -71,14 +67,14 @@
 #define DETECTOR_TYPE_OFST         (24)
 #define DETECTOR_TYPE_MSK          (0x000000FF << DETECTOR_TYPE_OFST)
 
-
 /* API Version Register */
 #define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
 
 #define API_VERSION_OFST               (0)
 #define API_VERSION_MSK                (0x00FFFFFF << API_VERSION_OFST)
 #define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
-#define API_VERSION_DETECTOR_TYPE_MSK   (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST)  //Not used in software
+#define API_VERSION_DETECTOR_TYPE_MSK                                          \
+    (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
 
 /* Fix pattern register */
 #define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
@@ -88,25 +84,35 @@
 #define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
 
 /* Look at me register, read only */
-#define LOOK_AT_ME_REG          		(0x05 * REG_OFFSET + BASE_CONTROL)	//Not used in firmware or software, good to play with
-
-#define SYSTEM_STATUS_REG               (0x06 * REG_OFFSET + BASE_CONTROL)  //Not used in software
+#define LOOK_AT_ME_REG                                                         \
+    (0x05 * REG_OFFSET +                                                       \
+     BASE_CONTROL) // Not used in firmware or software, good to play with
 
+#define SYSTEM_STATUS_REG                                                      \
+    (0x06 * REG_OFFSET + BASE_CONTROL) // Not used in software
 
 /* Config RW regiseter */
 #define CONFIG_REG              (0x20 * REG_OFFSET + BASE_CONTROL)
 #define CONFIG_COUNTER_ENA_OFST (0)
 #define CONFIG_COUNTER_ENA_MSK  (0x00000003 << CONFIG_COUNTER_ENA_OFST)
-#define CONFIG_COUNTER_ENA_DEFAULT_VAL  ((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
-#define CONFIG_COUNTER_ENA_1_VAL        ((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
-#define CONFIG_COUNTER_ENA_2_VAL        ((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
-#define CONFIG_COUNTER_ENA_ALL_VAL      ((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
+#define CONFIG_COUNTER_ENA_DEFAULT_VAL                                         \
+    ((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
+#define CONFIG_COUNTER_ENA_1_VAL                                               \
+    ((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
+#define CONFIG_COUNTER_ENA_2_VAL                                               \
+    ((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
+#define CONFIG_COUNTER_ENA_ALL_VAL                                             \
+    ((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
 #define CONFIG_DYNAMIC_RANGE_OFST (4)
 #define CONFIG_DYNAMIC_RANGE_MSK  (0x00000003 << CONFIG_DYNAMIC_RANGE_OFST)
-#define CONFIG_DYNAMIC_RANGE_1_VAL      ((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
-#define CONFIG_DYNAMIC_RANGE_4_VAL      ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
-#define CONFIG_DYNAMIC_RANGE_16_VAL     ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
-#define CONFIG_DYNAMIC_RANGE_24_VAL     ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
+#define CONFIG_DYNAMIC_RANGE_1_VAL                                             \
+    ((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
+#define CONFIG_DYNAMIC_RANGE_4_VAL                                             \
+    ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
+#define CONFIG_DYNAMIC_RANGE_16_VAL                                            \
+    ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
+#define CONFIG_DYNAMIC_RANGE_24_VAL                                            \
+    ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
 
 /* Control RW register */
 #define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
@@ -130,8 +136,6 @@
 
 #define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
 
-
-
 /* Packetizer -------------------------------------------------------------*/
 
 /* Packetizer Config Register */
@@ -154,23 +158,27 @@
 #define COORD_RESERVED_OFST (0)
 #define COORD_RESERVED_MSK  (0x0000FFFF << COORD_RESERVED_OFST)
 #define COORD_ID_OFST       (16) // Not connected in firmware TODO
-#define COORD_ID_MSK				    (0x0000FFFF << COORD_ID_OFST)   // Not connected in firmware TODO
+#define COORD_ID_MSK                                                           \
+    (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
 
-
-/* Pattern Control registers --------------------------------------------------*/
+/* Pattern Control registers
+ * --------------------------------------------------*/
 
 /* Pattern status Register*/
 #define PAT_STATUS_REG                 (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
 #define PAT_STATUS_RUN_BUSY_OFST       (0)
 #define PAT_STATUS_RUN_BUSY_MSK        (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
 #define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
-#define PAT_STATUS_WAIT_FOR_TRGGR_MSK	(0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
+#define PAT_STATUS_WAIT_FOR_TRGGR_MSK                                          \
+    (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
 #define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
-#define PAT_STATUS_DLY_BFRE_TRGGR_MSK	(0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
+#define PAT_STATUS_DLY_BFRE_TRGGR_MSK                                          \
+    (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
 #define PAT_STATUS_FIFO_FULL_OFST      (5)
 #define PAT_STATUS_FIFO_FULL_MSK       (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
 #define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
-#define PAT_STATUS_DLY_AFTR_TRGGR_MSK	(0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
+#define PAT_STATUS_DLY_AFTR_TRGGR_MSK                                          \
+    (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
 #define PAT_STATUS_CSM_BUSY_OFST (17)
 #define PAT_STATUS_CSM_BUSY_MSK  (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
 
@@ -194,7 +202,8 @@
 #define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_PATTERN_CONTROL)
 #define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_PATTERN_CONTROL)
 
-/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
+/* Get Frames from Start 64 bit register (frames from last reset using
+ * CONTROL_CRST) */
 #define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_PATTERN_CONTROL)
 #define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_PATTERN_CONTROL)
 
@@ -261,7 +270,8 @@
 #define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL)
 
 #define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_0_ADDR_STRT_MSK    (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
+#define PATTERN_LOOP_0_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
 #define PATTERN_LOOP_0_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_0_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
 
@@ -282,7 +292,8 @@
 #define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL)
 
 #define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_1_ADDR_STRT_MSK    (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
+#define PATTERN_LOOP_1_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
 #define PATTERN_LOOP_1_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_1_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
 
@@ -303,11 +314,11 @@
 #define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL)
 
 #define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
-#define PATTERN_LOOP_2_ADDR_STRT_MSK    (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
+#define PATTERN_LOOP_2_ADDR_STRT_MSK                                           \
+    (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
 #define PATTERN_LOOP_2_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_2_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
 
-
 /* Pattern RAM registers --------------------------------------------------*/
 
 /* Register of first word */

slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h

@@ -22,7 +22,6 @@
 #define TYPE_TOLERANCE              (10)
 #define TYPE_NO_MODULE_STARTING_VAL (800)
 
-
 /** Default Parameters */
 #define DEFAULT_DYNAMIC_RANGE       (24)
 #define DEFAULT_NUM_FRAMES          (1)
@@ -32,12 +31,11 @@
 #define DEFAULT_DELAY_AFTER_TRIGGER (0)
 #define DEFAULT_HIGH_VOLTAGE        (0)
 #define DEFAULT_TIMING_MODE         (AUTO_TIMING)
-#define DEFAULT_READOUT_C0          (125000000) // rdo_clk, 125 MHz  
-#define DEFAULT_READOUT_C1          (125000000) // rdo_x2_clk, 125 MHz  
-#define DEFAULT_SYSTEM_C0			(250000000) // run_clk, 250 MHz 
-#define DEFAULT_SYSTEM_C1			(125000000) // chip_clk, 125 MHz 
-#define DEFAULT_SYSTEM_C2			(125000000) // sync_clk, 125 MHz 
-
+#define DEFAULT_READOUT_C0          (10) //(125000000) // rdo_clk, 125 MHz
+#define DEFAULT_READOUT_C1          (10) //(125000000) // rdo_x2_clk, 125 MHz
+#define DEFAULT_SYSTEM_C0           (5)  //(250000000) // run_clk, 250 MHz
+#define DEFAULT_SYSTEM_C1           (10) //(125000000) // chip_clk, 125 MHz
+#define DEFAULT_SYSTEM_C2           (10) //(125000000) // sync_clk, 125 MHz
 
 /* Firmware Definitions */
 #define IP_HEADER_SIZE          (20)
@@ -48,11 +46,34 @@
 
 /** Other Definitions */
 #define BIT16_MASK         (0xFFFF)
+#define MAX_TRIMBITS_VALUE (63)
 
 /* Enums */
-enum DACINDEX   					{M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPL, M_VIPRE, M_VIINSH, M_VPH, M_VTRIM, M_VDCSH};
-#define  DAC_NAMES					"vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", "vdcsh"
-#define DEFAULT_DAC_VALS   			{1200,    /* casSh */     \
+enum DACINDEX {
+    M_CASSH,
+    M_VTH2,
+    M_VRFSH,
+    M_VRFSHNPOL,
+    M_VIPRE_OUT,
+    M_VTH3,
+    M_VTH1,
+    M_VICIN,
+    M_CAS,
+    M_VRF,
+    M_VPL,
+    M_VIPRE,
+    M_VIINSH,
+    M_VPH,
+    M_VTRIM,
+    M_VDCSH
+};
+#define DAC_NAMES                                                              \
+    "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1",    \
+        "vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim",  \
+        "vdcsh"
+#define DEFAULT_DAC_VALS                                                       \
+    {                                                                          \
+        1200, /* casSh */                                                      \
         2800, /* Vth2 */                                                       \
         1280, /* VrfSh */                                                      \
         2800, /* VrfShNpol */                                                  \
@@ -69,8 +90,16 @@ enum DACINDEX   					{M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3
         2800, /* vTrim */                                                      \
         800   /* VdcSh */                                                      \
     };
-enum CLKINDEX   					{READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
-#define CLK_NAMES					"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
+enum CLKINDEX {
+    READOUT_C0,
+    READOUT_C1,
+    SYSTEM_C0,
+    SYSTEM_C1,
+    SYSTEM_C2,
+    NUM_CLOCKS
+};
+#define CLK_NAMES                                                              \
+    "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
 enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
 
 /* Struct Definitions */
@@ -98,3 +127,31 @@ typedef struct udp_header_struct {
 } udp_header;
 #define UDP_IP_HEADER_LENGTH_BYTES (28)
 #define PACKETS_PER_FRAME          (2)
+
+/** Signal Definitions */
+#define SIGNAL_TBLoad_1    (0)
+#define SIGNAL_TBLoad_2    (1)
+#define SIGNAL_TBLoad_3    (2)
+#define SIGNAL_TBLoad_4    (3)
+#define SIGNAL_TBLoad_5    (4)
+#define SIGNAL_TBLoad_6    (5)
+#define SIGNAL_TBLoad_7    (6)
+#define SIGNAL_TBLoad_8    (7)
+#define SIGNAL_TBLoad_9    (8)
+#define SIGNAL_TBLoad_10   (9)
+#define SIGNAL_AnaMode     (10)
+#define SIGNAL_CHSserialIN (11)
+#define SIGNAL_READOUT     (12)
+#define SIGNAL_pulse       (13)
+#define SIGNAL_EN1         (14)
+#define SIGNAL_EN2         (15)
+#define SIGNAL_EN3         (16)
+#define SIGNAL_clk         (17)
+#define SIGNAL_SRmode      (18)
+#define SIGNAL_serialIN    (19)
+#define SIGNAL_STO         (20)
+#define SIGNAL_STATLOAD    (21)
+#define SIGNAL_resStorage  (22)
+#define SIGNAL_resCounter  (23)
+#define SIGNAL_CHSclk      (24)
+#define SIGNAL_exposing    (25)

slsDetectorServers/slsDetectorServer/include/AD7689.h

@@ -11,7 +11,8 @@
  * @param dmsk digital output mask
  * @param dofst digital output offset
  */
-void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
+void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk,
+                       uint32_t clkmsk, uint32_t dmsk, int dofst);
 
 /**
  * Disable SPI

slsDetectorServers/slsDetectorServer/include/AD9252.h

@@ -10,7 +10,8 @@
  * @param dmsk digital output mask
  * @param dofst digital output offset
  */
-void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
+void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
+                       uint32_t dmsk, int dofst);
 
 /**
  * Disable SPI

slsDetectorServers/slsDetectorServer/include/AD9257.h

@@ -10,7 +10,8 @@
  * @param dmsk digital output mask
  * @param dofst digital output offset
  */
-void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
+void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
+                       uint32_t dmsk, int dofst);
 
 /**
  * Disable SPI
@@ -24,7 +25,8 @@ int AD9257_GetVrefVoltage(int mV);
 
 /**
  * Set vref voltage
- * @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3 for 1.6V, 4 for 2.0V
+ * @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3
+ * for 1.6V, 4 for 2.0V
  * @returns ok or fail
  */
 int AD9257_SetVrefVoltage(int val, int mV);

slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h

@@ -15,7 +15,9 @@
  * @param wd2msk write parameter mask for pll for dbit clock (Jungfrau only)
  * @param clk2Index clkIndex of second pll (Jungfrau only)
  */
-void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst, uint32_t wd2msk, int clk2Index);
+void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
+                           uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
+                           int aofst, uint32_t wd2msk, int clk2Index);
 #else
 /**
  * Set Defines
@@ -27,7 +29,9 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
  * @param amsk address mask
  * @param aofst address offset
  */
-void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst);
+void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
+                           uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
+                           int aofst);
 #endif
 
 /**
@@ -44,9 +48,11 @@ void ALTERA_PLL_ResetPLLAndReconfiguration ();
  * Set PLL Reconfig register
  * @param reg register
  * @param val value
- * @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR mask)
+ * @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR
+ * mask)
  */
-void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMask);
+void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
+                                  int useSecondWRMask);
 
 /**
  * Write Phase Shift
@@ -68,4 +74,3 @@ void ALTERA_PLL_SetModePolling();
  * @param frequency set
  */
 int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value);
-

slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h

@@ -14,7 +14,10 @@
  * @param vcofreq0 vco frequency of pll 0
  * @param vcofreq1 vco frequency of pll 1
  */
-void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0, uint32_t baseaddr1, uint32_t resetreg0, uint32_t resetreg1, uint32_t resetmsk0, uint32_t resetmsk1, int vcofreq0, int vcofreq1);
+void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0,
+                               uint32_t baseaddr1, uint32_t resetreg0,
+                               uint32_t resetreg1, uint32_t resetmsk0,
+                               uint32_t resetmsk1, int vcofreq0, int vcofreq1);
 
 /**
  * Get Max Clock Divider
@@ -53,13 +56,13 @@ void ALTERA_PLL_C10_ResetPLL (int pllIndex);
  * @param phase phase shift
  * @param pos 1 if up down direction of shift is positive, else 0
  */
-void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos);
+void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase,
+                                  int pos);
 
 /**
  * Calculate and write output frequency
  * @param pllIndex pll index
  * @param clkIndex clock index
- * @param value frequency in Hz to set to
+ * @param value clock divider to set to
  */
-void ALTERA_PLL_C10_SetOuputFrequency (int pllIndex, int clkIndex, int value);
-
+void ALTERA_PLL_C10_SetOuputClockDivider(int pllIndex, int clkIndex, int value);

slsDetectorServers/slsDetectorServer/include/DAC6571.h

@@ -15,6 +15,3 @@ void DAC6571_SetDefines(int hardMaxV, char* driverfname);
  * @return OK or FAIL
  */
 int DAC6571_Set(int val);
-
-
-

slsDetectorServers/slsDetectorServer/include/I2C.h

@@ -15,9 +15,9 @@
  * @param sdreg sda hold register (defined in RegisterDefs.h)
  * @param treg transfer command fifo register (defined in RegisterDefs.h)
  */
-void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
-        uint32_t rreg, uint32_t rlvlreg,
-        uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
+void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
+                          uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
+                          uint32_t sdreg, uint32_t treg);
 
 /**
  * Read register
@@ -34,5 +34,3 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr);
  * @param data data to be written (16 bit)
  */
 void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data);
-
-

slsDetectorServers/slsDetectorServer/include/INA226.h

@@ -4,7 +4,8 @@
 
 /**
  * Configure the I2C core and Enable core
- * @param rOhm shunt resister value in Ohms (defined in slsDetectorServer_defs.h)
+ * @param rOhm shunt resister value in Ohms (defined in
+ * slsDetectorServer_defs.h)
  * @param creg control register (defined in RegisterDefs.h)
  * @param sreg status register (defined in RegisterDefs.h)
  * @param rreg rx data fifo register (defined in RegisterDefs.h)
@@ -15,8 +16,8 @@
  * @param treg transfer command fifo register (defined in RegisterDefs.h)
  */
 void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
-        uint32_t rreg, uint32_t rlvlreg,
-        uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
+                             uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
+                             uint32_t shreg, uint32_t sdreg, uint32_t treg);
 
 /**
  * Calibrate resolution of current register

slsDetectorServers/slsDetectorServer/include/LTC2620.h

@@ -9,11 +9,13 @@
  * @param clkmsk clock output mask
  * @param dmsk digital output mask
  * @param dofst digital output offset
- * @param nd total number of dacs for this board (for dac channel and daisy chain chip id)
+ * @param nd total number of dacs for this board (for dac channel and daisy
+ * chain chip id)
  * @param minMV minimum voltage determined by hardware
  * @param maxMV maximum voltage determined by hardware
  */
-void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
+void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
+                        uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
 
 /**
  * Disable SPI
@@ -84,7 +86,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex);
 
 /**
  * Sets a single chip (LTC2620_SetSingle) or multiple chip (LTC2620_SetDaisy)
- * multiple chip is only for ctb where the multiple chips are connected in daisy fashion
+ * multiple chip is only for ctb where the multiple chips are connected in daisy
+ * fashion
  * @param cmd command to send
  * @param data dac value to be set
  * @param dacaddr dac channel number for the chip

slsDetectorServers/slsDetectorServer/include/LTC2620_Driver.h

@@ -10,7 +10,6 @@
  */
 void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs);
 
-
 /**
  * Get max number of steps
  */
@@ -41,4 +40,5 @@ int LTC2620_D_DacToVoltage(int dacval, int* voltage);
  * @param dacval pointer to dac value
  * @return OK or FAIL
  */
-int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char* dacname, int *dacval);
+int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
+                          int *dacval);

slsDetectorServers/slsDetectorServer/include/MAX1932.h

@@ -12,8 +12,8 @@
  * @param minMV minimum voltage determined by hardware
  * @param maxMV maximum voltage determined by hardware
  */
-void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst,
-        int minMV, int maxMV);
+void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
+                        uint32_t dmsk, int dofst, int minMV, int maxMV);
 
 /**
  * Disable SPI
@@ -26,6 +26,3 @@ void MAX1932_Disable();
  * @return OK or FAIL
  */
 int MAX1932_Set(int *val);
-
-
-

slsDetectorServers/slsDetectorServer/include/blackfin.h

@@ -1,7 +1,7 @@
 #pragma once
 
-#include <sys/types.h>
 #include <inttypes.h>
+#include <sys/types.h>
 
 /** I2C defines */
 #define I2C_CLOCK_MHZ (131.25)

slsDetectorServers/slsDetectorServer/include/clogger.h

@@ -2,10 +2,9 @@
 
 #include "ansi.h"
 
-#include <stdlib.h>
-#include <stdio.h>
 #include <stdarg.h>
-
+#include <stdio.h>
+#include <stdlib.h>
 
 #ifdef FIFODEBUG
 #define FILELOG_MAX_LEVEL logDEBUG5
@@ -22,30 +21,69 @@
 #endif
 
 enum TLogLevel {
-logERROR, logWARNING, logINFOBLUE, logINFOGREEN, logINFORED, logINFO,
-logDEBUG, logDEBUG1, logDEBUG2, logDEBUG3, logDEBUG4, logDEBUG5
+    logERROR,
+    logWARNING,
+    logINFOBLUE,
+    logINFOGREEN,
+    logINFORED,
+    logINFO,
+    logDEBUG,
+    logDEBUG1,
+    logDEBUG2,
+    logDEBUG3,
+    logDEBUG4,
+    logDEBUG5
 };
 
 #define ERROR_MSG_LENGTH 1000
 
 #define LOG(lvl, fmt, ...)                                                     \
-	if (lvl > FILELOG_MAX_LEVEL);				\
-	else {char* temp = FILELOG_BuildLog fmt; FILELOG_PrintLog(lvl, temp);free(temp);}
+    if (lvl > FILELOG_MAX_LEVEL)                                               \
+        ;                                                                      \
+    else {                                                                     \
+        char *temp = FILELOG_BuildLog fmt;                                     \
+        FILELOG_PrintLog(lvl, temp);                                           \
+        free(temp);                                                            \
+    }
 
 static inline void FILELOG_PrintLog(enum TLogLevel level, char *m) {
     switch (level) {
-	case logERROR: 		cprintf(RED BOLD, "ERROR: %s", m);		break;
-	case logWARNING:	cprintf(YELLOW BOLD, "WARNING: %s", m);	break;
-	case logINFOBLUE: 	cprintf(BLUE, "INFO: %s", m);			break;
-	case logINFOGREEN:	cprintf(GREEN, "INFO: %s", m);			break;
-    case logINFORED:    cprintf(RED, "INFO: %s", m);            break;
-	case logINFO: 		cprintf(RESET, "INFO: %s", m);			break;
-	case logDEBUG: 		cprintf(MAGENTA, "DEBUG: %s", m);		break;
-	case logDEBUG1: 	cprintf(MAGENTA, "DEBUG1: %s", m);		break;
-	case logDEBUG2: 	cprintf(MAGENTA, "DEBUG2: %s", m);		break;
-	case logDEBUG3: 	cprintf(MAGENTA, "DEBUG3: %s", m);		break;
-	case logDEBUG4: 	cprintf(MAGENTA, "DEBUG4: %s", m);		break;
-	case logDEBUG5: 	cprintf(MAGENTA, "DEBUG5: %s", m);		break;
+    case logERROR:
+        cprintf(RED BOLD, "ERROR: %s", m);
+        break;
+    case logWARNING:
+        cprintf(YELLOW BOLD, "WARNING: %s", m);
+        break;
+    case logINFOBLUE:
+        cprintf(BLUE, "INFO: %s", m);
+        break;
+    case logINFOGREEN:
+        cprintf(GREEN, "INFO: %s", m);
+        break;
+    case logINFORED:
+        cprintf(RED, "INFO: %s", m);
+        break;
+    case logINFO:
+        cprintf(RESET, "INFO: %s", m);
+        break;
+    case logDEBUG:
+        cprintf(MAGENTA, "DEBUG: %s", m);
+        break;
+    case logDEBUG1:
+        cprintf(MAGENTA, "DEBUG1: %s", m);
+        break;
+    case logDEBUG2:
+        cprintf(MAGENTA, "DEBUG2: %s", m);
+        break;
+    case logDEBUG3:
+        cprintf(MAGENTA, "DEBUG3: %s", m);
+        break;
+    case logDEBUG4:
+        cprintf(MAGENTA, "DEBUG4: %s", m);
+        break;
+    case logDEBUG5:
+        cprintf(MAGENTA, "DEBUG5: %s", m);
+        break;
     }
     fflush(stdout);
 }
@@ -58,11 +96,9 @@ static inline char* FILELOG_BuildLog(const char* fmt, ...) {
     int ret = vsnprintf(p, ERROR_MSG_LENGTH, fmt, ap);
     va_end(ap);
     if (ret < 0 || ret >= ERROR_MSG_LENGTH) {
-		FILELOG_PrintLog(logERROR, ("Could not print the "
+        FILELOG_PrintLog(logERROR,
+                         ("Could not print the "
                           "complete error message in the next print.\n"));
     }
     return p;
 };
-
-
-