255 Commits

Author SHA1 Message Date
Erik Fröjdh
2f2fe4dd47
Release of 5.1.0 (#237)
* Setting pattern from memory (#218)

* ToString accepts c-style arrays

* fixed patwait time bug in validation

* Introduced pattern class

* compile for servers too

* Python binding for Pattern

* added scanParameters in Python

* slsReceiver: avoid potential memory leak around Implementation::generalData

* additional constructors for scanPrameters in python

* bugfix: avoid potentital memory leak in receiver if called outside constructor context

* added scanParameters in Python

* additional constructors for scanPrameters in python

* M3defaultpattern (#227)

* default pattern for m3 and moench including Python bindings

* M3settings (#228)

* some changes to compile on RH7 and in the server to load the default chip status register at startup

* Updated mythen3DeectorServer_developer executable with correct initialization at startup

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>

* Pattern.h as a public header files (#229)

* fixed buffer overflow but caused by using global instead of local enum

* replacing out of range trimbits with edge values

* replacing dac values that are out of range after interpolation

* updated pybind11 to 2.6.2

* Mythen3 improved synchronization (#231)

Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master

* New server for JF to go with the new FW (#232)

* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218

* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.

* fix for m3 scan with single module

* m3 fw version

* m3 server

* bugfix for bottom when setting quad

* new strategy for finding zmq based on cppzmq



Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com>
Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com>
Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
2021-03-22 14:43:11 +01:00
8be579ea53 binaries name changed 2020-11-17 18:41:18 +01:00
73d582744e updated binaries for 5.0.0 2020-11-17 16:49:03 +01:00
980d76a15a binaries in 2020-11-17 11:03:16 +01:00
121450b8cc binaries in 2020-11-17 11:02:23 +01:00
Dhanya Thattil
a6d696a0f8
Nextframenumber (#215) 2020-11-16 17:26:12 +01:00
Dhanya Thattil
4c4e2ccb6b
Defaultdacs (#214) 2020-11-13 08:31:02 +01:00
98fce317a8 binaries in 2020-11-02 16:39:06 +01:00
6838666802 Revert "updating sls subfolder in normal server bianries"
This reverts commit 420343eb31df0eef07c4c194e7428f5c7f0589d1.
2020-11-02 16:36:10 +01:00
420343eb31 updating sls subfolder in normal server bianries 2020-11-02 16:34:23 +01:00
Erik Fröjdh
a15d8dd30a
Moving headers into include/sls (#212) 2020-11-02 16:05:28 +01:00
f6189072bc binaries in 2020-10-27 18:17:37 +01:00
453908c7cb m3 and g2: bugfix to close fd in server after reading detector type 2020-10-27 18:16:42 +01:00
Dhanya Thattil
47018b61cd
M3readout (#209)
* m3: readout command
2020-10-26 16:13:48 +01:00
b31f8a5ca6 binary in 2020-10-20 12:05:18 +02:00
f4a2702996 m3: exptime and gatedelay values set from reg variables but not converted to time first 2020-10-20 12:03:46 +02:00
a86d70235c binaries in 2020-10-16 15:03:56 +02:00
fddc93ba8d binaries in 2020-10-15 09:28:41 +02:00
ae960fcb57 WIP 2020-10-15 09:28:17 +02:00
9f2bc85a18 m3: trigger enable moved to config reg, always enabling trigger flow for all timing modes for m3 2020-10-15 09:27:06 +02:00
12abf3e58b binary in 2020-10-09 17:56:36 +02:00
6ddde13b87 m3: exptime and gate delay registers 1 2 3 are updated only if counters enabled, when counters enabled, the registers are updated back 2020-10-09 17:54:35 +02:00
a310ab9bfa updated all servers 2020-10-09 16:59:46 +02:00
904d10eb43 wip 2020-10-09 16:54:46 +02:00
e364fbcf32 m3: changed run clk div to 10, change run clkdiv to 40 while trimming, set default pipeline adif reg 2020-10-09 16:52:24 +02:00
e0e2c2efba updated binaries 2020-10-08 15:55:24 +02:00
33d85dbfc0 all servers compiled 2020-10-08 15:45:29 +02:00
5c0dff29ed binaries in 2020-10-07 12:27:35 +02:00
c2d9532a69 updated versionign server color minor 2020-10-05 09:56:47 +02:00
7855005590 updated 5.0.0-rc2 in binaries 2020-10-05 09:53:13 +02:00
b2f5208745 binaries in 2020-10-02 11:19:19 +02:00
91efecd4ca servers: updated fw-sw api version check error message, m3 and g2: updated min fw version 2020-10-02 11:17:11 +02:00
2d104d9a9b setting 1 giga mode as default for virtual mythen3 2020-09-29 15:51:22 +02:00
b421a73c3d m3: virtual servers for switching to 1 giga (stop server does not know dr) 2020-09-28 17:27:56 +02:00
Dhanya Thattil
3f19f29c9e
G2ContTrigger (#188)
* g2: setting #frames  to 1 and period to 0 for cont trigger, extra frame reg is set to #frames for cont auto and #trigger for cont trigger
2020-09-24 11:59:11 +02:00
1515b79c97 Merge branch 'kernelcheck' of github.com:slsdetectorgroup/slsDetectorPackage into kernelcheck 2020-09-11 08:50:01 +02:00
2ab4bb1c04 minor 2020-09-11 08:49:52 +02:00
5214c0f1a4 binaries in 2020-09-10 18:43:26 +02:00
60bc3a8fa7 Merge branch 'kernelcheck' of github.com:slsdetectorgroup/slsDetectorPackage into kernelcheck 2020-09-10 18:41:49 +02:00
00f780665f using common.c to extract date and using nios.c to check kernel version(a bit specific to nios) and using c api instead of system command to get uname 2020-09-10 18:41:31 +02:00
88fe306902 binaries in 2020-09-10 16:23:29 +02:00
d931416def g2 and m3: kernel checks only when its too old 2020-09-10 16:22:08 +02:00
80b053eb10 binaries resolved, merge conflict from developer 2020-09-10 10:19:34 +02:00
Dhanya Thattil
3cd4f3897b
M3: software trigger (#175) 2020-09-10 10:15:45 +02:00
52303daffd binaries in 2020-09-09 16:44:23 +02:00
a9d1a78662 m3:smp_clk (timing rxr) changed back to clk div 5 2020-09-09 15:55:13 +02:00
3cf2160a2d binaries in 2020-09-09 15:25:48 +02:00
b33fdf4462 merge conflict fixed and merged with developer 2020-09-09 12:31:36 +02:00
6c8443f09e binaries in 2020-09-09 12:14:38 +02:00
97687f0f6d binary in 2020-09-08 17:33:06 +02:00