Dhanya Thattil
c64b09ee79
Jungfraufix ( #84 )
...
* jungfrau: added dbitphase, different pll clkindex 0 with different wr bit
2020-03-04 17:06:18 +01:00
6bbcf6173d
moench: first version
2020-03-02 18:34:10 +01:00
2e2e91b219
ctb adc: get in uV and print in client in mV to get decimals
2020-02-27 15:43:42 +01:00
8c8032dc69
ctb bug fix: slow adcs incorrect mv read out, needed clk down and usleep before reading
2020-02-27 09:16:22 +01:00
Erik Frojdh
a829e69313
minor
2020-02-03 16:00:24 +01:00
f0cccf9de8
initialchecks can be bypassed (version compatibility and oher tests at server start up)
2020-01-31 16:46:33 +01:00
Dhanya Thattil
5ca3a1b685
gotthard2 and mythen3: programming fpga, reboot; jungfrau, ctb: modified programming ( #74 )
2020-01-30 19:52:35 -08:00
a9e375ed34
gotthard2: bursttype to burstmode
2020-01-23 11:03:14 +01:00
f881133795
get/set timing, generate data for gotthard2, vref_rstore instead of restore for gotthard2
2020-01-22 18:18:56 +01:00
8cbf3c62a9
merge from developer
2020-01-22 17:30:13 +01:00
981b13494c
mythen3: virtual server, connected timing mode, row and col in header, included pattern bit and mask
2020-01-21 18:16:27 +01:00
e746256653
gotthard2: gain updated
2020-01-21 16:01:38 +01:00
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
b6d9015ed0
rearranging
2020-01-15 15:08:01 +01:00
Dhanya Thattil
de53747ddd
Counters ( #71 )
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* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2020-01-14 17:40:46 +01:00
Erik Frojdh
f4cdd759b0
clang-tidy
2019-11-27 18:42:16 +01:00
Erik Frojdh
d53082c615
clang-tidy empty()
2019-11-27 18:15:55 +01:00
Erik Frojdh
e996068328
more tests
2019-11-27 13:39:06 +01:00
Erik Fröjdh
fa2c842745
New command line app and removing slsDetectorCommand ( #69 )
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* WIP
* WIP
* WIP
* WIP
* config2 working
* removed slsDetectorCommand
* WIP
* added test file
* more tests
2019-11-18 09:29:17 +01:00
6a27207875
gotthard2: vetoref, burstmode
2019-11-15 18:59:27 +01:00
5518531620
gotthard2: veto reference
2019-11-14 19:01:10 +01:00
28a5aa8342
injectchannel WIP
2019-11-13 15:11:11 +01:00
615b3b2557
WIP
2019-11-06 19:07:00 +01:00
1797d39216
updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
2019-11-06 18:58:22 +01:00
1f64d2a4e2
speed separated
2019-11-05 18:50:35 +01:00
4aba8b6ac0
daclist and dacvalues for ctb as well
2019-10-30 11:38:29 +01:00
82570bc084
daclist and dacvalues
2019-10-30 11:09:34 +01:00
798f221764
WIP
2019-10-29 10:07:07 +01:00
4155e301b8
WIP
2019-10-28 16:48:13 +01:00
8c279695de
WIP
2019-10-28 16:27:20 +01:00
3fdae431b0
WIP
2019-10-28 15:47:18 +01:00
7b59b7e7d5
WIP
2019-10-28 12:26:30 +01:00
61d7c76d55
WIP
2019-10-28 11:34:58 +01:00
93bb0c9aed
WIP
2019-10-28 11:17:27 +01:00
f9d832bf34
WIP
2019-10-24 19:39:58 +02:00
5a49182626
WIP
2019-10-24 19:20:55 +02:00
f4a0780b51
patloops done
2019-10-24 18:59:23 +02:00
f73a15e786
tests made to pass ctb
2019-10-24 11:32:58 +02:00
fa84d17a19
gotthard tests passed
2019-10-22 17:07:38 +02:00
8006043a97
bug fixes for tests
2019-10-22 15:46:28 +02:00
Dhanya Thattil
995f0924e5
Commandline ( #66 )
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* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
2019-10-21 10:29:06 +02:00
be50344b45
set clock divider, phase and get clock freq for gotthard2, priliminary
2019-10-17 16:39:41 +02:00
Erik Fröjdh
9a48d9b832
Intcmd ( #53 )
...
* migrated more
* more
2019-08-23 17:39:41 +02:00
Erik Frojdh
2c5ff0e9bf
fixed output
2019-08-23 15:44:47 +02:00
Erik Fröjdh
5c06549982
Cleanup of the CmdProxy and migrated some commands ( #52 )
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* migrated rx_fifodepth
* Moved and cleand CmdProxy
* rx_slient
* new commands
* examples
* fixed result string print
2019-08-23 14:32:44 +02:00