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e0f686231a
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wip
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2021-09-02 15:37:28 +02:00 |
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a51deda2a4
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moduleid for eiger m3 and g2, but set only for g2
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2021-09-01 17:06:34 +02:00 |
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25d03f949e
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partialread changed to readnrows
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2021-08-31 16:46:49 +02:00 |
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861c81d57a
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wip
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2021-08-31 14:42:36 +02:00 |
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1d989637e9
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udp_firstdst for jungfrau
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2021-08-25 14:27:06 +02:00 |
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ab59f7db7b
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added udp_numdst
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2021-08-19 15:50:02 +02:00 |
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f8d8fcf48a
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wipg
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2021-08-18 19:05:05 +02:00 |
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c4c16ad9c0
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wip
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2021-08-17 14:05:59 +02:00 |
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f72f678d45
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Merge branch 'developer' into roundrobin
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2021-08-17 11:06:13 +02:00 |
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5790e4961b
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wip
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2021-08-13 17:10:46 +02:00 |
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62d697e91f
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readnlines->partialread, better debugging for TCP socket interface bug
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2021-08-13 12:34:50 +02:00 |
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ec01f98c26
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wip
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2021-08-12 17:37:55 +02:00 |
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200df88dcf
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module id instead of serial number
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2021-08-12 11:16:10 +02:00 |
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6f54402aba
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g2: setting serialnumber allowed
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2021-08-11 18:50:49 +02:00 |
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9a777b13bb
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g2: dbitpipeline
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2021-08-11 18:01:28 +02:00 |
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fce35e35a1
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wip
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2021-08-10 17:26:26 +02:00 |
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dd3f2db3c5
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binaries in, merge fix
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2021-08-06 16:18:28 +02:00 |
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4986a5e61a
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Merge branch 'j13flippeddatax' into j7filter
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2021-08-06 16:16:46 +02:00 |
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e62fc1907f
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binaries in, merge fix
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2021-08-06 16:16:25 +02:00 |
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cc3aede979
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merge fix
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2021-08-06 16:11:58 +02:00 |
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2c53a134cd
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updated i3gbe to lll
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2021-08-06 16:08:07 +02:00 |
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2934ccbf2c
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filter cell (only chipv1.1)
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2021-08-06 14:42:41 +02:00 |
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86126c7e27
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filter resistor in
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2021-08-05 16:56:53 +02:00 |
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619f3b71c1
|
flippeddataoverxaxis changed to flipRows
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2021-08-05 14:44:25 +02:00 |
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c5d6dd0dd4
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flippeddatax for jungfrau server
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2021-08-05 12:39:04 +02:00 |
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9c4ecf0506
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jungfrau: comp disable time
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2021-08-03 13:12:58 +02:00 |
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9ed3a294ce
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jungfrau: gainmode
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2021-08-02 12:44:57 +02:00 |
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9c03e83ef1
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reset default dacs
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2021-07-29 16:34:38 +02:00 |
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de7f4489af
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defaultdac upto detector side, settings is undefined when none given
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2021-07-28 20:11:58 +02:00 |
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cb293f9945
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j: 1. chipversion
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2021-07-22 16:48:35 +02:00 |
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05b7e0ef42
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conflict merge fix
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2021-07-22 11:53:00 +02:00 |
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da996314e7
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merge conflict
|
2021-07-22 11:15:57 +02:00 |
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ec7ba7c508
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wip to change to enum for portposition
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2021-07-20 16:05:08 +02:00 |
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e02493d4e4
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veotalg for g2
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2021-07-20 14:57:31 +02:00 |
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af16ad4040
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vetoalg: wip
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2021-07-20 12:58:05 +02:00 |
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780d4bfe0a
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gotthard2: vetostream (detector: only 3gbe, 10gbe via numudpinterfaces)
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2021-07-15 16:21:17 +02:00 |
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fdf6632356
|
wip
|
2021-07-05 15:20:34 +02:00 |
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cbdb05a3a8
|
wip
|
2021-07-01 15:11:22 +02:00 |
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18fe63f594
|
wip
|
2021-06-28 13:32:44 +02:00 |
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8b22b5dbe7
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wip
|
2021-06-25 17:13:40 +02:00 |
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1b525abfa1
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wip
|
2021-06-25 17:11:36 +02:00 |
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61c5018a46
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wip
|
2021-06-23 10:28:14 +02:00 |
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755738a42e
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wip
|
2021-06-22 20:50:50 +02:00 |
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b11f6c56e7
|
getmaster through stop server, allowing stopacq to first go to slave for eiger, eiger stop to first check reg value to send complete frames before calling stop
|
2021-06-15 12:59:54 +02:00 |
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0afe093afc
|
wip
|
2021-06-04 12:30:59 +02:00 |
|
Erik Frojdh
|
085ea3aee7
|
dont add detector id for .trim
|
2021-04-27 08:28:05 +02:00 |
|
Erik Frojdh
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be5fee8126
|
M3: fixed gain bits with negative polarity
|
2021-04-12 16:44:47 +02:00 |
|
Erik Frojdh
|
01c785271f
|
WIP
|
2021-03-31 16:26:36 +02:00 |
|
Erik Frojdh
|
043d582616
|
initial implementation
|
2021-03-29 14:21:48 +02:00 |
|
Erik Frojdh
|
7c4f9ee044
|
read back of csr
|
2021-03-26 17:46:11 +01:00 |
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