* g2: new hdi values, write hdi value to reg, set slave/master to reg, able to set master from server config file, server command line and client
* print versions for virtual as well
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* python working
* import fix
* changed fw version for ctb and moench. binaries in
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
* vicin default changed to 800, only setting vthx directly allows to set dac even if counter disabled, else disable counter, setallthresholdenergy if an energy is -1, get module value, fix that reg was repaced by isettings
* vth3 disabled for interpolation enable, interpolation disable sets counter mask to what it was before (updating old mask whn setting counter mask except for setting all counters for interpolation enable) and enabling vth3 if counter was enabled
* refactor and test for previous commit
* pump probe only has vth2 enabled, handles both pump probe mode and interpolation mode as well
* wip
* refactored pump probe and interpolation and added to setmodule
* check dacs and trimbits out of range for setmodule (not just threshold)
* binaries in
* m3: pump probe and interpolation mutually exclusive
* minor
* added the possibility to save settings file for m3 and eiger
* added save trimbits to gui
* update release notes
* python wip
* moved location of trimbits save option in gui
* python works
* updating getModule with all its parameters in the server side
* updating binaries
* wip, adding m3 functions: polarity, inerpolation, pumpprobe
* added interpol, polarity, pump probe, analog pulsing, digital pulsing
* tests
* binaries in
* update release
* added python polarity enum
* fixed python and minor readability in mythen3.c
* binarie sin
* added all the m3 funcs also in list.c and enablingall counters for enabling interpolation
* binarie sin
# Setting DAC names for CTB
* Introduced new shared memory for CTB only
* Prepared for additional functionality
* Works from C++ and Python
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
- progress looks at activated or enabled ports, so progress does not stagnate
- (eiger) disable datastreaming also for virtual servers only for 10g
- missing packets also takes care of disabled ports
* test for rx_arping
* arping ip and interface from client interface
* apring thread added to thread ids
* clean code for thread for arping
* removing the assumption that udpip1 fill be updated along with udpip2
* review, replacing syscall(sys_gettid) with gettid()
