Dhanya Thattil
758afad02c
ctb, moench, eiger, gotthard: get number of channels for moench and ctb, others removed unnecessary variables in shm, added moench virtual sever ( #86 )
2020-03-10 09:08:08 +01:00
Dhanya Thattil
11e7737a2f
gotthard2: timingsource and currentsource features, (timing source external yet to be implemented in fpga to test ( #80 )
2020-02-28 12:45:02 +01:00
6a0a931e3e
gotthard2: bursts and burst period, written to same register as triggers and delay (kept in server as variables) and set if conditions meet. bursts and burst period only in auto timing and burst mode. Also updating theses registers when switching between timing modes or burst modes
2020-02-25 15:45:40 +01:00
a9e375ed34
gotthard2: bursttype to burstmode
2020-01-23 11:03:14 +01:00
6cfd0f8962
gotthard2: first edit
2020-01-20 12:13:23 +01:00
Dhanya Thattil
de53747ddd
Counters ( #71 )
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* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2020-01-14 17:40:46 +01:00
9455a5fba1
ctb: adcenable10g included, 10g readout enables included
2019-11-27 17:28:57 +01:00
398f3734ec
rxr: missing packets, stopacquistion lets rxr know to calculate missing packets from last frame caught
2019-11-20 16:16:14 +01:00
6a27207875
gotthard2: vetoref, burstmode
2019-11-15 18:59:27 +01:00
5518531620
gotthard2: veto reference
2019-11-14 19:01:10 +01:00
28a5aa8342
injectchannel WIP
2019-11-13 15:11:11 +01:00
d7e2ab8ec4
gotthard2: on chip dacs
2019-11-08 17:09:57 +01:00
18b8720c17
separated parameters and versions
2019-11-06 16:43:59 +01:00
1f64d2a4e2
speed separated
2019-11-05 18:50:35 +01:00
031241ae28
timer split up
2019-11-04 16:40:11 +01:00
4b2cb7ecc1
WIP
2019-10-29 11:35:25 +01:00
f4a0780b51
patloops done
2019-10-24 18:59:23 +02:00
be50344b45
set clock divider, phase and get clock freq for gotthard2, priliminary
2019-10-17 16:39:41 +02:00
Dhanya Thattil
ca054626e6
Removeudpcache ( #65 )
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* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* solved eiger 1-10g issue
* some fixes for remove udp cache to work
* bug fix virtual
* removed special handling of rx_udpip
2019-09-30 14:46:25 +02:00
Dhanya Thattil
5bcde789ac
Readoutflags ( #61 )
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* WIP
* eiger binary back wih versioning
* fixed readout flag in ctbgui, added speedLevel enum
* ctbgui: fixed a print out error
* ctb readout bug fix
* WIP
* WIP
* WIP
2019-09-02 19:27:27 +02:00
28963e313b
removed gotthard functions not used
2019-08-20 18:18:34 +02:00
a0bdfcdae3
WIP
2019-08-16 17:38:41 +02:00
d4d8cbe9bc
gotthard fixed roi only xmin and xmax.remove updateoffsets
2019-08-14 09:20:50 +02:00
Dhanya Thattil
98ddf154b2
Partialreadout ( #47 )
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* eiger server, rxr: partial readout, also gui messages: up last command, down clear command
* added binaries and resolved conflict
* bugfix eiger server: interrupt subframe is bit 2 and not bit number 3
* brackets in defs
2019-08-07 09:08:58 +02:00
Dhanya Thattil
d72b6c3659
eiger server: quad, interrupt subframe, reg left and right ( #45 )
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* eiger server: quad, interrupt subframe, reg left and right
* eiger server: beb can fail in setting up quad, quad and gap pixels
2019-08-06 10:12:34 +02:00
Dhanya Thattil
e7a76ccea1
Quad ( #39 )
...
* making quad work in developer branch
* binary added
* minor changes
* bug fix to set quad to 0 when more than 1 detector
2019-07-22 16:41:03 +02:00
Dhanya Thattil
29141ac1a6
set starting frame number of next acquisition for both jungfrau and e… ( #27 )
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* set starting frame number of next acquisition for both jungfrau and eiger. firmware has not implemented a get, so workaround. tests included. frame number 0 not allowed due to Eiger. Eiger max frame is 48 bit, while jungfrau is 64 bit
* made argument of setstartingframenumber const
2019-06-03 11:07:53 +02:00
e14519c236
slsReceiver: removed special receiver config, added rx_dbitlist, rx_dbitoffset to put bits together in file, connected adcinvert, extsamplingsrc and extsampling properly to the detector, added tests
2019-05-03 20:37:40 +02:00
b0cffcd570
master file option, adcdisable changed to adcenable
2019-04-30 12:13:28 +02:00
61a939ef53
ctb: removed setroi, instead using adcenablemask
2019-04-26 16:53:23 +02:00
266520741a
ctb patterns interface rewritten
2019-04-18 15:29:43 +02:00
89a06f099c
merging refactor (replacing)
2019-04-12 10:53:09 +02:00
