* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers
* added parallel command
* remove gain plot for moench
* moench: updated adc invert val
* moench: update adcoffset to 0xf and adcphase to 140 degrees
* removed sync clock in moench
* updated min fw version
* removing config file in moench server
* copied jungfrau server to moench and adapted
* fixed image size and num packets
* read n rows allows 16
* commneted out configure_asic_timer at server startup. To be removed later the ASIC_CTRL_REG and storage cell options
* moench:removing the decrement (which was in jf) in read n rows to register
* removed lblsamples from gui
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* python working
* import fix
* changed fw version for ctb and moench. binaries in
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
